diff options
Diffstat (limited to 'regtests/jedutil/eqns/WinCUPL')
6 files changed, 558 insertions, 0 deletions
diff --git a/regtests/jedutil/eqns/WinCUPL/atf22v10/atf22v10_power_down_mode.pld b/regtests/jedutil/eqns/WinCUPL/atf22v10/atf22v10_power_down_mode.pld new file mode 100644 index 00000000000..ff81d877397 --- /dev/null +++ b/regtests/jedutil/eqns/WinCUPL/atf22v10/atf22v10_power_down_mode.pld @@ -0,0 +1,123 @@ +Name ATF22V10 Power Down Mode Test ; +PartNo 00 ; +Date 5/6/2020 ; +Revision 01 ; +Designer MAME ; +Company MAME ; +Assembly None ; +Location ; +Device G22V10CP ; + +/* Power Down Mode Test */ + +/* Input Pins (Pin 4 not allowed for input, but instead triggers power down mode.) */ +PIN 1 = [I1] ; +PIN 2 = [I2] ; +PIN 3 = [I3] ; +PIN 5 = [I5] ; +PIN 6 = [I6] ; +PIN 7 = [I7] ; +PIN 8 = [I8] ; +PIN 9 = [I9] ; +PIN 10 = [I10] ; +PIN 11 = [I11] ; +PIN 13 = [I13] ; +PIN 14 = [I14] ; +PIN 23 = [I23] ; + +/* Output Pins */ +PINNODE 15 = [O15] ; +PINNODE 16 = [O16] ; +PINNODE 17 = [O17] ; +PINNODE 18 = [O18] ; +PINNODE 19 = [O19] ; +PINNODE 20 = [O20] ; +PINNODE 21 = [O21] ; +PINNODE 22 = [O22] ; + +/* Logic Equations */ + +ASYNC_RESET = !I2 & O15 & !O16 & O17 & !O18; +SYNC_PRESET = O19 & !O20 & O21 & !O22 & I23; + +O15 = I1 & !I2 # + I3 # + !I5 & I6 & I7 & !I8 & I9 # + !I10 & !I11 # + I13 # + I14 # + I23; +O15.oe = !I23; +O15.AR = ASYNC_RESET; +O15.SP = SYNC_PRESET; + +O16 = I1 & I2 & I3 & I5 # + I6 & I7 & I8 & I9 & I10 # + I13 # + I14 & !O21 # + I23 # + !I5 & O17 & O18 # + !I2; +O16.AR = ASYNC_RESET; +O16.SP = SYNC_PRESET; + +O17 = !I7 & O21 # + I8 # + !I3 # + !I1 & !I2 & I3 # + !I5 # + !I6 & !I7 & !I8 & !I9 & !I10 # + !O18; +O17.AR = ASYNC_RESET; +O17.SP = SYNC_PRESET; + +!O18 = I1 # + I3 # + I5 # + I7 # + I9 # + I11 # + I13; +O18.AR = ASYNC_RESET; +O18.SP = SYNC_PRESET; + +O19 = !I13 # + !I11 # + !I9 # + !I7 # + !I5 # + !I3 # + !I1; +O19.AR = ASYNC_RESET; +O19.SP = SYNC_PRESET; + +O20 = I6 # + I13 & O19 # + I1 & !I7 # + O18 # + I9 & !I13 # + I14 & !O17 # + !O16; +O20.AR = ASYNC_RESET; +O20.SP = SYNC_PRESET; + +!O21 = !I1 & I2 # + !I3 # + I5 & !I6 & !I7 & I8 & !I9 # + I10 & I11 # + !I13 # + !I14 # + !I23; +O21.oe = !I23; +O21.AR = ASYNC_RESET; +O21.SP = SYNC_PRESET; + +O22 = !I8 & I23 # + !O19 & I23 # + !O18 # + O17 # + O16 # + !I2 & I8 & I14 # + !I2 & !I6 & !I8 & !I10 & !I14; +O22.AR = ASYNC_RESET; +O22.SP = SYNC_PRESET; diff --git a/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_complex_mode.pld b/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_complex_mode.pld new file mode 100644 index 00000000000..66bcd965902 --- /dev/null +++ b/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_complex_mode.pld @@ -0,0 +1,69 @@ +Name GAL16V8 Complex Mode Test ; +PartNo 00 ; +Date 4/27/2020 ; +Revision 01 ; +Designer MAME ; +Company MAME ; +Assembly None ; +Location ; +Device G16V8A ; + +/* Complex Mode Test */ + +/* Input Pins */ +PIN 1 = [I1] ; +PIN 2 = [I2] ; +PIN 3 = [I3] ; +PIN 4 = [I4] ; +PIN 5 = [I5] ; +PIN 6 = [I6] ; +PIN 7 = [I7] ; +PIN 8 = [I8] ; +PIN 9 = [I9] ; +PIN 11 = [I11] ; +PIN 13 = [I13] ; +PIN 14 = [I14] ; +PIN 17 = [I17] ; +PIN 18 = [I18] ; + +/* Output Pins */ +PINNODE 12 = [O12] ; +PINNODE 15 = [O15] ; +PINNODE 16 = [O16] ; +PINNODE 19 = [O19] ; + +/* Logic Equations */ + +O12 = I1 & I3 & I5 & !O16 # + I7 & I9 & I11 # + I13 & O16 & I17 # + I8 & I14 & !I17 # + !I8 & !I14 # + !I1 & !I2 & !I3 & !I4 & !I5 & !I7 # + I2 & I4 & I6 & !O16 ; +O12.oe = !O15 & O16 ; + +O15 = !I1 & !I3 & !I5 # + !I7 & !I9 & !I11 # + !I13 & !I17 # + !I2 & !I4 & I13 # + I4 & I18 # + !I2 & !I4 & !I6 # + !I8 & !I14 & I17 ; + +!O16 = I17 & !I18 # + !I11 & !I13 & !I14 # + I6 & I7 & I8 & I9 # + !I1 & !I2 & !I3 & !I4 & !I5 # + I1 & I2 & I3 & I4 & I5 & I13 & !I17 # + I11 & I13 & I14 # + !I6 & !I7 & !I8 & !I9 ; + +!O19 = !I1 & !I3 # + !I5 & !I7 # + !I9 & !I11 & O15 # + !I13 & !O15 # + !I14 & I17 # + I2 & I4 & I6 # + I8 & I9 & I14 ; +O19.oe = O15 & !O16 ; diff --git a/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_registered_mode.pld b/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_registered_mode.pld new file mode 100644 index 00000000000..24fd93b105a --- /dev/null +++ b/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_registered_mode.pld @@ -0,0 +1,78 @@ +Name GAL16V8 Registered Mode Test ; +PartNo 00 ; +Date 5/1/2020 ; +Revision 01 ; +Designer MAME ; +Company MAME ; +Assembly None ; +Location ; +Device G16V8A ; + +/* Registered Mode Test */ + +/* Input Pins */ +PIN 2 = [I2] ; +PIN 3 = [I3] ; +PIN 4 = [I4] ; +PIN 5 = [I5] ; +PIN 6 = [I6] ; +PIN 7 = [I7] ; +PIN 8 = [I8] ; +PIN 9 = [I9] ; +PIN 13 = [I13] ; +PIN 17 = [I17] ; +PIN 18 = [I18] ; + +/* Output Pins */ +PINNODE 12 = [RF12] ; +PINNODE 14 = [O14] ; +PINNODE 15 = [RF15] ; +PINNODE 16 = [O16] ; +PINNODE 19 = [RF19] ; + +/* Logic Equations */ + +!RF12.D = I3 & I5 & !O16 # + I7 & I9 # + I13 & O16 & I17 # + I8 & O14 & !I17 # + !I8 & !O14 # + !I2 & !I3 & !I4 # + !I5 & !I7 # + I2 & I4 & I6 & !O16 ; + +O14 = I2 # + I3 # + I4 # + I5 # + I6 # + I7 # + I8 ; +O14.oe = I9 & RF12 & I13 & I17 & I18 ; + +RF15.D = !I3 & !I5 # + !I7 & !I9 # + !I13 & !I17 # + !I2 & !I4 & I13 # + I4 & !RF12 & I18 # + !I2 & !I4 & !I6 # + !I8 & !O14 & I17 # + I3 & RF12 & O14 ; + +!O16 = RF12 & I17 & !I18 # + !I13 & !O14 # + I6 & I7 & I8 & I9 # + !I2 & !I3 & !I4 & !I5 # + I2 & I3 & I4 & I5 & I13 & !I17 # + !RF12 & I13 & O14 # + !I6 & !I7 & !I8 & !I9 ; +O16.oe = !RF12 & O14 & !RF15 & RF19 ; + +!RF19.D = !I3 & !O14 # + !I5 & !I7 & !O16 # + !I9 & RF15 # + !I13 & !RF15 # + !O14 & I17 # + I2 & I4 & I6 & O16 # + I8 & I9 & O14 # + O14 & RF15 ; diff --git a/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_simple_mode.pld b/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_simple_mode.pld new file mode 100644 index 00000000000..acdf5f9e17a --- /dev/null +++ b/regtests/jedutil/eqns/WinCUPL/gal16v8/gal16v8_simple_mode.pld @@ -0,0 +1,81 @@ +Name GAL16V8 Simple Mode Test ; +PartNo 00 ; +Date 4/22/2020 ; +Revision 01 ; +Designer MAME ; +Company MAME ; +Assembly None ; +Location ; +Device G16V8A ; + +/* Simple Mode Test */ + +/* + NOTE: + + According to the datasheet when in Simple Mode pins 12, 13, 14, 17, 18, 19 + can be configured as combinatorial output with feedback, but WinCUPL + will not allow these pins to be fed back into a different product term. + + I'm assuming WinCUPL is wrong and not the datasheet because the GAL20V8 + device supports this configuration and WinCUPL will allow it. +*/ + +/* Input Pins */ +PIN 1 = [I1] ; +PIN 2 = [I2] ; +PIN 3 = [I3] ; +PIN 4 = [I4] ; +PIN 5 = [I5] ; +PIN 6 = [I6] ; +PIN 7 = [I7] ; +PIN 8 = [I8] ; +PIN 9 = [I9] ; +PIN 11 = [I11] ; +PIN 13 = [I13] ; +PIN 14 = [I14] ; +PIN 17 = [I17] ; +PIN 19 = [I19] ; + +/* Output Pins */ +PINNODE 12 = [O12] ; +PINNODE 15 = [O15] ; +PINNODE 16 = [O16] ; +PINNODE 18 = [O18] ; + +/* Logic Equations */ + +!O12 = I1 & I3 & I5 # + I7 & I9 & I11 # + I13 & I17 # + !I17 # + !I8 # + !I1 & !I2 & !I3 & !I4 & !I5 & !I7 # + I2 & I4 & I6 # + I8 & I14 ; + +!O15 = !I1 & !I3 & !I5 # + !I7 & !I9 & !I11 # + !I13 & !I17 # + !I2 & !I4 # + I4 # + !I2 & !I4 & !I6 # + !I8 & !I14 # + I13 & I17 ; + +O16 = !I11 & !I13 & !I14 & I17 # + I6 & I7 & I8 & I9 # + !I1 & !I2 & !I3 & !I4 & !I5 # + !I17 # + I11 & I13 & I14 # + !I6 & !I7 & !I8 & !I9 # + I1 & I2 & I3 & I4 & I5 ; + +!O18 = !I1 & !I3 # + !I5 & !I7 # + !I9 & !I11 # + !I13 & I19 # + I17 # + I2 & I4 & I6 # + I8 & I9 # + I14; diff --git a/regtests/jedutil/eqns/WinCUPL/gal22v10/gal22v10_combinatorial_mode.pld b/regtests/jedutil/eqns/WinCUPL/gal22v10/gal22v10_combinatorial_mode.pld new file mode 100644 index 00000000000..166bd718ed3 --- /dev/null +++ b/regtests/jedutil/eqns/WinCUPL/gal22v10/gal22v10_combinatorial_mode.pld @@ -0,0 +1,124 @@ +Name GAL22V10 Combinatorial Mode Test ; +PartNo 00 ; +Date 5/3/2020 ; +Revision 01 ; +Designer MAME ; +Company MAME ; +Assembly None ; +Location ; +Device G22V10 ; + +/* Combinatorial Mode Test */ + +/* Input Pins */ +PIN 1 = [I1] ; +PIN 2 = [I2] ; +PIN 3 = [I3] ; +PIN 4 = [I4] ; +PIN 5 = [I5] ; +PIN 6 = [I6] ; +PIN 7 = [I7] ; +PIN 8 = [I8] ; +PIN 9 = [I9] ; +PIN 10 = [I10] ; +PIN 11 = [I11] ; +PIN 13 = [I13] ; +PIN 14 = [I14] ; +PIN 23 = [I23] ; + +/* Output Pins */ +PINNODE 15 = [O15] ; +PINNODE 16 = [O16] ; +PINNODE 17 = [O17] ; +PINNODE 18 = [O18] ; +PINNODE 19 = [O19] ; +PINNODE 20 = [O20] ; +PINNODE 21 = [O21] ; +PINNODE 22 = [O22] ; + +/* Logic Equations */ + +ASYNC_RESET = !I2 & O15 & !O16 & O17 & !O18; +SYNC_PRESET = O19 & !O20 & O21 & !O22 & I23; + +O15 = I1 & !I2 # + I3 # + I4 & !I5 & I6 & I7 & !I8 & I9 # + !I10 & !I11 # + I13 # + I14 # + I23; +O15.oe = !I23; +O15.AR = ASYNC_RESET; +O15.SP = SYNC_PRESET; + +O16 = I1 & I2 & I3 & I4 & I5 # + I6 & I7 & I8 & I9 & I10 # + I13 # + I14 & !O21 # + I23 # + !I5 & O17 & O18 # + !I2; +O16.AR = ASYNC_RESET; +O16.SP = SYNC_PRESET; + +O17 = !I7 & O21 # + I8 # + !I3 # + !I1 & !I2 & I3 # + !I4 & !I5 # + !I6 & !I7 & !I8 & !I9 & !I10 # + !O18; +O17.AR = ASYNC_RESET; +O17.SP = SYNC_PRESET; + +!O18 = I1 # + I3 # + I5 # + I7 # + I9 # + I11 # + I13; +O18.AR = ASYNC_RESET; +O18.SP = SYNC_PRESET; + +O19 = !I13 # + !I11 # + !I9 # + !I7 # + !I5 # + !I3 # + !I1; +O19.AR = ASYNC_RESET; +O19.SP = SYNC_PRESET; + +O20 = I6 # + I13 & O19 # + I1 & !I7 # + O18 # + I9 & !I13 # + I14 & !O17 # + !O16; +O20.AR = ASYNC_RESET; +O20.SP = SYNC_PRESET; + +!O21 = !I1 & I2 # + !I3 # + !I4 & I5 & !I6 & !I7 & I8 & !I9 # + I10 & I11 # + !I13 # + !I14 # + !I23; +O21.oe = !I23; +O21.AR = ASYNC_RESET; +O21.SP = SYNC_PRESET; + +O22 = !I8 & I23 # + !O19 & I23 # + !O18 # + O17 # + O16 # + !I2 & I8 & I14 # + !I2 & !I4 & !I6 & !I8 & !I10 & !I14; +O22.AR = ASYNC_RESET; +O22.SP = SYNC_PRESET; diff --git a/regtests/jedutil/eqns/WinCUPL/gal22v10/gal22v10_registered_mode.pld b/regtests/jedutil/eqns/WinCUPL/gal22v10/gal22v10_registered_mode.pld new file mode 100644 index 00000000000..316aaeecc32 --- /dev/null +++ b/regtests/jedutil/eqns/WinCUPL/gal22v10/gal22v10_registered_mode.pld @@ -0,0 +1,83 @@ +Name GAL22V10 Registered Mode Test ; +PartNo 00 ; +Date 5/3/2020 ; +Revision 01 ; +Designer MAME ; +Company MAME ; +Assembly None ; +Location ; +Device G22V10 ; + +/* Registered Mode Test */ + +/* Input Pins */ +PIN 2 = [I2] ; +PIN 3 = [I3] ; +PIN 4 = [I4] ; +PIN 5 = [I5] ; +PIN 6 = [I6] ; +PIN 7 = [I7] ; +PIN 8 = [I8] ; +PIN 9 = [I9] ; +PIN 10 = [I10] ; +PIN 11 = [I11] ; +PIN 14 = [I14] ; +PIN 15 = [I15] ; +PIN 16 = [I16] ; +PIN 17 = [I17] ; +PIN 21 = [I21] ; +PIN 23 = [I23] ; + +/* Output Pins */ +PINNODE 18 = [RF18] ; +PINNODE 19 = [RF19] ; +PINNODE 20 = [RF20] ; +PINNODE 22 = [RF22] ; + +/* Logic Equations */ + +ASYNC_RESET = I2 & !I15 & I16 & !I17 & RF18; +SYNC_PRESET = !RF19 & RF20 & !I21 & !I23; + +!RF18.D = I3 & RF19 # + I5 # + I7 # + I9 # + I11 # + I15 & !RF19 # + I17; +RF18.oe = !I17 & !I21 & I23; +RF18.AR = ASYNC_RESET; +RF18.SP = SYNC_PRESET; + +!RF19.D = !I10 & !I23 # + !I11 & RF18 # + !I9 # + !I7 & I21 # + !I5 # + !I3 & !RF18 # + !I2 # + I4; +RF19.AR = ASYNC_RESET; +RF19.SP = SYNC_PRESET; + +RF20.D = I6 # + I10 & RF19 # + !I7 & I17 # + RF18 # + I9 & !I10 # + I14 & !I17 # + !I16 # + !RF19 & I23; +RF20.AR = ASYNC_RESET; +RF20.SP = SYNC_PRESET; + +RF22.D = !I8 & I23 # + !RF19 & I23 # + !RF18 # + I17 # + I16 # + !I2 & I8 & I14 # + !I2 & !I4 & !I6 & !I8 & !I10 & !I14; +RF22.AR = ASYNC_RESET; +RF22.SP = SYNC_PRESET; |