diff options
Diffstat (limited to 'regtests/jedutil/eqns/PALASM/palce16v8')
12 files changed, 1212 insertions, 0 deletions
diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal10h8-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal10h8-as-palce16v8.pds new file mode 100644 index 00000000000..83a32dc6fd7 --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal10h8-as-palce16v8.pds @@ -0,0 +1,119 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL10H8 Test +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL10H8Test PALCE16V8 + +SIGNATURE #b0010011001100110011001100110011001100110011001100110011001100100 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 O12 COMBINATORIAL ; +PIN 13 O13 COMBINATORIAL ; +PIN 14 O14 COMBINATORIAL ; +PIN 15 O15 COMBINATORIAL ; +PIN 16 O16 COMBINATORIAL ; +PIN 17 O17 COMBINATORIAL ; +PIN 18 O18 COMBINATORIAL ; +PIN 19 O19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +O12 = I2 + + I1 * I3 + + I4 * /I11 + + I5 + + I6 + + /I1 * I7 + + I8 + + I9 * I11 + +O13 = /I2 + + /I4 + + /I3 * /I6 + + /I8 + + /I11 + + /I9 + + /I1 * /I7 + + /I5 + +O14 = I4 + + /I8 * I11 + + /I6 + + /I2 + + I5 * /I11 + + I7 + + /I3 * /I9 + + /I1 + +O15 = I5 + + /I1 + + I1 * I7 + + /I3 + + I1 * /I3 + + I2 * I9 + + /I8 + + I4 + +O16 = I6 + + I3 * I11 + + I6 * I8 + + /I1 + + /I8 + + /I7 * /I8 + + /I2 * /I9 + + /i5 * I7 * I8 + +O17 = I7 + + I2 * I9 + + I3 * I4 + + /I5 + + /I9 + + /I8 + + /I1 * /I11 + + I6 * I9 + +O18 = /I1 + + /I3 + + /I5 + + /I7 + + /I9 + + /I11 + + I1 * I7 * I11 + + I3 * I5 * I9 + +O19 = I3 * I11 + + I1 + + /I1 * /I9 + + /I3 * /I5 * /I7 + + I2 + + I4 + + I6 + + I8 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal10l8-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal10l8-as-palce16v8.pds new file mode 100644 index 00000000000..d39fa0d5436 --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal10l8-as-palce16v8.pds @@ -0,0 +1,119 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL10L8 Test +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL10L8Test PALCE16V8 + +SIGNATURE #b0010011001100110011001100110011001100110011001100110011001100100 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 O12 COMBINATORIAL ; +PIN 13 O13 COMBINATORIAL ; +PIN 14 O14 COMBINATORIAL ; +PIN 15 O15 COMBINATORIAL ; +PIN 16 O16 COMBINATORIAL ; +PIN 17 O17 COMBINATORIAL ; +PIN 18 O18 COMBINATORIAL ; +PIN 19 O19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +/O12 = /I1 * I7 + + I8 + + I9 * I11 + + I2 + + I1 * I3 + + I5 + + I4 * /I11 + + I6 + +/O13 = /I8 + + /I11 + + /I9 + + /I3 * /I6 + + /I1 * /I7 + + /I2 + + /I4 + + /I5 + +/O14 = /I3 * /I9 + + /I6 + + /I2 + + I4 + + /I8 * I11 + + I7 + + I5 * /I11 + + /I1 + +/O15 = I4 + + I1 * /I3 + + I2 * I9 + + I5 + + I1 * I7 + + /I3 + + /I8 + + /I1 + +/O16 = I6 + + /I2 * /I9 + + I3 * I11 + + /I8 + + I6 * I8 + + /I1 + + /i5 * I7 * I8 + + /I7 * /I8 + +/O17 = I3 * I4 + + /I5 + + /I9 + + /I1 * /I11 + + I7 + + I2 * I9 + + I6 * I9 + + /I8 + +/O18 = /I9 + + I3 * I5 * I9 + + /I7 + + /I11 + + /I1 + + /I3 + + /I5 + + I1 * I7 * I11 + +/O19 = /I3 * /I5 * /I7 + + I2 + + I8 + + I3 * I11 + + I1 + + I4 + + I6 + + /I1 * /I9 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal12h6-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal12h6-as-palce16v8.pds new file mode 100644 index 00000000000..fbb6cfeb85e --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal12h6-as-palce16v8.pds @@ -0,0 +1,101 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL12H6 Test +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL12H6Test PALCE16V8 + +SIGNATURE #b0010011001100110011001100110011001100110011001100110011001100100 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 I12 COMBINATORIAL ; +PIN 13 O13 COMBINATORIAL ; +PIN 14 O14 COMBINATORIAL ; +PIN 15 O15 COMBINATORIAL ; +PIN 16 O16 COMBINATORIAL ; +PIN 17 O17 COMBINATORIAL ; +PIN 18 O18 COMBINATORIAL ; +PIN 19 I19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +O13 = /I2 + + /I4 + + /I3 * /I6 + + /I8 + + /I11 + + /I9 + + /I1 * /I7 + + /I5 + +O14 = I4 + + /I8 * I11 + + /I6 + + /I2 + + I5 * /I11 + + I7 + + /I3 * /I9 + + /I1 * /I12 + +O15 = I5 * I19 + + /I1 + + I1 * I7 + + /I3 + + I1 * /I3 + + I2 * I9 + + /I8 + + I4 + +O16 = I6 + + I3 * I11 + + I6 * I8 + + /I1 + + /I8 + + /I7 * /I8 + + /I2 * /I9 + + /i5 * I7 * I8 + +O17 = I7 * I12 + + I2 * I9 + + I3 * I4 + + /I5 + + /I9 + + /I8 + + /I1 * /I11 + + I6 * I9 + +O18 = /I1 + + /I3 + + /I5 + + /I7 + + /I9 * /I19 + + /I11 + + I1 * I7 * I11 + + I3 * I5 * I9 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal12l6-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal12l6-as-palce16v8.pds new file mode 100644 index 00000000000..38f7f44a61e --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal12l6-as-palce16v8.pds @@ -0,0 +1,101 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL12L6 Test +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL12L6Test PALCE16V8 + +SIGNATURE #b0010011001100110011001100110011001100110011001100110011001100100 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 I12 COMBINATORIAL ; +PIN 13 O13 COMBINATORIAL ; +PIN 14 O14 COMBINATORIAL ; +PIN 15 O15 COMBINATORIAL ; +PIN 16 O16 COMBINATORIAL ; +PIN 17 O17 COMBINATORIAL ; +PIN 18 O18 COMBINATORIAL ; +PIN 19 I19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +/O13 = /I8 + + /I11 + + /I9 + + /I3 * /I6 + + /I1 * /I7 + + /I2 + + /I4 * /I12 + + /I5 + +/O14 = /I3 * /I9 * I19 + + /I6 + + /I2 + + I4 + + /I8 * I11 + + I7 + + I5 * /I11 + + /I1 + +/O15 = I4 + + I1 * /I3 + + I2 * I9 + + I5 + + I1 * I7 + + /I3 + + /I8 + + /I1 + +/O16 = I6 + + /I2 * /I9 + + I3 * I11 + + /I8 + + I6 * I8 + + /I1 + + /i5 * I7 * I8 + + /I7 * /I8 * I12 + +/O17 = I3 * I4 + + /I5 + + /I9 + + /I1 * /I11 + + I7 + + I2 * I9 * /I19 + + I6 * I9 + + /I8 + +/O18 = /I9 + + I3 * I5 * I9 + + /I7 + + /I11 + + /I1 + + /I3 + + /I5 + + I1 * I7 * I11 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal14h4-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal14h4-as-palce16v8.pds new file mode 100644 index 00000000000..38d9f968c70 --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal14h4-as-palce16v8.pds @@ -0,0 +1,83 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL14H4 Test +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL14H4Test PALCE16V8 + +SIGNATURE #b0010011001100110011001100110011001100110011001100110011001100100 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 I12 COMBINATORIAL ; +PIN 13 I13 COMBINATORIAL ; +PIN 14 O14 COMBINATORIAL ; +PIN 15 O15 COMBINATORIAL ; +PIN 16 O16 COMBINATORIAL ; +PIN 17 O17 COMBINATORIAL ; +PIN 18 I18 COMBINATORIAL ; +PIN 19 I19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +O14 = I4 + + /I8 * I11 + + /I12 + + /I2 + + I5 * /I11 + + I7 * I12 + + /I3 * /I9 + + /I1 + +O15 = I5 + + /I13 + + I1 * I7 + + /I3 + + /I3 * I13 + + I2 * I9 + + /I8 + + I4 + +O16 = I6 + + I3 * I11 + + I6 * I18 + + /I1 + + /I18 + + /I7 * /I8 + + /I2 * /I9 + + /i5 * I7 * I8 + +O17 = I7 + + I2 * I19 + + I3 * I4 + + /I5 + + /I9 + + /I19 + + /I1 * /I11 + + I6 * I9 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal14l4-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal14l4-as-palce16v8.pds new file mode 100644 index 00000000000..228ab69d47c --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal14l4-as-palce16v8.pds @@ -0,0 +1,83 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL14L4 Test +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL14L4Test PALCE16V8 + +SIGNATURE #b0010011001100110011001100110011001100110011001100110011001100100 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 I12 COMBINATORIAL ; +PIN 13 I13 COMBINATORIAL ; +PIN 14 O14 COMBINATORIAL ; +PIN 15 O15 COMBINATORIAL ; +PIN 16 O16 COMBINATORIAL ; +PIN 17 O17 COMBINATORIAL ; +PIN 18 I18 COMBINATORIAL ; +PIN 19 I19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +/O14 = /I8 * I11 + + I4 + + /I12 + + I5 * /I11 + + I1 + + I7 * I12 + + /I3 * /I9 + + /I2 + +/O15 = I1 * I7 + + /I8 + + I5 + + /I13 + + /I3 + + I2 * I9 + + I4 + + /I3 * I13 + +/O16 = /I18 + + I3 * I11 + + I6 + + I6 * I18 + + /I1 + + /i5 * I7 * I8 + + /I2 * /I9 + + /I7 * /I8 + +/O17 = I2 * I19 + + /I9 + + /I19 + + I3 * I4 + + I6 * I9 + + /I5 + + /I1 * /I11 + + I7 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal16h2-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal16h2-as-palce16v8.pds new file mode 100644 index 00000000000..6bb6a10a367 --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal16h2-as-palce16v8.pds @@ -0,0 +1,65 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL16H2 Test +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL16H2Test PALCE16V8 + +SIGNATURE #b0010011001100110011001100110011001100110011001100110011001100100 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 I12 COMBINATORIAL ; +PIN 13 I13 COMBINATORIAL ; +PIN 14 I14 COMBINATORIAL ; +PIN 15 O15 COMBINATORIAL ; +PIN 16 O16 COMBINATORIAL ; +PIN 17 I17 COMBINATORIAL ; +PIN 18 I18 COMBINATORIAL ; +PIN 19 I19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +O15 = I5 + + /I13 * /I14 + + I1 * I7 + + /I3 * I14 + + /I3 * I13 + + I2 * I9 + + /I8 + + I4 + +O16 = I6 + + I3 * I11 + + I6 * I18 + + /I1 * /I17 + + /I18 + + /I7 * /I8 + + /I2 * /I9 + + /i5 * I7 * I8 * I17 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal16l2-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal16l2-as-palce16v8.pds new file mode 100644 index 00000000000..ce363e1dc6b --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal16l2-as-palce16v8.pds @@ -0,0 +1,65 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL16L2 Test +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL16L2Test PALCE16V8 + +SIGNATURE #b0010011001100110011001100110011001100110011001100110011001100100 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 I12 COMBINATORIAL ; +PIN 13 I13 COMBINATORIAL ; +PIN 14 I14 COMBINATORIAL ; +PIN 15 O15 COMBINATORIAL ; +PIN 16 O16 COMBINATORIAL ; +PIN 17 I17 COMBINATORIAL ; +PIN 18 I18 COMBINATORIAL ; +PIN 19 I19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +/O15 = I5 * /I11 + + /I3 * I14 + + /I3 * I13 + + /I13 * /I14 + + I1 * I7 * I12 + + /I8 * I18 + + I2 * I9 + + I4 * I17 * /I19 + +/O16 = /I2 * /I9 * I19 + + I3 * I11 * /I18 + + /i5 * I7 * I8 * I17 + + I6 * I18 + + /I1 * I14 * /I17 + + I13 * /I18 + + /I7 * /I8 * /I12 + + I6 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal16l8-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal16l8-as-palce16v8.pds new file mode 100644 index 00000000000..74d858e67f4 --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal16l8-as-palce16v8.pds @@ -0,0 +1,119 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL16L8 Test 1 +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL16L8 PALCE16V8 + +SIGNATURE #b1110011001100110011001100110011001100110011001100110011001100110 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 O12 COMBINATORIAL ; +PIN 13 O13 COMBINATORIAL ; +PIN 14 O14 COMBINATORIAL ; +PIN 15 O15 COMBINATORIAL ; +PIN 16 O16 COMBINATORIAL ; +PIN 17 O17 COMBINATORIAL ; +PIN 18 O18 COMBINATORIAL ; +PIN 19 O19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +O12 = I1 * /I2 + + /I1 * I3 + + /I3 * I7 + + I4 * O13 + + I6 * /O13 + + I6 * /I7 + + /I6 * /I8 * /I9 +O12.TRST = /I5 + +/O13 = I3 + + O14 + + /I11 + + I2 + + /I4 * /O14 + + I8 * I9 + + I5 +O13.TRST = VCC + +/O14 = I4 + + /I8 * I11 + + O15 + + /I2 + + I5 * /I11 + + I7 + + /I3 * /I9 +O14.TRST = I1 + +/O15 = I5 + + /O16 + + I1 * I7 + + /I3 + + /I3 * O16 + + I2 * I9 + + /I8 +O15.TRST = VCC + +/O16 = I6 + + I3 * I11 + + I6 * O17 + + /I1 + + /O17 + + /I7 * /I8 + + /I2 * /I9 +O16.TRST = /I11 + +/O17 = I7 + + I2 * O18 + + I3 * I4 + + /I5 + + /I9 + + /O18 + + /I1 * /I11 +O17.TRST = VCC + +O18 = I3 + + I8 + + I9 * I11 + + I1 + + /I4 + + I2 + + I5 * /I7 +O18.TRST = VCC + +O19 = O18 + + O17 + + O16 + + O15 + + O14 + + O13 + + /O13 * /O14 * /O15 * /O16 * /O17 * /O18 +O19.TRST = I3 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal16r4-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal16r4-as-palce16v8.pds new file mode 100644 index 00000000000..6c30783032f --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal16r4-as-palce16v8.pds @@ -0,0 +1,119 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL16R4 Test 1 +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL16R4Test1 PALCE16V8 + +SIGNATURE #b0000000000000000000000000000000000000000000000000000000000000000 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 O12 COMBINATORIAL ; +PIN 13 O13 COMBINATORIAL ; +PIN 14 RF14 REGISTERED ; +PIN 15 RF15 REGISTERED ; +PIN 16 RF16 REGISTERED ; +PIN 17 RF17 REGISTERED ; +PIN 18 O18 COMBINATORIAL ; +PIN 19 O19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +/O12 = I3 * /I4 + + /O19 + + /I2 + + /I5 + + /I6 + + /I7 + + I2 * /I8 * O19 +O12.TRST = I4 * /I9 + +/O13 = /RF14 + + I3 * I7 + + I4 * I5 + + I6 + + /I6 * /I9 * RF14 + + /I2 * /I8 + + I8 * /I9 +O13.TRST = RF14 + +/RF14 := I2 * I9 + + /I2 * RF15 + + I4 * /RF15 + + I3 * /I8 + + I3 * /I4 + + /I5 * /I7 + + /I7 * /I9 + + /I4 * I5 + +/RF15 := I5 * I9 + + I3 * I4 * /I9 + + /RF16 + + /I2 * /I6 + + /I4 * /I9 + + /I3 * RF16 + + /I8 + + /I5 * I8 + +/RF16 := /I8 + + /I7 + + /I6 + + /I5 + + /I4 + + /I3 * /RF17 + + /I2 + + I2 * I3 * I4 * I5 * I6 * I7 * I8 * I9 * RF17 + +/RF17 := I9 + + I8 * O18 + + I7 + + I6 + + I5 + + I4 * /O18 + + I3 + + /I2 + +/O18 = /I3 * O19 + + /I5 + + /I7 + + /I9 + + /I2 + + /I4 * /O19 + + /I6 +O18.TRST = I8 + +/O19 = I2 + + /I5 + + I3 * /O12 + + I9 + + /I2 * /I3 + + /I7 * I9 * O12 + + I5 * I8 +O19.TRST = I4 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal16r6-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal16r6-as-palce16v8.pds new file mode 100644 index 00000000000..0454eba3e30 --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal16r6-as-palce16v8.pds @@ -0,0 +1,119 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL16R6 Test 1 +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL16R6Test1 PALCE16V8 + +SIGNATURE #b0000000000000000000000000000000000000000000000000000000000000000 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 O12 COMBINATORIAL ; +PIN 13 RF13 REGISTERED ; +PIN 14 RF14 REGISTERED ; +PIN 15 RF15 REGISTERED ; +PIN 16 RF16 REGISTERED ; +PIN 17 RF17 REGISTERED ; +PIN 18 RF18 REGISTERED ; +PIN 19 O19 COMBINATORIAL ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +/O12 = RF13 * RF14 * RF15 * RF16 * RF17 * RF18 + + I2 + + I3 + + I4 + + /O19 + + I6 * O19 + + I7 * /I8 * I9 +O12.TRST = /I5 + +/RF13 = /I6 * RF13 + + O12 * O19 + + /I9 * /RF13 + + /I2 * /I5 + + I2 * /O12 + + /I7 * /I9 + + /I2 * /I8 + + /I3 * I8 * I9 + +/RF14 := I2 + + /RF14 + + I3 + + I7 * /I8 * /RF13 + + /I9 * RF14 + + I6 * I9 * RF13 + + I2 * I4 * /I9 + + /I5 * /I8 + +/RF15 := /I3 + + I4 + + I5 * RF14 * RF16 + + /I7 * I9 + + I3 * /RF14 + + /I4 * /I5 + + I6 * /I9 + + /I8 * /RF16 + +/RF16 := I8 * RF17 + + I3 * I9 + + /I4 * /I9 * /RF15 + + I7 * I8 + + I2 * I3 * I9 * /RF17 + + I2 * I5 + + I3 * /I4 * /I5 * RF15 + + /I6 * /I7 * I9 + +/RF17 := I2 * I9 + + /I2 * I3 * /I8 + + /I4 * /I8 + + /I5 * I6 * /I8 * /RF16 + + RF16 * /RF18 + + I3 * /I8 + + /I4 * /I8 * RF16 + + RF18 + +/RF18 := RF18 + + I8 * I9 + + /I5 * I8 + + I3 * I4 * /RF18 + + I2 * /I3 + + /I5 * /I7 * /O19 + + /I2 * I3 * /I7 + + /I2 * O19 + +/O19 = I4 * /O12 + + I5 * /I6 + + /I5 * I6 + + I8 * I9 * /RF18 + + I2 * /I9 * RF18 + + I3 * I9 + + /I4 * /I7 * /I8 +O19.TRST = O12 * /RF18 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- diff --git a/regtests/jedutil/eqns/PALASM/palce16v8/pal16r8-as-palce16v8.pds b/regtests/jedutil/eqns/PALASM/palce16v8/pal16r8-as-palce16v8.pds new file mode 100644 index 00000000000..68dc7770b19 --- /dev/null +++ b/regtests/jedutil/eqns/PALASM/palce16v8/pal16r8-as-palce16v8.pds @@ -0,0 +1,119 @@ +;PALASM Design Description + +;---------------------------------- Declaration Segment ------------ +TITLE PAL16R8 Test 1 +PATTERN A +REVISION 1.0 +AUTHOR MAMEDev +COMPANY MAMEDev +DATE 08/25/13 + +CHIP PAL16R8Test1 PALCE16V8 + +SIGNATURE #b0000000000000000000000000000000000000000000000000000000000000000 + +;---------------------------------- PIN Declarations --------------- +PIN 1 I1 COMBINATORIAL ; +PIN 2 I2 COMBINATORIAL ; +PIN 3 I3 COMBINATORIAL ; +PIN 4 I4 COMBINATORIAL ; +PIN 5 I5 COMBINATORIAL ; +PIN 6 I6 COMBINATORIAL ; +PIN 7 I7 COMBINATORIAL ; +PIN 8 I8 COMBINATORIAL ; +PIN 9 I9 COMBINATORIAL ; +PIN 10 GND ; +PIN 11 I11 COMBINATORIAL ; +PIN 12 RF12 REGISTERED ; +PIN 13 RF13 REGISTERED ; +PIN 14 RF14 REGISTERED ; +PIN 15 RF15 REGISTERED ; +PIN 16 RF16 REGISTERED ; +PIN 17 RF17 REGISTERED ; +PIN 18 RF18 REGISTERED ; +PIN 19 RF19 REGISTERED ; +PIN 20 VCC ; + +;----------------------------------- Boolean Equation Segment ------ +EQUATIONS + +MINIMIZE_OFF + +/RF12 := I5 * RF19 + + /I5 * /RF19 + + /I7 * /I9 * RF12 + + I7 * I9 * /RF12 + + I3 * /I4 * I5 + + /I3 * I4 * /I5 + + /I2 * I6 + + I2 * /I6 + +/RF13 := I8 * I9 * /RF12 + + /I7 * I8 + + I6 * I7 * /I8 * /RF13 + + I5 * /I7 * /I8 + + I5 * /I9 + + I4 * RF12 * RF13 + + /I2 * /I3 * /I9 + + /I4 * /I6 + +/RF14 := /I4 * /I8 * RF13 + + I2 * /I4 + + I3 * /I4 * /RF13 + + /I4 * I5 * I6 + + /I4 * /I5 * I6 * /RF14 + + /I4 * /I5 * /I6 * I7 + + I7 * I8 * RF14 + + /I8 * /I9 + +/RF15 := /I3 * /I4 + + I3 * I5 + + I6 * /RF14 + + I7 * I8 * RF14 + + I9 * /RF15 + + /I5 * /I8 + + I2 * RF15 + + I2 * I9 + +/RF16 := I5 * I9 * /RF16 + + /I5 * /I9 * RF16 + + /I2 * /I3 + + I2 * I3 * I4 + + I5 * I6 * I7 * I8 * I9 * RF15 + + /I5 * /I6 * /I7 * /I8 * /I9 * /RF15 + + I6 * /I7 + + I9 + +/RF17 := I9 + + I8 * /I9 + + /I2 * /RF16 + + /I2 * /I3 * /I9 + + /I3 * I4 * RF17 + + /I3 * I6 * I7 + + /I7 * /I9 + + I5 * RF16 * /RF17 + +/RF18 := /RF17 + + /I2 * /I3 * /I4 * RF17 + + /I2 * /RF18 + + I7 + + I8 + + I9 + + /I2 * /I3 * /I4 * /I5 + + I6 * I7 * /I8 * /I9 + +/RF19 := I2 + + /RF19 + + I3 + + /RF12 * RF19 + + /I5 * /I9 + + /I2 * I8 + + /I4 * I5 * RF12 + + I6 * /I8 * /I9 + +MINIMIZE_ON + +;----------------------------------- Simulation Segment ------------ +SIMULATION + +;------------------------------------------------------------------- |