diff options
| author | 2012-10-03 14:36:54 +0000 | |
|---|---|---|
| committer | 2012-10-03 14:36:54 +0000 | |
| commit | 99ffca1069d9770dfe83afac2ed511ac13aa57e9 (patch) | |
| tree | ec7ea40b3da174fa5c23952d9347f8a06534b5e7 /src | |
| parent | 467aeb1cca692550701af416c1dd8ad1eaa91d5d (diff) | |
some cleanup (nw)
Diffstat (limited to 'src')
| -rw-r--r-- | src/mess/drivers/bebox.c | 34 | ||||
| -rw-r--r-- | src/mess/drivers/dgn_beta.c | 6 | ||||
| -rw-r--r-- | src/mess/includes/bebox.h | 51 | ||||
| -rw-r--r-- | src/mess/includes/dgn_beta.h | 22 | ||||
| -rw-r--r-- | src/mess/includes/fmtowns.h | 22 | ||||
| -rw-r--r-- | src/mess/includes/mbc55x.h | 17 | ||||
| -rw-r--r-- | src/mess/machine/bebox.c | 204 | ||||
| -rw-r--r-- | src/mess/machine/dgn_beta.c | 25 | ||||
| -rw-r--r-- | src/mess/video/dgn_beta.c | 5 |
9 files changed, 164 insertions, 222 deletions
diff --git a/src/mess/drivers/bebox.c b/src/mess/drivers/bebox.c index a6883271b5b..a470017f9ea 100644 --- a/src/mess/drivers/bebox.c +++ b/src/mess/drivers/bebox.c @@ -37,50 +37,50 @@ #include "formats/pc_dsk.h" #include "machine/ram.h" -static READ8_HANDLER(at_dma8237_1_r) { return i8237_r(space.machine().device("dma8237_2"), space, offset / 2); } -static WRITE8_HANDLER(at_dma8237_1_w) { i8237_w(space.machine().device("dma8237_2"), space, offset / 2, data); } +READ8_MEMBER(bebox_state::at_dma8237_1_r) { return i8237_r(machine().device("dma8237_2"), space, offset / 2); } +WRITE8_MEMBER(bebox_state::at_dma8237_1_w) { i8237_w(machine().device("dma8237_2"), space, offset / 2, data); } static ADDRESS_MAP_START( bebox_mem, AS_PROGRAM, 64, bebox_state ) - AM_RANGE(0x7FFFF0F0, 0x7FFFF0F7) AM_READWRITE_LEGACY(bebox_cpu0_imask_r, bebox_cpu0_imask_w ) - AM_RANGE(0x7FFFF1F0, 0x7FFFF1F7) AM_READWRITE_LEGACY(bebox_cpu1_imask_r, bebox_cpu1_imask_w ) - AM_RANGE(0x7FFFF2F0, 0x7FFFF2F7) AM_READ_LEGACY(bebox_interrupt_sources_r ) - AM_RANGE(0x7FFFF3F0, 0x7FFFF3F7) AM_READWRITE_LEGACY(bebox_crossproc_interrupts_r, bebox_crossproc_interrupts_w ) - AM_RANGE(0x7FFFF4F0, 0x7FFFF4F7) AM_WRITE_LEGACY(bebox_processor_resets_w ) + AM_RANGE(0x7FFFF0F0, 0x7FFFF0F7) AM_READWRITE(bebox_cpu0_imask_r, bebox_cpu0_imask_w ) + AM_RANGE(0x7FFFF1F0, 0x7FFFF1F7) AM_READWRITE(bebox_cpu1_imask_r, bebox_cpu1_imask_w ) + AM_RANGE(0x7FFFF2F0, 0x7FFFF2F7) AM_READ(bebox_interrupt_sources_r ) + AM_RANGE(0x7FFFF3F0, 0x7FFFF3F7) AM_READWRITE(bebox_crossproc_interrupts_r, bebox_crossproc_interrupts_w ) + AM_RANGE(0x7FFFF4F0, 0x7FFFF4F7) AM_WRITE(bebox_processor_resets_w ) AM_RANGE(0x80000000, 0x8000001F) AM_DEVREADWRITE8_LEGACY("dma8237_1", i8237_r, i8237_w, U64(0xffffffffffffffff) ) AM_RANGE(0x80000020, 0x8000003F) AM_DEVREADWRITE8_LEGACY("pic8259_master", pic8259_r, pic8259_w, U64(0xffffffffffffffff) ) AM_RANGE(0x80000040, 0x8000005f) AM_DEVREADWRITE8_LEGACY("pit8254", pit8253_r, pit8253_w, U64(0xffffffffffffffff) ) AM_RANGE(0x80000060, 0x8000006F) AM_READWRITE8_LEGACY(kbdc8042_8_r, kbdc8042_8_w, U64(0xffffffffffffffff) ) AM_RANGE(0x80000070, 0x8000007F) AM_DEVREADWRITE8("rtc", mc146818_device, read, write , U64(0xffffffffffffffff) ) - AM_RANGE(0x80000080, 0x8000009F) AM_READWRITE8_LEGACY(bebox_page_r, bebox_page_w, U64(0xffffffffffffffff) ) + AM_RANGE(0x80000080, 0x8000009F) AM_READWRITE8(bebox_page_r, bebox_page_w, U64(0xffffffffffffffff) ) AM_RANGE(0x800000A0, 0x800000BF) AM_DEVREADWRITE8_LEGACY("pic8259_slave", pic8259_r, pic8259_w, U64(0xffffffffffffffff) ) - AM_RANGE(0x800000C0, 0x800000DF) AM_READWRITE8_LEGACY(at_dma8237_1_r, at_dma8237_1_w, U64(0xffffffffffffffff)) - AM_RANGE(0x800001F0, 0x800001F7) AM_READWRITE8_LEGACY(bebox_800001F0_r, bebox_800001F0_w, U64(0xffffffffffffffff) ) + AM_RANGE(0x800000C0, 0x800000DF) AM_READWRITE8(at_dma8237_1_r, at_dma8237_1_w, U64(0xffffffffffffffff)) + AM_RANGE(0x800001F0, 0x800001F7) AM_READWRITE8(bebox_800001F0_r, bebox_800001F0_w, U64(0xffffffffffffffff) ) AM_RANGE(0x800002F8, 0x800002FF) AM_DEVREADWRITE8( "ns16550_1", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) ) AM_RANGE(0x80000380, 0x80000387) AM_DEVREADWRITE8( "ns16550_2", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) ) AM_RANGE(0x80000388, 0x8000038F) AM_DEVREADWRITE8( "ns16550_3", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) ) AM_RANGE(0x800003b0, 0x800003bf) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03b0_r, port_03b0_w, U64(0xffffffffffffffff)) AM_RANGE(0x800003c0, 0x800003cf) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03c0_r, port_03c0_w, U64(0xffffffffffffffff)) AM_RANGE(0x800003d0, 0x800003df) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03d0_r, port_03d0_w, U64(0xffffffffffffffff)) - AM_RANGE(0x800003F0, 0x800003F7) AM_READWRITE_LEGACY(bebox_800003F0_r, bebox_800003F0_w ) + AM_RANGE(0x800003F0, 0x800003F7) AM_READWRITE(bebox_800003F0_r, bebox_800003F0_w ) AM_RANGE(0x800003F8, 0x800003FF) AM_DEVREADWRITE8( "ns16550_0",ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) ) - AM_RANGE(0x80000480, 0x8000048F) AM_READWRITE8_LEGACY(bebox_80000480_r, bebox_80000480_w, U64(0xffffffffffffffff) ) + AM_RANGE(0x80000480, 0x8000048F) AM_READWRITE8(bebox_80000480_r, bebox_80000480_w, U64(0xffffffffffffffff) ) AM_RANGE(0x80000CF8, 0x80000CFF) AM_DEVREADWRITE("pcibus", pci_bus_device, read_64be, write_64be ) //AM_RANGE(0x800042E8, 0x800042EF) AM_DEVWRITE8_LEGACY("cirrus", cirrus_42E8_w, U64(0xffffffffffffffff) ) - AM_RANGE(0xBFFFFFF0, 0xBFFFFFFF) AM_READ_LEGACY(bebox_interrupt_ack_r ) + AM_RANGE(0xBFFFFFF0, 0xBFFFFFFF) AM_READ(bebox_interrupt_ack_r ) AM_RANGE(0xC00A0000, 0XC00BFFFF) AM_DEVREADWRITE8("vga", cirrus_vga_device, mem_r, mem_w, U64(0xffffffffffffffff) ) AM_RANGE(0xC1000000, 0XC11FFFFF) AM_DEVREADWRITE8("vga", cirrus_vga_device, mem_linear_r, mem_linear_w, U64(0xffffffffffffffff) ) AM_RANGE(0xFFF00000, 0xFFF03FFF) AM_ROMBANK("bank2") - AM_RANGE(0xFFF04000, 0xFFFFFFFF) AM_READWRITE8_LEGACY(bebox_flash_r, bebox_flash_w, U64(0xffffffffffffffff) ) + AM_RANGE(0xFFF04000, 0xFFFFFFFF) AM_READWRITE8(bebox_flash_r, bebox_flash_w, U64(0xffffffffffffffff) ) ADDRESS_MAP_END // The following is a gross hack to let the BeBox boot ROM identify the processors correctly. // This needs to be done in a better way if someone comes up with one. -static READ64_HANDLER(bb_slave_64be_r) +READ64_MEMBER(bebox_state::bb_slave_64be_r) { - pci_bus_device *device = space.machine().device<pci_bus_device>("pcibus"); + pci_bus_device *device = machine().device<pci_bus_device>("pcibus"); // 2e94 is the real address, 2e84 is where the PC appears to be under full DRC if ((space.device().safe_pc() == 0xfff02e94) || (space.device().safe_pc() == 0xfff02e84)) @@ -92,7 +92,7 @@ static READ64_HANDLER(bb_slave_64be_r) } static ADDRESS_MAP_START( bebox_slave_mem, AS_PROGRAM, 64, bebox_state ) - AM_RANGE(0x80000cf8, 0x80000cff) AM_READ_LEGACY(bb_slave_64be_r) + AM_RANGE(0x80000cf8, 0x80000cff) AM_READ(bb_slave_64be_r) AM_RANGE(0x80000cf8, 0x80000cff) AM_DEVWRITE("pcibus", pci_bus_device, write_64be ) AM_IMPORT_FROM(bebox_mem) ADDRESS_MAP_END diff --git a/src/mess/drivers/dgn_beta.c b/src/mess/drivers/dgn_beta.c index 4b2a011d700..3b0ae3e971d 100644 --- a/src/mess/drivers/dgn_beta.c +++ b/src/mess/drivers/dgn_beta.c @@ -158,12 +158,12 @@ static ADDRESS_MAP_START( dgnbeta_map, AS_PROGRAM, 8, dgn_beta_state ) AM_RANGE(0xfc80, 0xfc80) AM_DEVWRITE("crtc", mc6845_device, address_w) AM_RANGE(0xfc81, 0xfc81) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w) AM_RANGE(0xfc82, 0xfC9F) AM_NOP - AM_RANGE(0xFCA0, 0xFCA3) AM_READNOP AM_WRITE_LEGACY(dgnbeta_colour_ram_w) /* 4x4bit colour ram for graphics modes */ + AM_RANGE(0xFCA0, 0xFCA3) AM_READNOP AM_WRITE(dgnbeta_colour_ram_w) /* 4x4bit colour ram for graphics modes */ AM_RANGE(0xFCC0, 0xFCC3) AM_DEVREADWRITE(PIA_2_TAG, pia6821_device, read, write) AM_RANGE(0xfcC4, 0xfcdf) AM_NOP - AM_RANGE(0xfce0, 0xfce3) AM_READWRITE_LEGACY(dgnbeta_wd2797_r ,dgnbeta_wd2797_w) /* Onboard disk interface */ + AM_RANGE(0xfce0, 0xfce3) AM_READWRITE(dgnbeta_wd2797_r ,dgnbeta_wd2797_w) /* Onboard disk interface */ AM_RANGE(0xfce4, 0xfdff) AM_NOP - AM_RANGE(0xFE00, 0xFE0F) AM_READWRITE_LEGACY(dgn_beta_page_r ,dgn_beta_page_w) + AM_RANGE(0xFE00, 0xFE0F) AM_READWRITE(dgn_beta_page_r ,dgn_beta_page_w) AM_RANGE(0xfe10, 0xfEff) AM_NOP AM_RANGE(0xFF00, 0xFFFF) AM_RAMBANK("bank17") diff --git a/src/mess/includes/bebox.h b/src/mess/includes/bebox.h index 152dc1cdbc1..133db9cd60d 100644 --- a/src/mess/includes/bebox.h +++ b/src/mess/includes/bebox.h @@ -54,6 +54,33 @@ public: DECLARE_WRITE_LINE_MEMBER(pc_dack2_w); DECLARE_WRITE_LINE_MEMBER(pc_dack3_w); DECLARE_WRITE_LINE_MEMBER(bebox_timer0_w); + DECLARE_READ64_MEMBER(bebox_cpu0_imask_r); + DECLARE_READ64_MEMBER(bebox_cpu1_imask_r); + DECLARE_READ64_MEMBER(bebox_interrupt_sources_r); + DECLARE_READ64_MEMBER(bebox_crossproc_interrupts_r); + DECLARE_READ8_MEMBER(bebox_800001F0_r); + DECLARE_READ64_MEMBER(bebox_800003F0_r); + DECLARE_READ64_MEMBER(bebox_interrupt_ack_r); + DECLARE_READ8_MEMBER(bebox_page_r); + DECLARE_READ8_MEMBER(bebox_80000480_r); + DECLARE_READ8_MEMBER(bebox_flash_r); + + DECLARE_WRITE64_MEMBER(bebox_cpu0_imask_w); + DECLARE_WRITE64_MEMBER(bebox_cpu1_imask_w); + DECLARE_WRITE64_MEMBER(bebox_crossproc_interrupts_w); + DECLARE_WRITE64_MEMBER(bebox_processor_resets_w); + DECLARE_WRITE8_MEMBER(bebox_800001F0_w); + DECLARE_WRITE64_MEMBER(bebox_800003F0_w); + DECLARE_WRITE8_MEMBER(bebox_page_w); + DECLARE_WRITE8_MEMBER(bebox_80000480_w); + DECLARE_WRITE8_MEMBER(bebox_flash_w); + DECLARE_READ8_MEMBER(at_dma8237_1_r); + DECLARE_WRITE8_MEMBER(at_dma8237_1_w); + DECLARE_READ8_MEMBER(bebox_dma_read_byte); + DECLARE_WRITE8_MEMBER(bebox_dma_write_byte); + DECLARE_READ64_MEMBER(scsi53c810_r); + DECLARE_WRITE64_MEMBER(scsi53c810_w); + DECLARE_READ64_MEMBER(bb_slave_64be_r); }; @@ -69,30 +96,6 @@ extern const ins8250_interface bebox_uart_inteface_1; extern const ins8250_interface bebox_uart_inteface_2; extern const ins8250_interface bebox_uart_inteface_3; - - - -DECLARE_READ64_HANDLER( bebox_cpu0_imask_r ); -DECLARE_READ64_HANDLER( bebox_cpu1_imask_r ); -DECLARE_READ64_HANDLER( bebox_interrupt_sources_r ); -DECLARE_READ64_HANDLER( bebox_crossproc_interrupts_r ); -DECLARE_READ8_HANDLER( bebox_800001F0_r ); -DECLARE_READ64_HANDLER( bebox_800003F0_r ); -DECLARE_READ64_HANDLER( bebox_interrupt_ack_r ); -DECLARE_READ8_HANDLER( bebox_page_r ); -DECLARE_READ8_HANDLER( bebox_80000480_r ); -DECLARE_READ8_HANDLER( bebox_flash_r ); - -DECLARE_WRITE64_HANDLER( bebox_cpu0_imask_w ); -DECLARE_WRITE64_HANDLER( bebox_cpu1_imask_w ); -DECLARE_WRITE64_HANDLER( bebox_crossproc_interrupts_w ); -DECLARE_WRITE64_HANDLER( bebox_processor_resets_w ); -DECLARE_WRITE8_HANDLER( bebox_800001F0_w ); -DECLARE_WRITE64_HANDLER( bebox_800003F0_w ); -DECLARE_WRITE8_HANDLER( bebox_page_w ); -DECLARE_WRITE8_HANDLER( bebox_80000480_w ); -DECLARE_WRITE8_HANDLER( bebox_flash_w ); - void bebox_ide_interrupt(device_t *device, int state); void bebox_set_irq_bit(running_machine &machine, unsigned int interrupt_bit, int val); diff --git a/src/mess/includes/dgn_beta.h b/src/mess/includes/dgn_beta.h index 4f61bf96d65..f2188c879dc 100644 --- a/src/mess/includes/dgn_beta.h +++ b/src/mess/includes/dgn_beta.h @@ -183,6 +183,15 @@ public: DECLARE_WRITE_LINE_MEMBER(dgnbeta_fdc_intrq_w); DECLARE_WRITE_LINE_MEMBER(dgnbeta_fdc_drq_w); DECLARE_WRITE_LINE_MEMBER(dgnbeta_vsync_changed); + /* 74HC670 4x4bit colour ram */ + DECLARE_WRITE8_MEMBER(dgnbeta_colour_ram_w); + // Page IO at FE00 + DECLARE_READ8_MEMBER(dgn_beta_page_r); + DECLARE_WRITE8_MEMBER(dgn_beta_page_w); + + /* WD2797 FDC */ + DECLARE_READ8_HANDLER(dgnbeta_wd2797_r); + DECLARE_WRITE8_HANDLER(dgnbeta_wd2797_w); }; @@ -192,16 +201,6 @@ extern const wd17xx_interface dgnbeta_wd17xx_interface; extern const pia6821_interface dgnbeta_pia_intf[]; - - -// Page IO at FE00 -DECLARE_READ8_HANDLER( dgn_beta_page_r ); -DECLARE_WRITE8_HANDLER( dgn_beta_page_w ); - -/* WD2797 FDC */ -DECLARE_READ8_HANDLER(dgnbeta_wd2797_r); -DECLARE_WRITE8_HANDLER(dgnbeta_wd2797_w); - void dgn_beta_frame_interrupt (running_machine &machine, int data); @@ -210,9 +209,6 @@ void dgn_beta_frame_interrupt (running_machine &machine, int data); /* mc6845 video display generator */ void dgnbeta_vid_set_gctrl(running_machine &machine, int data); -/* 74HC670 4x4bit colour ram */ -DECLARE_WRITE8_HANDLER(dgnbeta_colour_ram_w); - extern const mc6845_interface dgnbeta_crtc6845_interface; #endif /* DGN_BETA_H_ */ diff --git a/src/mess/includes/fmtowns.h b/src/mess/includes/fmtowns.h index 204fc40dc70..3bb44f58009 100644 --- a/src/mess/includes/fmtowns.h +++ b/src/mess/includes/fmtowns.h @@ -21,28 +21,6 @@ #define IRQ_LOG 0 // set to 1 to log IRQ line activity -DECLARE_READ8_HANDLER( towns_gfx_high_r ); -DECLARE_WRITE8_HANDLER( towns_gfx_high_w ); -DECLARE_READ8_HANDLER( towns_gfx_r ); -DECLARE_WRITE8_HANDLER( towns_gfx_w ); -DECLARE_READ8_HANDLER( towns_video_cff80_r ); -DECLARE_WRITE8_HANDLER( towns_video_cff80_w ); -DECLARE_READ8_HANDLER( towns_video_cff80_mem_r ); -DECLARE_WRITE8_HANDLER( towns_video_cff80_mem_w ); -DECLARE_READ8_HANDLER(towns_video_440_r); -DECLARE_WRITE8_HANDLER(towns_video_440_w); -DECLARE_READ8_HANDLER(towns_video_5c8_r); -DECLARE_WRITE8_HANDLER(towns_video_5c8_w); -DECLARE_READ8_HANDLER(towns_video_fd90_r); -DECLARE_WRITE8_HANDLER(towns_video_fd90_w); -DECLARE_READ8_HANDLER(towns_video_ff81_r); -DECLARE_WRITE8_HANDLER(towns_video_ff81_w); -DECLARE_READ32_HANDLER(towns_video_unknown_r); -DECLARE_READ8_HANDLER(towns_spriteram_low_r); -DECLARE_WRITE8_HANDLER(towns_spriteram_low_w); -DECLARE_READ8_HANDLER(towns_spriteram_r); -DECLARE_WRITE8_HANDLER(towns_spriteram_w); - struct towns_cdrom_controller { UINT8 command; diff --git a/src/mess/includes/mbc55x.h b/src/mess/includes/mbc55x.h index 8d8dc3a8ba2..aa0395caf35 100644 --- a/src/mess/includes/mbc55x.h +++ b/src/mess/includes/mbc55x.h @@ -160,13 +160,6 @@ public: TIMER_CALLBACK_MEMBER(keyscan_callback); }; -/* IO chips */ - - -struct msm_rx_t -{ -}; - /*----------- defined in drivers/mbc55x.c -----------*/ extern const unsigned char mbc55x_palette[SCREEN_NO_COLOURS][3]; @@ -181,9 +174,6 @@ extern const i8251_interface mbc55x_i8251a_interface; extern const i8251_interface mbc55x_i8251b_interface; - - - /* Memory controller */ #define RAM_BANK00_TAG "bank0" #define RAM_BANK01_TAG "bank1" @@ -204,10 +194,6 @@ extern const i8251_interface mbc55x_i8251b_interface; #define RAM_BANK_SIZE (64*1024) #define RAM_BANK_COUNT 15 - -DECLARE_READ8_HANDLER(ppi8255_r); -DECLARE_WRITE8_HANDLER(ppi8255_w); - /* Floppy drive interface */ #define FDC_PAUSE 10000 @@ -219,9 +205,6 @@ extern const wd17xx_interface mbc55x_wd17xx_interface; extern const mc6845_interface mb55x_mc6845_intf; -DECLARE_READ16_HANDLER (mbc55x_video_io_r); -DECLARE_WRITE16_HANDLER (mbc55x_video_io_w); - #define RED 0 #define GREEN 1 diff --git a/src/mess/machine/bebox.c b/src/mess/machine/bebox.c index 36e2dbd7219..3b848622a59 100644 --- a/src/mess/machine/bebox.c +++ b/src/mess/machine/bebox.c @@ -194,65 +194,59 @@ static void bebox_mbreg32_w(UINT32 *target, UINT64 data, UINT64 mem_mask) } -READ64_HANDLER( bebox_cpu0_imask_r ) +READ64_MEMBER(bebox_state::bebox_cpu0_imask_r ) { - bebox_state *state = space.machine().driver_data<bebox_state>(); - return ((UINT64) state->m_cpu_imask[0]) << 32; + return ((UINT64) m_cpu_imask[0]) << 32; } -READ64_HANDLER( bebox_cpu1_imask_r ) +READ64_MEMBER(bebox_state::bebox_cpu1_imask_r ) { - bebox_state *state = space.machine().driver_data<bebox_state>(); - return ((UINT64) state->m_cpu_imask[1]) << 32; + return ((UINT64) m_cpu_imask[1]) << 32; } -READ64_HANDLER( bebox_interrupt_sources_r ) +READ64_MEMBER(bebox_state::bebox_interrupt_sources_r ) { - bebox_state *state = space.machine().driver_data<bebox_state>(); - return ((UINT64) state->m_interrupts) << 32; + return ((UINT64) m_interrupts) << 32; } -WRITE64_HANDLER( bebox_cpu0_imask_w ) +WRITE64_MEMBER(bebox_state::bebox_cpu0_imask_w ) { - bebox_state *state = space.machine().driver_data<bebox_state>(); - UINT32 old_imask = state->m_cpu_imask[0]; + UINT32 old_imask = m_cpu_imask[0]; - bebox_mbreg32_w(&state->m_cpu_imask[0], data, mem_mask); + bebox_mbreg32_w(&m_cpu_imask[0], data, mem_mask); - if (old_imask != state->m_cpu_imask[0]) + if (old_imask != m_cpu_imask[0]) { if (LOG_CPUIMASK) { logerror("BeBox CPU #0 pc=0x%08X imask=0x%08x\n", - (unsigned) space.device().safe_pc( ), state->m_cpu_imask[0]); + (unsigned) space.device().safe_pc( ), m_cpu_imask[0]); } bebox_update_interrupts(space.machine()); } } -WRITE64_HANDLER( bebox_cpu1_imask_w ) -{ - bebox_state *state = space.machine().driver_data<bebox_state>(); - UINT32 old_imask = state->m_cpu_imask[1]; +WRITE64_MEMBER(bebox_state::bebox_cpu1_imask_w ) +{ + UINT32 old_imask = m_cpu_imask[1]; - bebox_mbreg32_w(&state->m_cpu_imask[1], data, mem_mask); + bebox_mbreg32_w(&m_cpu_imask[1], data, mem_mask); - if (old_imask != state->m_cpu_imask[1]) + if (old_imask != m_cpu_imask[1]) { if (LOG_CPUIMASK) { logerror("BeBox CPU #1 pc=0x%08X imask=0x%08x\n", - (unsigned) space.device() .safe_pc( ), state->m_cpu_imask[1]); + (unsigned) space.device() .safe_pc( ), m_cpu_imask[1]); } bebox_update_interrupts(space.machine()); } } -READ64_HANDLER( bebox_crossproc_interrupts_r ) +READ64_MEMBER(bebox_state::bebox_crossproc_interrupts_r ) { - bebox_state *state = space.machine().driver_data<bebox_state>(); UINT32 result; - result = state->m_crossproc_interrupts; + result = m_crossproc_interrupts; /* return a different result depending on which CPU is accessing this handler */ if (&space != &space.machine().device("ppc1")->memory().space(AS_PROGRAM)) @@ -263,9 +257,8 @@ READ64_HANDLER( bebox_crossproc_interrupts_r ) return ((UINT64) result) << 32; } -WRITE64_HANDLER( bebox_crossproc_interrupts_w ) +WRITE64_MEMBER(bebox_state::bebox_crossproc_interrupts_w ) { - bebox_state *state = space.machine().driver_data<bebox_state>(); static const struct { UINT32 mask; @@ -280,16 +273,16 @@ WRITE64_HANDLER( bebox_crossproc_interrupts_w ) { 0x04000000, 1, 0, 0/*PPC_INPUT_LINE_TLBISYNC*/ } }; int i, line; - UINT32 old_crossproc_interrupts = state->m_crossproc_interrupts; + UINT32 old_crossproc_interrupts = m_crossproc_interrupts; static const char *const cputags[] = { "ppc1", "ppc2" }; - bebox_mbreg32_w(&state->m_crossproc_interrupts, data, mem_mask); + bebox_mbreg32_w(&m_crossproc_interrupts, data, mem_mask); for (i = 0; i < ARRAY_LENGTH(crossproc_map); i++) { - if ((old_crossproc_interrupts ^ state->m_crossproc_interrupts) & crossproc_map[i].mask) + if ((old_crossproc_interrupts ^ m_crossproc_interrupts) & crossproc_map[i].mask) { - if (state->m_crossproc_interrupts & crossproc_map[i].mask) + if (m_crossproc_interrupts & crossproc_map[i].mask) line = crossproc_map[i].active_high ? ASSERT_LINE : CLEAR_LINE; else line = crossproc_map[i].active_high ? CLEAR_LINE : ASSERT_LINE; @@ -308,7 +301,7 @@ WRITE64_HANDLER( bebox_crossproc_interrupts_w ) } } -WRITE64_HANDLER( bebox_processor_resets_w ) +WRITE64_MEMBER(bebox_state::bebox_processor_resets_w ) { UINT8 b = (UINT8) (data >> 56); @@ -505,11 +498,10 @@ static const struct pc_fdc_interface bebox_fdc_interface = * *************************************/ -READ64_HANDLER( bebox_interrupt_ack_r ) +READ64_MEMBER(bebox_state::bebox_interrupt_ack_r ) { - bebox_state *state = space.machine().driver_data<bebox_state>(); int result; - result = pic8259_acknowledge( state->m_devices.pic8259_master ); + result = pic8259_acknowledge( m_devices.pic8259_master ); bebox_set_irq_bit(space.machine(), 5, 0); /* HACK */ return ((UINT64) result) << 56; } @@ -566,10 +558,10 @@ static device_t *ide_device(running_machine &machine) return machine.device("ide"); } -READ8_HANDLER( bebox_800001F0_r ) { return ide_controller_r(ide_device(space.machine()), offset + 0x1F0, 1); } -WRITE8_HANDLER( bebox_800001F0_w ) { ide_controller_w(ide_device(space.machine()), offset + 0x1F0, 1, data); } +READ8_MEMBER(bebox_state::bebox_800001F0_r ) { return ide_controller_r(ide_device(space.machine()), offset + 0x1F0, 1); } +WRITE8_MEMBER(bebox_state::bebox_800001F0_w ) { ide_controller_w(ide_device(space.machine()), offset + 0x1F0, 1, data); } -READ64_HANDLER( bebox_800003F0_r ) +READ64_MEMBER(bebox_state::bebox_800003F0_r ) { UINT64 result = read64be_with_read8_handler(pc_fdc_r, space, offset, mem_mask | 0xFFFF); @@ -588,7 +580,7 @@ READ64_HANDLER( bebox_800003F0_r ) } -WRITE64_HANDLER( bebox_800003F0_w ) +WRITE64_MEMBER(bebox_state::bebox_800003F0_w ) { write64be_with_write8_handler(pc_fdc_w, space, offset, data, mem_mask | 0xFFFF); @@ -616,7 +608,7 @@ void bebox_ide_interrupt(device_t *device, int state) * *************************************/ /* -static READ64_HANDLER( bebox_video_r ) +static READ64_MEMBER(bebox_state::bebox_video_r ) { UINT64 result = 0; mem_mask = FLIPENDIAN_INT64(mem_mask); @@ -640,7 +632,7 @@ static READ64_HANDLER( bebox_video_r ) } -static WRITE64_HANDLER( bebox_video_w ) +static WRITE64_MEMBER(bebox_state::bebox_video_w ) { data = FLIPENDIAN_INT64(data); mem_mask = FLIPENDIAN_INT64(mem_mask); @@ -669,83 +661,80 @@ static WRITE64_HANDLER( bebox_video_w ) *************************************/ -READ8_HANDLER(bebox_page_r) -{ - bebox_state *state = space.machine().driver_data<bebox_state>(); - UINT8 data = state->m_at_pages[offset % 0x10]; +READ8_MEMBER(bebox_state::bebox_page_r) +{ + UINT8 data = m_at_pages[offset % 0x10]; switch(offset % 8) { case 1: - data = state->m_dma_offset[(offset / 8) & 1][2]; + data = m_dma_offset[(offset / 8) & 1][2]; break; case 2: - data = state->m_dma_offset[(offset / 8) & 1][3]; + data = m_dma_offset[(offset / 8) & 1][3]; break; case 3: - data = state->m_dma_offset[(offset / 8) & 1][1]; + data = m_dma_offset[(offset / 8) & 1][1]; break; case 7: - data = state->m_dma_offset[(offset / 8) & 1][0]; + data = m_dma_offset[(offset / 8) & 1][0]; break; } return data; } -WRITE8_HANDLER(bebox_page_w) -{ - bebox_state *state = space.machine().driver_data<bebox_state>(); - state->m_at_pages[offset % 0x10] = data; +WRITE8_MEMBER(bebox_state::bebox_page_w) +{ + m_at_pages[offset % 0x10] = data; switch(offset % 8) { case 1: - state->m_dma_offset[(offset / 8) & 1][2] &= 0xFF00; - state->m_dma_offset[(offset / 8) & 1][2] |= ((UINT16 ) data) << 0; + m_dma_offset[(offset / 8) & 1][2] &= 0xFF00; + m_dma_offset[(offset / 8) & 1][2] |= ((UINT16 ) data) << 0; break; case 2: - state->m_dma_offset[(offset / 8) & 1][3] &= 0xFF00; - state->m_dma_offset[(offset / 8) & 1][3] |= ((UINT16 ) data) << 0; + m_dma_offset[(offset / 8) & 1][3] &= 0xFF00; + m_dma_offset[(offset / 8) & 1][3] |= ((UINT16 ) data) << 0; break; case 3: - state->m_dma_offset[(offset / 8) & 1][1] &= 0xFF00; - state->m_dma_offset[(offset / 8) & 1][1] |= ((UINT16 ) data) << 0; + m_dma_offset[(offset / 8) & 1][1] &= 0xFF00; + m_dma_offset[(offset / 8) & 1][1] |= ((UINT16 ) data) << 0; break; case 7: - state->m_dma_offset[(offset / 8) & 1][0] &= 0xFF00; - state->m_dma_offset[(offset / 8) & 1][0] |= ((UINT16 ) data) << 0; + m_dma_offset[(offset / 8) & 1][0] &= 0xFF00; + m_dma_offset[(offset / 8) & 1][0] |= ((UINT16 ) data) << 0; break; } } -WRITE8_HANDLER(bebox_80000480_w) -{ - bebox_state *state = space.machine().driver_data<bebox_state>(); +WRITE8_MEMBER(bebox_state::bebox_80000480_w) +{ switch(offset % 8) { case 1: - state->m_dma_offset[(offset / 8) & 1][2] &= 0x00FF; - state->m_dma_offset[(offset / 8) & 1][2] |= ((UINT16 ) data) << 8; + m_dma_offset[(offset / 8) & 1][2] &= 0x00FF; + m_dma_offset[(offset / 8) & 1][2] |= ((UINT16 ) data) << 8; break; case 2: - state->m_dma_offset[(offset / 8) & 1][3] &= 0x00FF; - state->m_dma_offset[(offset / 8) & 1][3] |= ((UINT16 ) data) << 8; + m_dma_offset[(offset / 8) & 1][3] &= 0x00FF; + m_dma_offset[(offset / 8) & 1][3] |= ((UINT16 ) data) << 8; break; case 3: - state->m_dma_offset[(offset / 8) & 1][1] &= 0x00FF; - state->m_dma_offset[(offset / 8) & 1][1] |= ((UINT16 ) data) << 8; + m_dma_offset[(offset / 8) & 1][1] &= 0x00FF; + m_dma_offset[(offset / 8) & 1][1] |= ((UINT16 ) data) << 8; break; case 7: - state->m_dma_offset[(offset / 8) & 1][0] &= 0x00FF; - state->m_dma_offset[(offset / 8) & 1][0] |= ((UINT16 ) data) << 8; + m_dma_offset[(offset / 8) & 1][0] &= 0x00FF; + m_dma_offset[(offset / 8) & 1][0] |= ((UINT16 ) data) << 8; break; } } -READ8_HANDLER(bebox_80000480_r) +READ8_MEMBER(bebox_state::bebox_80000480_r) { fatalerror("NYI\n"); } @@ -760,21 +749,21 @@ WRITE_LINE_MEMBER(bebox_state::bebox_dma_hrq_changed) } -static READ8_HANDLER( bebox_dma_read_byte ) +READ8_MEMBER(bebox_state::bebox_dma_read_byte ) { - bebox_state *state = space.machine().driver_data<bebox_state>(); - offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16) + address_space& prog_space = machine().device<cpu_device>("ppc1")->space(AS_PROGRAM); // get the right address space + offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0x7FFF0000; - return space.read_byte(page_offset + offset); + return prog_space.read_byte(page_offset + offset); } -static WRITE8_HANDLER( bebox_dma_write_byte ) +WRITE8_MEMBER(bebox_state::bebox_dma_write_byte ) { - bebox_state *state = space.machine().driver_data<bebox_state>(); - offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16) + address_space& prog_space = machine().device<cpu_device>("ppc1")->space(AS_PROGRAM); // get the right address space + offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0x7FFF0000; - space.write_byte(page_offset + offset, data); + prog_space.write_byte(page_offset + offset, data); } @@ -808,8 +797,8 @@ I8237_INTERFACE( bebox_dma8237_1_config ) { DEVCB_DRIVER_LINE_MEMBER(bebox_state,bebox_dma_hrq_changed), DEVCB_DRIVER_LINE_MEMBER(bebox_state,bebox_dma8237_out_eop), - DEVCB_MEMORY_HANDLER("ppc1", PROGRAM, bebox_dma_read_byte), - DEVCB_MEMORY_HANDLER("ppc1", PROGRAM, bebox_dma_write_byte), + DEVCB_DRIVER_MEMBER(bebox_state, bebox_dma_read_byte), + DEVCB_DRIVER_MEMBER(bebox_state, bebox_dma_write_byte), { DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(bebox_state,bebox_dma8237_fdc_dack_r), DEVCB_NULL }, { DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(bebox_state,bebox_dma8237_fdc_dack_w), DEVCB_NULL }, { DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack0_w), DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack1_w), DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack2_w), DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack3_w) } @@ -869,7 +858,7 @@ const struct pit8253_config bebox_pit8254_config = * *************************************/ -READ8_HANDLER( bebox_flash_r ) +READ8_MEMBER(bebox_state::bebox_flash_r ) { fujitsu_29f016a_device *flash = space.machine().device<fujitsu_29f016a_device>("flash"); offset = (offset & ~7) | (7 - (offset & 7)); @@ -877,7 +866,7 @@ READ8_HANDLER( bebox_flash_r ) } -WRITE8_HANDLER( bebox_flash_w ) +WRITE8_MEMBER(bebox_state::bebox_flash_w ) { fujitsu_29f016a_device *flash = space.machine().device<fujitsu_29f016a_device>("flash"); offset = (offset & ~7) | (7 - (offset & 7)); @@ -920,67 +909,65 @@ static const struct kbdc8042_interface bebox_8042_interface = *************************************/ -static READ64_HANDLER( scsi53c810_r ) -{ - bebox_state *state = space.machine().driver_data<bebox_state>(); +READ64_MEMBER(bebox_state::scsi53c810_r ) +{ int reg = offset*8; UINT64 r = 0; if (!(mem_mask & U64(0xff00000000000000))) { - r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+0) << 56; + r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+0) << 56; } if (!(mem_mask & U64(0x00ff000000000000))) { - r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+1) << 48; + r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+1) << 48; } if (!(mem_mask & U64(0x0000ff0000000000))) { - r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+2) << 40; + r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+2) << 40; } if (!(mem_mask & U64(0x000000ff00000000))) { - r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+3) << 32; + r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+3) << 32; } if (!(mem_mask & U64(0x00000000ff000000))) { - r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+4) << 24; + r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+4) << 24; } if (!(mem_mask & U64(0x0000000000ff0000))) { - r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+5) << 16; + r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+5) << 16; } if (!(mem_mask & U64(0x000000000000ff00))) { - r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+6) << 8; + r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+6) << 8; } if (!(mem_mask & U64(0x00000000000000ff))) { - r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+7) << 0; + r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+7) << 0; } return r; } -static WRITE64_HANDLER( scsi53c810_w ) -{ - bebox_state *state = space.machine().driver_data<bebox_state>(); +WRITE64_MEMBER(bebox_state::scsi53c810_w ) +{ int reg = offset*8; if (!(mem_mask & U64(0xff00000000000000))) { - state->m_lsi53c810->lsi53c810_reg_w(reg+0, data >> 56); + m_lsi53c810->lsi53c810_reg_w(reg+0, data >> 56); } if (!(mem_mask & U64(0x00ff000000000000))) { - state->m_lsi53c810->lsi53c810_reg_w(reg+1, data >> 48); + m_lsi53c810->lsi53c810_reg_w(reg+1, data >> 48); } if (!(mem_mask & U64(0x0000ff0000000000))) { - state->m_lsi53c810->lsi53c810_reg_w(reg+2, data >> 40); + m_lsi53c810->lsi53c810_reg_w(reg+2, data >> 40); } if (!(mem_mask & U64(0x000000ff00000000))) { - state->m_lsi53c810->lsi53c810_reg_w(reg+3, data >> 32); + m_lsi53c810->lsi53c810_reg_w(reg+3, data >> 32); } if (!(mem_mask & U64(0x00000000ff000000))) { - state->m_lsi53c810->lsi53c810_reg_w(reg+4, data >> 24); + m_lsi53c810->lsi53c810_reg_w(reg+4, data >> 24); } if (!(mem_mask & U64(0x0000000000ff0000))) { - state->m_lsi53c810->lsi53c810_reg_w(reg+5, data >> 16); + m_lsi53c810->lsi53c810_reg_w(reg+5, data >> 16); } if (!(mem_mask & U64(0x000000000000ff00))) { - state->m_lsi53c810->lsi53c810_reg_w(reg+6, data >> 8); + m_lsi53c810->lsi53c810_reg_w(reg+6, data >> 8); } if (!(mem_mask & U64(0x00000000000000ff))) { - state->m_lsi53c810->lsi53c810_reg_w(reg+7, data >> 0); + m_lsi53c810->lsi53c810_reg_w(reg+7, data >> 0); } } @@ -1040,8 +1027,7 @@ void scsi53c810_pci_write(device_t *busdevice, device_t *device, int function, i address_space &space = device->machine().device("ppc1")->memory().space(AS_PROGRAM); addr = (state->m_scsi53c810_data[5] | 0xC0000000) & ~0xFF; - space.install_legacy_read_handler(addr, addr + 0xFF, FUNC(scsi53c810_r)); - space.install_legacy_write_handler(addr, addr + 0xFF, FUNC(scsi53c810_w)); + space.install_readwrite_handler(addr, addr + 0xFF, read64_delegate(FUNC(bebox_state::scsi53c810_r),state), write64_delegate(FUNC(bebox_state::scsi53c810_w),state)); } } break; diff --git a/src/mess/machine/dgn_beta.c b/src/mess/machine/dgn_beta.c index b184c3be3b0..84d13acdd2b 100644 --- a/src/mess/machine/dgn_beta.c +++ b/src/mess/machine/dgn_beta.c @@ -326,28 +326,26 @@ static void SetDefaultTask(running_machine &machine) } // Return the value of a page register -READ8_HANDLER( dgn_beta_page_r ) +READ8_MEMBER(dgn_beta_state::dgn_beta_page_r) { - dgn_beta_state *state = space.machine().driver_data<dgn_beta_state>(); - return state->m_PageRegs[state->m_PIATaskReg][offset].value; + return m_PageRegs[m_PIATaskReg][offset].value; } // Write to a page register, writes to the register, and then checks to see // if memory banking is active, if it is, it calls UpdateBanks, to actually // setup the mappings. -WRITE8_HANDLER( dgn_beta_page_w ) +WRITE8_MEMBER(dgn_beta_state::dgn_beta_page_w ) { - dgn_beta_state *state = space.machine().driver_data<dgn_beta_state>(); - state->m_PageRegs[state->m_PIATaskReg][offset].value=data; + m_PageRegs[m_PIATaskReg][offset].value=data; - LOG_PAGE_WRITE(("PageRegWrite : task=$%X offset=$%X value=$%X\n",state->m_PIATaskReg,offset,data)); + LOG_PAGE_WRITE(("PageRegWrite : task=$%X offset=$%X value=$%X\n",m_PIATaskReg,offset,data)); - if (state->m_EnableMapRegs) + if (m_EnableMapRegs) { - UpdateBanks(space.machine(), offset,offset); + UpdateBanks(machine(), offset,offset); if (offset==15) - UpdateBanks(space.machine(), offset+1,offset+1); + UpdateBanks(machine(), offset+1,offset+1); } } @@ -887,7 +885,7 @@ const wd17xx_interface dgnbeta_wd17xx_interface = {FLOPPY_0, FLOPPY_1, FLOPPY_2, FLOPPY_3} }; -READ8_HANDLER(dgnbeta_wd2797_r) +READ8_MEMBER(dgn_beta_state::dgnbeta_wd2797_r) { int result = 0; device_t *fdc = space.machine().device(FDC_TAG); @@ -914,12 +912,11 @@ READ8_HANDLER(dgnbeta_wd2797_r) return result; } -WRITE8_HANDLER(dgnbeta_wd2797_w) +WRITE8_MEMBER(dgn_beta_state::dgnbeta_wd2797_w) { - dgn_beta_state *state = space.machine().driver_data<dgn_beta_state>(); device_t *fdc = space.machine().device(FDC_TAG); - state->m_wd2797_written=1; + m_wd2797_written=1; switch(offset & 0x3) { diff --git a/src/mess/video/dgn_beta.c b/src/mess/video/dgn_beta.c index 6980c9fec66..c14f6d4ddb3 100644 --- a/src/mess/video/dgn_beta.c +++ b/src/mess/video/dgn_beta.c @@ -294,8 +294,7 @@ void dgnbeta_vid_set_gctrl(running_machine &machine, int data) /* Write handler for colour, pallate ram */ -WRITE8_HANDLER(dgnbeta_colour_ram_w) +WRITE8_MEMBER(dgn_beta_state::dgnbeta_colour_ram_w) { - dgn_beta_state *state = space.machine().driver_data<dgn_beta_state>(); - state->m_ColourRAM[offset]=data&0x0f; /* Colour ram 4 bit and write only to CPU */ + m_ColourRAM[offset]=data&0x0f; /* Colour ram 4 bit and write only to CPU */ } |
