diff options
author | 2013-10-14 01:05:11 +0000 | |
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committer | 2013-10-14 01:05:11 +0000 | |
commit | 6992f792c78bda7a9bd7be7ceeddbf5433a6e356 (patch) | |
tree | fa0f0855bbf489034140916220264423f803d00c /src/emu/cpu/nec | |
parent | 7574c7d951ffe3a9d1b8c43a347a4b68540cc04f (diff) |
Fix NEC V25/V35 internal clock divider which was missed during modernization (nw)
Diffstat (limited to 'src/emu/cpu/nec')
-rw-r--r-- | src/emu/cpu/nec/v25.c | 3 | ||||
-rw-r--r-- | src/emu/cpu/nec/v25sfr.c | 17 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/emu/cpu/nec/v25.c b/src/emu/cpu/nec/v25.c index a4a3b583faf..b4cdac81582 100644 --- a/src/emu/cpu/nec/v25.c +++ b/src/emu/cpu/nec/v25.c @@ -8,8 +8,6 @@ Using V20/V30 cycle counts for now. V25/V35 cycle counts vary based on whether internal RAM access is enabled (RAMEN). - Likewise, the programmable clock divider (PCK) currently only - affects the timers, not instruction execution. BTCLR and STOP instructions not implemented. @@ -203,6 +201,7 @@ void v25_common_device::device_reset() m_PCK = 8; m_IDB = 0xFFE00; + set_clock_scale(1.0 / m_PCK); tmp = m_PCK << m_TB; time = attotime::from_hz(unscaled_clock()) * tmp; m_timers[3]->adjust(time, INTTB, time); diff --git a/src/emu/cpu/nec/v25sfr.c b/src/emu/cpu/nec/v25sfr.c index 0594c41f733..9ff2067b470 100644 --- a/src/emu/cpu/nec/v25sfr.c +++ b/src/emu/cpu/nec/v25sfr.c @@ -192,8 +192,8 @@ void v25_common_device::write_sfr(unsigned o, UINT8 d) { if(d & 0x80) { - tmp = m_TM0 * m_PCK * ((d & 0x40) ? 128 : 12 ); - time = attotime::from_hz(unscaled_clock()) * tmp; + tmp = m_TM0 * ((d & 0x40) ? 128 : 12 ); + time = attotime::from_hz(clock()) * tmp; m_timers[0]->adjust(time, INTTU0); } else @@ -201,8 +201,8 @@ void v25_common_device::write_sfr(unsigned o, UINT8 d) if(d & 0x20) { - tmp = m_MD0 * m_PCK * ((d & 0x10) ? 128 : 12 ); - time = attotime::from_hz(unscaled_clock()) * tmp; + tmp = m_MD0 * ((d & 0x10) ? 128 : 12 ); + time = attotime::from_hz(clock()) * tmp; m_timers[1]->adjust(time, INTTU1); } else @@ -212,8 +212,8 @@ void v25_common_device::write_sfr(unsigned o, UINT8 d) { if(d & 0x80) { - tmp = m_MD0 * m_PCK * ((d & 0x40) ? 128 : 6 ); - time = attotime::from_hz(unscaled_clock()) * tmp; + tmp = m_MD0 * ((d & 0x40) ? 128 : 6 ); + time = attotime::from_hz(clock()) * tmp; m_timers[0]->adjust(time, INTTU0, time); m_timers[1]->adjust(attotime::never); m_TM0 = m_MD0; @@ -229,8 +229,8 @@ void v25_common_device::write_sfr(unsigned o, UINT8 d) m_TMC1 = d & 0xC0; if(d & 0x80) { - tmp = m_MD1 * m_PCK * ((d & 0x40) ? 128 : 6 ); - time = attotime::from_hz(unscaled_clock()) * tmp; + tmp = m_MD1 * ((d & 0x40) ? 128 : 6 ); + time = attotime::from_hz(clock()) * tmp; m_timers[2]->adjust(time, INTTU2, time); m_TM1 = m_MD1; } @@ -261,6 +261,7 @@ void v25_common_device::write_sfr(unsigned o, UINT8 d) logerror(" Warning: invalid clock divider\n"); m_PCK = 8; } + set_clock_scale(1.0 / m_PCK); tmp = m_PCK << m_TB; time = attotime::from_hz(unscaled_clock()) * tmp; m_timers[3]->adjust(time, INTTB, time); |