diff options
author | 2015-03-14 17:33:19 +0100 | |
---|---|---|
committer | 2015-03-14 17:33:19 +0100 | |
commit | 4cf5728397ec036d2650a903ed405089816e0bd5 (patch) | |
tree | c9b01b7cd4d95edaa33736c814ccf0921511b853 /src/emu/cpu/hmcs40 | |
parent | 612af8ba64b4aa37a51f5b2f6d895158382ece30 (diff) |
added interrupt/timer
Diffstat (limited to 'src/emu/cpu/hmcs40')
-rw-r--r-- | src/emu/cpu/hmcs40/hmcs40.c | 209 | ||||
-rw-r--r-- | src/emu/cpu/hmcs40/hmcs40.h | 23 | ||||
-rw-r--r-- | src/emu/cpu/hmcs40/hmcs40d.c | 50 | ||||
-rw-r--r-- | src/emu/cpu/hmcs40/hmcs40op.inc | 67 |
4 files changed, 272 insertions, 77 deletions
diff --git a/src/emu/cpu/hmcs40/hmcs40.c b/src/emu/cpu/hmcs40/hmcs40.c index defd8a6e180..bbf4b4327bd 100644 --- a/src/emu/cpu/hmcs40/hmcs40.c +++ b/src/emu/cpu/hmcs40/hmcs40.c @@ -184,6 +184,9 @@ void hmcs40_cpu_device::device_start() m_prgmask = (1 << m_prgwidth) - 1; m_datamask = (1 << m_datawidth) - 1; m_pcmask = (1 << m_pcwidth) - 1; + + m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hmcs40_cpu_device::simple_timer_cb), this)); + reset_prescaler(); m_read_r0.resolve_safe(0); m_read_r1.resolve_safe(0); @@ -210,6 +213,8 @@ void hmcs40_cpu_device::device_start() memset(m_stack, 0, sizeof(m_stack)); m_op = 0; m_prev_op = 0; + m_i = 0; + m_eint_line = 0; m_pc = 0; m_prev_pc = 0; m_page = 0; @@ -221,6 +226,13 @@ void hmcs40_cpu_device::device_start() m_spy = 0; m_s = 1; m_c = 0; + m_tc = 0; + m_cf = 0; + m_ie = 0; + m_iri = m_irt = 0; + memset(m_if, 0, sizeof(m_if)); + m_tf = 0; + memset(m_int, 0, sizeof(m_int)); memset(m_r, 0, sizeof(m_r)); m_d = 0; @@ -228,6 +240,8 @@ void hmcs40_cpu_device::device_start() save_item(NAME(m_stack)); save_item(NAME(m_op)); save_item(NAME(m_prev_op)); + save_item(NAME(m_i)); + save_item(NAME(m_eint_line)); save_item(NAME(m_pc)); save_item(NAME(m_prev_pc)); save_item(NAME(m_page)); @@ -239,6 +253,15 @@ void hmcs40_cpu_device::device_start() save_item(NAME(m_spy)); save_item(NAME(m_s)); save_item(NAME(m_c)); + save_item(NAME(m_tc)); + save_item(NAME(m_cf)); + save_item(NAME(m_ie)); + save_item(NAME(m_iri)); + save_item(NAME(m_irt)); + save_item(NAME(m_if)); + save_item(NAME(m_tf)); + save_item(NAME(m_int)); + save_item(NAME(m_r)); save_item(NAME(m_d)); @@ -275,6 +298,12 @@ void hmcs40_cpu_device::device_reset() for (int i = 0; i < 8; i++) hmcs40_cpu_device::write_r(i, 0); + + // clear interrupts + m_cf = 0; + m_ie = 0; + m_iri = m_irt = 0; + m_if[0] = m_if[1] = m_tf = 1; } @@ -347,7 +376,7 @@ UINT8 hmcs43_cpu_device::read_r(int index) index &= 7; if (index >= 2) - logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc << 1); + logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc); return hmcs40_cpu_device::read_r(index); } @@ -359,7 +388,7 @@ void hmcs43_cpu_device::write_r(int index, UINT8 data) if (index != 0 && index < 4) hmcs40_cpu_device::write_r(index, data); else - logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1); + logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc); } int hmcs43_cpu_device::read_d(int index) @@ -367,7 +396,7 @@ int hmcs43_cpu_device::read_d(int index) index &= 15; if (index >= 4) - logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc << 1); + logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc); return hmcs40_cpu_device::read_d(index); } @@ -381,7 +410,7 @@ UINT8 hmcs44_cpu_device::read_r(int index) index &= 7; if (index >= 6) - logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc << 1); + logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc); return hmcs40_cpu_device::read_r(index); } @@ -393,7 +422,7 @@ void hmcs44_cpu_device::write_r(int index, UINT8 data) if (index < 6) hmcs40_cpu_device::write_r(index, data); else - logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1); + logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc); } // HMCS45: @@ -405,7 +434,7 @@ UINT8 hmcs45_cpu_device::read_r(int index) index &= 7; if (index >= 6) - logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc << 1); + logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc); return hmcs40_cpu_device::read_r(index); } @@ -417,7 +446,83 @@ void hmcs45_cpu_device::write_r(int index, UINT8 data) if (index != 7) hmcs40_cpu_device::write_r(index, data); else - logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1); + logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc); +} + + + +//------------------------------------------------- +// interrupt/timer handling +//------------------------------------------------- + +void hmcs40_cpu_device::do_interrupt() +{ + m_icount--; + push_stack(); + + // line 0/1 for external interrupt, let's use 2 for t/c interrupt + int line = (m_iri) ? m_eint_line : 2; + + // vector $3f, on page 0(timer/counter), or page 1(external) + // external interrupt has priority over t/c interrupt + m_pc = 0x3f | (m_iri ? 0x40 : 0); + m_iri = m_irt = 0; + m_ie = 0; + + standard_irq_callback(line); +} + +void hmcs40_cpu_device::execute_set_input(int line, int state) +{ + if (line != 0 && line != 1) + return; + state = (state) ? 1 : 0; + + // external interrupt request on rising edge + if (state && !m_int[line]) + { + if (!m_if[line]) + { + m_eint_line = line; + m_iri = 1; + m_if[line] = 1; + } + + // clock tc if it is in counter mode + if (m_cf && line == 1) + increment_tc(); + } + + m_int[line] = state; +} + +void hmcs40_cpu_device::reset_prescaler() +{ + // reset 6-bit timer prescaler + attotime base = attotime::from_hz(unscaled_clock() / 4 / 64); + m_timer->adjust(base); +} + +TIMER_CALLBACK_MEMBER( hmcs40_cpu_device::simple_timer_cb ) +{ + // timer prescaler overflow + if (!m_cf) + increment_tc(); + + reset_prescaler(); +} + +void hmcs40_cpu_device::increment_tc() +{ + // increment timer/counter + m_tc = (m_tc + 1) & 0xf; + + // timer interrupt request on overflow + if (m_tc == 0 && !m_tf) + { + m_irt = 1; + m_tf = 1; + } } @@ -451,6 +556,10 @@ void hmcs40_cpu_device::execute_run() if ((m_prev_op & 0x3e0) == 0x340) m_pc = ((m_page << 6) | (m_pc & 0x3f)) & m_pcmask; + // check/handle interrupt + else if (m_ie && (m_iri || m_irt)) + do_interrupt(); + // remember previous state m_prev_op = m_op; m_prev_pc = m_pc; @@ -458,15 +567,67 @@ void hmcs40_cpu_device::execute_run() // fetch next opcode debugger_instruction_hook(this, m_pc); m_op = m_program->read_word(m_pc << 1) & 0x3ff; + m_i = BITSWAP8(m_op,7,6,5,4,0,1,2,3) & 0xf; // reversed bit-order for immediate param increment_pc(); +/* + +op_ayy(); - +op_syy(); - +op_am(); - 34 234 4c +op_sm()???:- 234 +op_daa(); - 46 +op_das(); - 45 +op_nega(); - +op_anem(); - 324 124 +op_bnem(); - 267 024 +op_alem(); - 324 124 +op_blem(); - 267 024 +op_lay(); - 118 + +*/ + // handle opcode switch (m_op) { + case 0x118: + op_lay(); // probably lay + break; + case 0x267: + op_blem(); break; // bnem or blem + case 0x124: + op_alem(); // alem or anem + break; + case 0x324: + op_anem(); break; // " + case 0x024: + //op_nega(); + //op_am(); + op_illegal(); + break; + case 0x234: + // sm? +#if 0 + m_a = ram_r() - m_a; + m_s = ~m_a >> 4 & 1; + m_a &= 0xf; +#else + op_am(); +#endif + break; + case 0x04c: + op_illegal(); + //m_c ^= 1; + //op_lat(); + break; + + + + /* 0x000 */ case 0x000: case 0x001: case 0x002: case 0x003: - op_xsp(); break; +/* ok */ op_xsp(); break; case 0x004: case 0x005: case 0x006: case 0x007: op_sem(); break; case 0x008: case 0x009: case 0x00a: case 0x00b: @@ -490,7 +651,7 @@ void hmcs40_cpu_device::execute_run() case 0x050: op_lya(); break; case 0x054: - op_iy(); break; +/* ok */ op_iy(); break; case 0x060: op_lba(); break; case 0x064: @@ -513,7 +674,7 @@ void hmcs40_cpu_device::execute_run() case 0x0a2: op_seif0(); break; case 0x0a4: - op_seie(); break; +/* ok */ op_seie(); break; case 0x0a5: op_setf(); break; @@ -526,14 +687,14 @@ void hmcs40_cpu_device::execute_run() op_lbr(); break; case 0x0f0: case 0x0f1: case 0x0f2: case 0x0f3: case 0x0f4: case 0x0f5: case 0x0f6: case 0x0f7: case 0x0f8: case 0x0f9: case 0x0fa: case 0x0fb: case 0x0fc: case 0x0fd: case 0x0fe: case 0x0ff: - op_xamr(); break; +/* ok */ op_xamr(); break; /* 0x100 */ - case 0x110: case 0x111: +/* ok */ case 0x110: case 0x111: op_lmaiy(); break; - case 0x114: case 0x115: +/* ok */ case 0x114: case 0x115: op_lmady(); break; case 0x120: op_or(); break; @@ -549,7 +710,7 @@ void hmcs40_cpu_device::execute_run() /* ok */ op_lbi(); break; case 0x170: case 0x171: case 0x172: case 0x173: case 0x174: case 0x175: case 0x176: case 0x177: case 0x178: case 0x179: case 0x17a: case 0x17b: case 0x17c: case 0x17d: case 0x17e: case 0x17f: - op_lti(); break; +/* ok */ op_lti(); break; case 0x1a0: op_tif1(); break; @@ -580,40 +741,40 @@ void hmcs40_cpu_device::execute_run() case 0x204: case 0x205: case 0x206: case 0x207: op_rem(); break; case 0x208: case 0x209: case 0x20a: case 0x20b: - op_xma(); break; +/* ok */ op_xma(); break; case 0x210: case 0x211: case 0x212: case 0x213: case 0x214: case 0x215: case 0x216: case 0x217: case 0x218: case 0x219: case 0x21a: case 0x21b: case 0x21c: case 0x21d: case 0x21e: case 0x21f: op_mnei(); break; case 0x220: case 0x221: case 0x222: case 0x223: /* ok */ op_xmb(); break; case 0x224: - op_rotr(); break; +/* ok */ op_rotr(); break; case 0x225: - op_rotl(); break; +/* ok */ op_rotl(); break; case 0x230: op_smc(); break; case 0x23c: op_lat(); break; case 0x240: - op_laspx(); break; +/* ok */ op_laspx(); break; case 0x24f: op_tc(); break; case 0x250: - op_laspy(); break; +/* ok */ op_laspy(); break; case 0x254: op_dy(); break; case 0x260: - op_lab(); break; +/* ok */ op_lab(); break; case 0x264: op_db(); break; case 0x270: case 0x271: case 0x272: case 0x273: case 0x274: case 0x275: case 0x276: case 0x277: case 0x278: case 0x279: case 0x27a: case 0x27b: case 0x27c: case 0x27d: case 0x27e: case 0x27f: - op_alei(); break; +/* ok */ op_alei(); break; case 0x280: case 0x281: case 0x282: case 0x283: case 0x284: case 0x285: case 0x286: case 0x287: case 0x288: case 0x289: case 0x28a: case 0x28b: case 0x28c: case 0x28d: case 0x28e: case 0x28f: - op_ynei(); break; +/* ok */ op_ynei(); break; case 0x290: /* ok */ op_red(); break; case 0x2a0: @@ -625,7 +786,7 @@ void hmcs40_cpu_device::execute_run() case 0x2a4: op_reie(); break; case 0x2a5: - op_retf(); break; +/* ok */ op_retf(); break; case 0x2c0: case 0x2c1: case 0x2c2: case 0x2c3: case 0x2c4: case 0x2c5: case 0x2c6: case 0x2c7: /* ok */ op_lra(); break; @@ -651,7 +812,7 @@ void hmcs40_cpu_device::execute_run() /* ok */ op_p(); break; case 0x3a4: - op_rtni(); break; +/* ok */ op_rtni(); break; case 0x3a7: /* ok */ op_rtn(); break; diff --git a/src/emu/cpu/hmcs40/hmcs40.h b/src/emu/cpu/hmcs40/hmcs40.h index 6e423a52879..2ee8f2f7a96 100644 --- a/src/emu/cpu/hmcs40/hmcs40.h +++ b/src/emu/cpu/hmcs40/hmcs40.h @@ -78,7 +78,8 @@ protected: // device_execute_interface overrides virtual UINT32 execute_min_cycles() const { return 1; } virtual UINT32 execute_max_cycles() const { return 2; } - virtual UINT32 execute_input_lines() const { return 1; } + virtual UINT32 execute_input_lines() const { return 2+1; } // 3rd one is internal + virtual void execute_set_input(int line, int state); virtual void execute_run(); // device_memory_interface overrides @@ -86,7 +87,7 @@ protected: // device_disasm_interface overrides virtual UINT32 disasm_min_opcode_bytes() const { return 2; } - virtual UINT32 disasm_max_opcode_bytes() const { return 2+1; } + virtual UINT32 disasm_max_opcode_bytes() const { return 2; } virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); void state_string_export(const device_state_entry &entry, astring &string); @@ -107,6 +108,9 @@ protected: UINT16 m_stack[4]; // max 4 UINT16 m_op; // current opcode UINT16 m_prev_op; + UINT8 m_i; // 4-bit immediate opcode param + int m_eint_line; // which input_line caused an interrupt + emu_timer *m_timer; int m_icount; UINT16 m_pc; // Program Counter @@ -118,8 +122,16 @@ protected: UINT8 m_spx; // 1/3/4-bit SPX register UINT8 m_y; // 4-bit Y register UINT8 m_spy; // 4-bit SPY register - UINT8 m_s; // Status F/F + UINT8 m_s; // Status F/F (F/F = flip-flop) UINT8 m_c; // Carry F/F + UINT8 m_tc; // Timer/Counter + UINT8 m_cf; // CF F/F (timer mode or counter mode) + UINT8 m_ie; // I/E(Interrupt Enable) F/F + UINT8 m_iri; // external interrupt pending I/RI F/F + UINT8 m_irt; // timer interrupt pending I/RT F/F + UINT8 m_if[2]; // external interrupt mask IF0,1 F/F + UINT8 m_tf; // timer interrupt mask TF F/F + UINT8 m_int[2]; // INT0/1 pins state UINT8 m_r[8]; // R outputs state UINT16 m_d; // D pins state @@ -142,6 +154,11 @@ protected: virtual int read_d(int index); virtual void write_d(int index, int state); + void reset_prescaler(); + TIMER_CALLBACK_MEMBER( simple_timer_cb ); + void increment_tc(); + void do_interrupt(); + // opcode handlers void op_illegal(); diff --git a/src/emu/cpu/hmcs40/hmcs40d.c b/src/emu/cpu/hmcs40/hmcs40d.c index 53b4ebd292d..08aecd78110 100644 --- a/src/emu/cpu/hmcs40/hmcs40d.c +++ b/src/emu/cpu/hmcs40/hmcs40d.c @@ -3,6 +3,8 @@ /* Hitachi HMCS40 MCU family disassembler + + NOTE: start offset(basepc) is $3F, not 0 */ @@ -41,19 +43,19 @@ static const char *const s_mnemonics[] = "NOP", "?" }; -// number of bits per opcode parameter, -3 means (XY) parameter +// number of bits per opcode parameter, 99 means (XY) parameter, negative means reversed bit-order static const INT8 s_bits[] = { 0, 0, 0, 0, 0, 4, - 0, 0, 4, 4, 0, 0, 0, 0, -3, - -3, -3, -3, -3, -3, -3, - 4, 4, 4, - 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 4, 4, 0, 0, 4, 0, 0, + 0, 0, -4, -4, 0, 0, 0, 0, 99, + 99, 99, 99, 99, 99, 99, + -4, -4, -4, + -4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + -4, -4, 0, 0, -4, 0, 0, 2, 2, 2, 6, 6, 5, 3, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, - 0, 0, 0, 4, 4, 3, 3, 3, 3, 3, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -4, 0, 0, 0, + 0, 0, 0, -4, -4, 3, 3, 3, 3, 3, 0, 0 }; @@ -186,7 +188,7 @@ CPU_DISASSEMBLE(hmcs40) INT8 bits = s_bits[instr]; // special case for (XY) opcode - if (bits == -3) + if (bits == 99) { dst += sprintf(dst, "%s", s_mnemonics[instr]); @@ -196,17 +198,29 @@ CPU_DISASSEMBLE(hmcs40) dst += sprintf(dst, "Y"); } else + { dst += sprintf(dst, "%-6s ", s_mnemonics[instr]); - // opcode parameter - if (bits > 0) - { - UINT8 param = op & ((1 << bits) - 1); - - if (bits > 5) - dst += sprintf(dst, "$%02X", param); - else - dst += sprintf(dst, "%d", param); + // opcode parameter + if (bits != 0) + { + UINT8 param = op; + + // reverse bits + if (bits < 0) + { + param = BITSWAP8(param,0,1,2,3,4,5,6,7); + param >>= (8 + bits); + bits = -bits; + } + + param &= ((1 << bits) - 1); + + if (bits > 5) + dst += sprintf(dst, "$%02X", param); + else + dst += sprintf(dst, "%d", param); + } } int pos = s_next_pc[pc & 0x3f] & DASMFLAG_LENGTHMASK; diff --git a/src/emu/cpu/hmcs40/hmcs40op.inc b/src/emu/cpu/hmcs40/hmcs40op.inc index 916af48f1b9..15c6d309755 100644 --- a/src/emu/cpu/hmcs40/hmcs40op.inc +++ b/src/emu/cpu/hmcs40/hmcs40op.inc @@ -34,7 +34,7 @@ void hmcs40_cpu_device::push_stack() void hmcs40_cpu_device::op_illegal() { - logerror("%s unknown opcode $%03X at $%04X\n", tag(), m_op, m_prev_pc << 1); + logerror("%s unknown opcode $%03X at $%04X\n", tag(), m_op, m_prev_pc); } @@ -110,13 +110,13 @@ void hmcs40_cpu_device::op_lya() void hmcs40_cpu_device::op_lxi() { // LXI i: Load X from Immediate - m_x = m_op & 0xf; + m_x = m_i; } void hmcs40_cpu_device::op_lyi() { // LYI i: Load Y from Immediate - m_y = m_op & 0xf; + m_y = m_i; } void hmcs40_cpu_device::op_iy() @@ -223,20 +223,20 @@ void hmcs40_cpu_device::op_lmady() void hmcs40_cpu_device::op_lmiiy() { // LMIIY i: Load Memory from Immediate, Increment Y - ram_w(m_op & 0xf); + ram_w(m_i); op_iy(); } void hmcs40_cpu_device::op_lai() { // LAI i: Load A from Immediate - m_a = m_op & 0xf; + m_a = m_i; } void hmcs40_cpu_device::op_lbi() { // LBI i: Load B from Immediate - m_b = m_op & 0xf; + m_b = m_i; } @@ -245,7 +245,7 @@ void hmcs40_cpu_device::op_lbi() void hmcs40_cpu_device::op_ai() { // AI i: Add Immediate to A - m_a += (m_op & 0xf); + m_a += (m_i); m_s = m_a >> 4 & 1; m_a &= 0xf; } @@ -368,13 +368,13 @@ void hmcs40_cpu_device::op_or() void hmcs40_cpu_device::op_mnei() { // MNEI i: Memory Not Equal to Immediate - m_s = (ram_r() != (m_op & 0xf)); + m_s = (ram_r() != (m_i)); } void hmcs40_cpu_device::op_ynei() { // YNEI i: Y Not Equal to Immediate - m_s = (m_y != (m_op & 0xf)); + m_s = (m_y != (m_i)); } void hmcs40_cpu_device::op_anem() @@ -392,7 +392,7 @@ void hmcs40_cpu_device::op_bnem() void hmcs40_cpu_device::op_alei() { // ALEI i: A Less or Equal to Immediate - m_s = (m_a <= (m_op & 0xf)); + m_s = (m_a <= (m_i)); } void hmcs40_cpu_device::op_alem() @@ -458,7 +458,7 @@ void hmcs40_cpu_device::op_lpu() if (m_s) m_page = m_op & 0x1f; else - m_op = 0; + m_op = 0; // fake nop } void hmcs40_cpu_device::op_tbr() @@ -480,115 +480,118 @@ void hmcs40_cpu_device::op_rtn() void hmcs40_cpu_device::op_seie() { // SEIE: Set I/E - op_illegal(); + m_ie = 1; } void hmcs40_cpu_device::op_seif0() { // SEIF0: Set IF0 - op_illegal(); + m_if[0] = 1; } void hmcs40_cpu_device::op_seif1() { // SEIF1: Set IF1 - op_illegal(); + m_if[1] = 1; } void hmcs40_cpu_device::op_setf() { // SETF: Set TF - op_illegal(); + m_tf = 1; } void hmcs40_cpu_device::op_secf() { // SECF: Set CF - op_illegal(); + m_cf = 1; } void hmcs40_cpu_device::op_reie() { // REIE: Reset I/E - op_illegal(); + m_ie = 0; } void hmcs40_cpu_device::op_reif0() { // REIF0: Reset IF0 - op_illegal(); + m_if[0] = 0; } void hmcs40_cpu_device::op_reif1() { // REIF1: Reset IF1 - op_illegal(); + m_if[1] = 0; } void hmcs40_cpu_device::op_retf() { // RETF: Reset TF - op_illegal(); + m_tf = 0; } void hmcs40_cpu_device::op_recf() { // RECF: Reset CF - op_illegal(); + m_cf = 0; } void hmcs40_cpu_device::op_ti0() { // TI0: Test INT0 - op_illegal(); + m_s = m_int[0]; } void hmcs40_cpu_device::op_ti1() { // TI1: Test INT1 - op_illegal(); + m_s = m_int[1]; } void hmcs40_cpu_device::op_tif0() { // TIF0: Test IF0 - op_illegal(); + m_s = m_if[0]; } void hmcs40_cpu_device::op_tif1() { // TIF1: Test IF1 - op_illegal(); + m_s = m_if[1]; } void hmcs40_cpu_device::op_ttf() { // TTF: Test TF - op_illegal(); + m_s = m_tf; } void hmcs40_cpu_device::op_lti() { // LTI i: Load Timer/Counter from Immediate - op_illegal(); + m_tc = m_i; + reset_prescaler(); } void hmcs40_cpu_device::op_lta() { // LTA: Load Timer/Counter from A - op_illegal(); + m_tc = m_a; + reset_prescaler(); } void hmcs40_cpu_device::op_lat() { // LAT: Load A from Timer/Counter - op_illegal(); + m_a = m_tc; } void hmcs40_cpu_device::op_rtni() { // RTNI: Return from Interrupt - op_illegal(); + op_seie(); + op_rtn(); } @@ -615,13 +618,13 @@ void hmcs40_cpu_device::op_td() void hmcs40_cpu_device::op_sedd() { // SEDD n: Set Discrete I/O Latch Direct - write_d(m_op & 0xf, 1); + write_d(m_i, 1); } void hmcs40_cpu_device::op_redd() { // REDD n: Reset Discrete I/O Latch Direct - write_d(m_op & 0xf, 0); + write_d(m_i, 0); } void hmcs40_cpu_device::op_lar() |