diff options
author | 2013-01-11 07:32:46 +0000 | |
---|---|---|
committer | 2013-01-11 07:32:46 +0000 | |
commit | 0e19f641d3186cdbf51f8ca857e2b07ab95779c2 (patch) | |
tree | 234109de1123b13f217494af4b3f8efad346d5cc /src/emu/cpu/g65816 | |
parent | 111157ca09a9ff60fe4a9ba49173c315e94314fa (diff) |
Cleanups and version bumpmame0148
Diffstat (limited to 'src/emu/cpu/g65816')
-rw-r--r-- | src/emu/cpu/g65816/g65816.c | 220 | ||||
-rw-r--r-- | src/emu/cpu/g65816/g65816cm.h | 390 | ||||
-rw-r--r-- | src/emu/cpu/g65816/g65816ds.c | 64 | ||||
-rw-r--r-- | src/emu/cpu/g65816/g65816op.h | 1590 |
4 files changed, 1132 insertions, 1132 deletions
diff --git a/src/emu/cpu/g65816/g65816.c b/src/emu/cpu/g65816/g65816.c index 94348229019..0dbc1c6b791 100644 --- a/src/emu/cpu/g65816/g65816.c +++ b/src/emu/cpu/g65816/g65816.c @@ -385,28 +385,28 @@ static CPU_SET_INFO( g65816 ) switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + G65816_LINE_IRQ: g65816_set_irq_line(cpustate, G65816_LINE_IRQ, info->i); break; - case CPUINFO_INT_INPUT_STATE + G65816_LINE_NMI: g65816_set_irq_line(cpustate, G65816_LINE_NMI, info->i); break; - case CPUINFO_INT_INPUT_STATE + G65816_LINE_ABORT: g65816_set_irq_line(cpustate, G65816_LINE_ABORT, info->i); break; - case CPUINFO_INT_INPUT_STATE + G65816_LINE_SO: g65816_set_irq_line(cpustate, G65816_LINE_SO, info->i); break; - case CPUINFO_INT_INPUT_STATE + G65816_LINE_RDY: g65816_set_irq_line(cpustate, G65816_LINE_RDY, info->i); break; - case CPUINFO_INT_INPUT_STATE + G65816_LINE_RESET: g65816_set_irq_line(cpustate, G65816_LINE_RESET, info->i); break; - - case CPUINFO_INT_PC: g65816_set_pc(cpustate, info->i); break; - case CPUINFO_INT_SP: g65816_set_sp(cpustate, info->i); break; - - case CPUINFO_INT_REGISTER + G65816_PC: g65816_set_reg(cpustate, G65816_PC, info->i); break; - case CPUINFO_INT_REGISTER + G65816_S: g65816_set_reg(cpustate, G65816_S, info->i); break; - case CPUINFO_INT_REGISTER + G65816_P: g65816_set_reg(cpustate, G65816_P, info->i); break; - case CPUINFO_INT_REGISTER + G65816_A: g65816_set_reg(cpustate, G65816_A, info->i); break; - case CPUINFO_INT_REGISTER + G65816_X: g65816_set_reg(cpustate, G65816_X, info->i); break; - case CPUINFO_INT_REGISTER + G65816_Y: g65816_set_reg(cpustate, G65816_Y, info->i); break; - case CPUINFO_INT_REGISTER + G65816_PB: g65816_set_reg(cpustate, G65816_PB, info->i); break; - case CPUINFO_INT_REGISTER + G65816_DB: g65816_set_reg(cpustate, G65816_DB, info->i); break; - case CPUINFO_INT_REGISTER + G65816_D: g65816_set_reg(cpustate, G65816_D, info->i); break; - case CPUINFO_INT_REGISTER + G65816_E: g65816_set_reg(cpustate, G65816_E, info->i); break; - case CPUINFO_INT_REGISTER + G65816_NMI_STATE: g65816_set_reg(cpustate, G65816_NMI_STATE, info->i); break; - case CPUINFO_INT_REGISTER + G65816_IRQ_STATE: g65816_set_reg(cpustate, G65816_IRQ_STATE, info->i); break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_IRQ: g65816_set_irq_line(cpustate, G65816_LINE_IRQ, info->i); break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_NMI: g65816_set_irq_line(cpustate, G65816_LINE_NMI, info->i); break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_ABORT: g65816_set_irq_line(cpustate, G65816_LINE_ABORT, info->i); break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_SO: g65816_set_irq_line(cpustate, G65816_LINE_SO, info->i); break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_RDY: g65816_set_irq_line(cpustate, G65816_LINE_RDY, info->i); break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_RESET: g65816_set_irq_line(cpustate, G65816_LINE_RESET, info->i); break; + + case CPUINFO_INT_PC: g65816_set_pc(cpustate, info->i); break; + case CPUINFO_INT_SP: g65816_set_sp(cpustate, info->i); break; + + case CPUINFO_INT_REGISTER + G65816_PC: g65816_set_reg(cpustate, G65816_PC, info->i); break; + case CPUINFO_INT_REGISTER + G65816_S: g65816_set_reg(cpustate, G65816_S, info->i); break; + case CPUINFO_INT_REGISTER + G65816_P: g65816_set_reg(cpustate, G65816_P, info->i); break; + case CPUINFO_INT_REGISTER + G65816_A: g65816_set_reg(cpustate, G65816_A, info->i); break; + case CPUINFO_INT_REGISTER + G65816_X: g65816_set_reg(cpustate, G65816_X, info->i); break; + case CPUINFO_INT_REGISTER + G65816_Y: g65816_set_reg(cpustate, G65816_Y, info->i); break; + case CPUINFO_INT_REGISTER + G65816_PB: g65816_set_reg(cpustate, G65816_PB, info->i); break; + case CPUINFO_INT_REGISTER + G65816_DB: g65816_set_reg(cpustate, G65816_DB, info->i); break; + case CPUINFO_INT_REGISTER + G65816_D: g65816_set_reg(cpustate, G65816_D, info->i); break; + case CPUINFO_INT_REGISTER + G65816_E: g65816_set_reg(cpustate, G65816_E, info->i); break; + case CPUINFO_INT_REGISTER + G65816_NMI_STATE: g65816_set_reg(cpustate, G65816_NMI_STATE, info->i); break; + case CPUINFO_INT_REGISTER + G65816_IRQ_STATE: g65816_set_reg(cpustate, G65816_IRQ_STATE, info->i); break; } } @@ -429,70 +429,70 @@ CPU_GET_INFO( g65816 ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(g65816i_cpu_struct); break; - case CPUINFO_INT_INPUT_LINES: info->i = 1; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 20; /* rough guess */ break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + G65816_LINE_IRQ: info->i = LINE_IRQ; break; - case CPUINFO_INT_INPUT_STATE + G65816_LINE_NMI: info->i = LINE_NMI; break; - case CPUINFO_INT_INPUT_STATE + G65816_LINE_ABORT: info->i = 0; break; - case CPUINFO_INT_INPUT_STATE + G65816_LINE_SO: info->i = 0; break; - case CPUINFO_INT_INPUT_STATE + G65816_LINE_RDY: info->i = 0; break; - case CPUINFO_INT_INPUT_STATE + G65816_LINE_RESET: info->i = 0; break; - - case CPUINFO_INT_PREVIOUSPC: /* not supported */ break; - - case CPUINFO_INT_PC: info->i = g65816_get_pc(cpustate); break; - case CPUINFO_INT_SP: info->i = g65816_get_sp(cpustate); break; - - case CPUINFO_INT_REGISTER + G65816_PC: info->i = g65816_get_pc(cpustate); break; - case CPUINFO_INT_REGISTER + G65816_S: info->i = g65816_get_reg(cpustate, G65816_S); break; - case CPUINFO_INT_REGISTER + G65816_P: info->i = g65816_get_reg(cpustate, G65816_P); break; - case CPUINFO_INT_REGISTER + G65816_A: info->i = g65816_get_reg(cpustate, G65816_A); break; - case CPUINFO_INT_REGISTER + G65816_X: info->i = g65816_get_reg(cpustate, G65816_X); break; - case CPUINFO_INT_REGISTER + G65816_Y: info->i = g65816_get_reg(cpustate, G65816_Y); break; - case CPUINFO_INT_REGISTER + G65816_PB: info->i = g65816_get_reg(cpustate, G65816_PB); break; - case CPUINFO_INT_REGISTER + G65816_DB: info->i = g65816_get_reg(cpustate, G65816_DB); break; - case CPUINFO_INT_REGISTER + G65816_D: info->i = g65816_get_reg(cpustate, G65816_D); break; - case CPUINFO_INT_REGISTER + G65816_E: info->i = g65816_get_reg(cpustate, G65816_E); break; - case CPUINFO_INT_REGISTER + G65816_NMI_STATE: info->i = g65816_get_reg(cpustate, G65816_NMI_STATE); break; - case CPUINFO_INT_REGISTER + G65816_IRQ_STATE: info->i = g65816_get_reg(cpustate, G65816_IRQ_STATE); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(g65816i_cpu_struct); break; + case CPUINFO_INT_INPUT_LINES: info->i = 1; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 20; /* rough guess */ break; + + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; + + case CPUINFO_INT_INPUT_STATE + G65816_LINE_IRQ: info->i = LINE_IRQ; break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_NMI: info->i = LINE_NMI; break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_ABORT: info->i = 0; break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_SO: info->i = 0; break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_RDY: info->i = 0; break; + case CPUINFO_INT_INPUT_STATE + G65816_LINE_RESET: info->i = 0; break; + + case CPUINFO_INT_PREVIOUSPC: /* not supported */ break; + + case CPUINFO_INT_PC: info->i = g65816_get_pc(cpustate); break; + case CPUINFO_INT_SP: info->i = g65816_get_sp(cpustate); break; + + case CPUINFO_INT_REGISTER + G65816_PC: info->i = g65816_get_pc(cpustate); break; + case CPUINFO_INT_REGISTER + G65816_S: info->i = g65816_get_reg(cpustate, G65816_S); break; + case CPUINFO_INT_REGISTER + G65816_P: info->i = g65816_get_reg(cpustate, G65816_P); break; + case CPUINFO_INT_REGISTER + G65816_A: info->i = g65816_get_reg(cpustate, G65816_A); break; + case CPUINFO_INT_REGISTER + G65816_X: info->i = g65816_get_reg(cpustate, G65816_X); break; + case CPUINFO_INT_REGISTER + G65816_Y: info->i = g65816_get_reg(cpustate, G65816_Y); break; + case CPUINFO_INT_REGISTER + G65816_PB: info->i = g65816_get_reg(cpustate, G65816_PB); break; + case CPUINFO_INT_REGISTER + G65816_DB: info->i = g65816_get_reg(cpustate, G65816_DB); break; + case CPUINFO_INT_REGISTER + G65816_D: info->i = g65816_get_reg(cpustate, G65816_D); break; + case CPUINFO_INT_REGISTER + G65816_E: info->i = g65816_get_reg(cpustate, G65816_E); break; + case CPUINFO_INT_REGISTER + G65816_NMI_STATE: info->i = g65816_get_reg(cpustate, G65816_NMI_STATE); break; + case CPUINFO_INT_REGISTER + G65816_IRQ_STATE: info->i = g65816_get_reg(cpustate, G65816_IRQ_STATE); break; /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(g65816); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(g65816); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(g65816); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(g65816); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(g65816); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(g65816); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->ICount; break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(g65816); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(g65816); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(g65816); break; + case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(g65816); break; + case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(g65816); break; + case CPUINFO_FCT_BURN: info->burn = NULL; break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(g65816); break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->ICount; break; - case CPUINFO_FCT_READOP: info->readop = CPU_READOP_NAME(g65816); break; + case CPUINFO_FCT_READOP: info->readop = CPU_READOP_NAME(g65816); break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "G65C816"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "6500"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud, all rights reserved."); break; + case CPUINFO_STR_NAME: strcpy(info->s, "G65C816"); break; + case CPUINFO_STR_FAMILY: strcpy(info->s, "6500"); break; + case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; + case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud, all rights reserved."); break; case CPUINFO_STR_FLAGS: sprintf(info->s, "%c%c%c%c%c%c%c%c", @@ -507,26 +507,26 @@ CPU_GET_INFO( g65816 ) cpustate->flag_c & CFLAG_SET ? 'C':'.'); break; - case CPUINFO_STR_REGISTER + G65816_PC: sprintf(info->s, "PC:%06X", g65816_get_pc(cpustate)); break; - case CPUINFO_STR_REGISTER + G65816_PB: sprintf(info->s, "PB:%02X", cpustate->pb>>16); break; - case CPUINFO_STR_REGISTER + G65816_DB: sprintf(info->s, "DB:%02X", cpustate->db>>16); break; - case CPUINFO_STR_REGISTER + G65816_D: sprintf(info->s, "D:%04X", cpustate->d); break; - case CPUINFO_STR_REGISTER + G65816_S: sprintf(info->s, "S:%04X", cpustate->s); break; - case CPUINFO_STR_REGISTER + G65816_P: sprintf(info->s, "P:%02X", - (cpustate->flag_n&0x80) | - ((cpustate->flag_v>>1)&0x40) | - cpustate->flag_m | - cpustate->flag_x | - cpustate->flag_d | - cpustate->flag_i | - ((!cpustate->flag_z)<<1) | + case CPUINFO_STR_REGISTER + G65816_PC: sprintf(info->s, "PC:%06X", g65816_get_pc(cpustate)); break; + case CPUINFO_STR_REGISTER + G65816_PB: sprintf(info->s, "PB:%02X", cpustate->pb>>16); break; + case CPUINFO_STR_REGISTER + G65816_DB: sprintf(info->s, "DB:%02X", cpustate->db>>16); break; + case CPUINFO_STR_REGISTER + G65816_D: sprintf(info->s, "D:%04X", cpustate->d); break; + case CPUINFO_STR_REGISTER + G65816_S: sprintf(info->s, "S:%04X", cpustate->s); break; + case CPUINFO_STR_REGISTER + G65816_P: sprintf(info->s, "P:%02X", + (cpustate->flag_n&0x80) | + ((cpustate->flag_v>>1)&0x40) | + cpustate->flag_m | + cpustate->flag_x | + cpustate->flag_d | + cpustate->flag_i | + ((!cpustate->flag_z)<<1) | ((cpustate->flag_c>>8)&1)); break; - case CPUINFO_STR_REGISTER + G65816_E: sprintf(info->s, "E:%d", cpustate->flag_e); break; - case CPUINFO_STR_REGISTER + G65816_A: sprintf(info->s, "A:%04X", cpustate->a | cpustate->b); break; - case CPUINFO_STR_REGISTER + G65816_X: sprintf(info->s, "X:%04X", cpustate->x); break; - case CPUINFO_STR_REGISTER + G65816_Y: sprintf(info->s, "Y:%04X", cpustate->y); break; - case CPUINFO_STR_REGISTER + G65816_NMI_STATE: sprintf(info->s, "NMI:%X", cpustate->line_nmi); break; - case CPUINFO_STR_REGISTER + G65816_IRQ_STATE: sprintf(info->s, "IRQ:%X", cpustate->line_irq); break; + case CPUINFO_STR_REGISTER + G65816_E: sprintf(info->s, "E:%d", cpustate->flag_e); break; + case CPUINFO_STR_REGISTER + G65816_A: sprintf(info->s, "A:%04X", cpustate->a | cpustate->b); break; + case CPUINFO_STR_REGISTER + G65816_X: sprintf(info->s, "X:%04X", cpustate->x); break; + case CPUINFO_STR_REGISTER + G65816_Y: sprintf(info->s, "Y:%04X", cpustate->y); break; + case CPUINFO_STR_REGISTER + G65816_NMI_STATE: sprintf(info->s, "NMI:%X", cpustate->line_nmi); break; + case CPUINFO_STR_REGISTER + G65816_IRQ_STATE: sprintf(info->s, "IRQ:%X", cpustate->line_irq); break; } } @@ -680,9 +680,9 @@ CPU_SET_INFO( _5a22 ) switch (state) { - case CPUINFO_INT_REGISTER + _5A22_FASTROM: g65816_set_reg(cpustate, _5A22_FASTROM, info->i); break; + case CPUINFO_INT_REGISTER + _5A22_FASTROM: g65816_set_reg(cpustate, _5A22_FASTROM, info->i); break; - default: CPU_SET_INFO_CALL(g65816); break; + default: CPU_SET_INFO_CALL(g65816); break; } } @@ -693,17 +693,17 @@ CPU_GET_INFO( _5a22 ) switch (state) { /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(_5a22); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(5a22); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(5a22); break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(_5a22); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(5a22); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(5a22); break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "5A22"); break; - case CPUINFO_INT_REGISTER + _5A22_FASTROM: info->i = g65816_get_reg(cpustate, _5A22_FASTROM); break; - case CPUINFO_STR_REGISTER + _5A22_FASTROM: sprintf(info->s, "fastROM:%d", cpustate->fastROM & 1 ? 1 : 0); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(_5a22_map); break; + case CPUINFO_STR_NAME: strcpy(info->s, "5A22"); break; + case CPUINFO_INT_REGISTER + _5A22_FASTROM: info->i = g65816_get_reg(cpustate, _5A22_FASTROM); break; + case CPUINFO_STR_REGISTER + _5A22_FASTROM: sprintf(info->s, "fastROM:%d", cpustate->fastROM & 1 ? 1 : 0); break; + case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map8 = ADDRESS_MAP_NAME(_5a22_map); break; - default: CPU_GET_INFO_CALL(g65816); break; + default: CPU_GET_INFO_CALL(g65816); break; } } diff --git a/src/emu/cpu/g65816/g65816cm.h b/src/emu/cpu/g65816/g65816cm.h index 18d8873d3a8..c404b00e6de 100644 --- a/src/emu/cpu/g65816/g65816cm.h +++ b/src/emu/cpu/g65816/g65816cm.h @@ -11,9 +11,9 @@ #undef G65816_CALL_DEBUGGER #define G65816_CALL_DEBUGGER(x) debugger_instruction_hook(cpustate->device, x) -#define g65816_read_8(addr) cpustate->program->read_byte(addr) -#define g65816_write_8(addr,data) cpustate->program->write_byte(addr,data) -#define g65816_read_8_immediate(A) cpustate->program->read_byte(A) +#define g65816_read_8(addr) cpustate->program->read_byte(addr) +#define g65816_write_8(addr,data) cpustate->program->write_byte(addr,data) +#define g65816_read_8_immediate(A) cpustate->program->read_byte(A) #define g65816_jumping(A) #define g65816_branching(A) @@ -52,14 +52,14 @@ INLINE int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;} #define MAKE_UINT_24(A) ((A)&0xffffff) /* Bits */ -#define BIT_0 0x01 -#define BIT_1 0x02 -#define BIT_2 0x04 -#define BIT_3 0x08 -#define BIT_4 0x10 -#define BIT_5 0x20 -#define BIT_6 0x40 -#define BIT_7 0x80 +#define BIT_0 0x01 +#define BIT_1 0x02 +#define BIT_2 0x04 +#define BIT_3 0x08 +#define BIT_4 0x10 +#define BIT_5 0x20 +#define BIT_6 0x40 +#define BIT_7 0x80 /* ======================================================================== */ @@ -69,35 +69,35 @@ INLINE int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;} /* CPU Structure */ struct g65816i_cpu_struct { - uint a; /* Accumulator */ - uint b; /* holds high byte of accumulator */ - uint x; /* Index Register X */ - uint y; /* Index Register Y */ - uint s; /* Stack Pointer */ - uint pc; /* Program Counter */ - uint ppc; /* Previous Program Counter */ - uint pb; /* Program Bank (shifted left 16) */ - uint db; /* Data Bank (shifted left 16) */ - uint d; /* Direct Register */ - uint flag_e; /* Emulation Mode Flag */ - uint flag_m; /* Memory/Accumulator Select Flag */ - uint flag_x; /* Index Select Flag */ - uint flag_n; /* Negative Flag */ - uint flag_v; /* Overflow Flag */ - uint flag_d; /* Decimal Mode Flag */ - uint flag_i; /* Interrupt Mask Flag */ - uint flag_z; /* Zero Flag (inverted) */ - uint flag_c; /* Carry Flag */ - uint line_irq; /* Status of the IRQ line */ - uint line_nmi; /* Status of the NMI line */ - uint fastROM; /* SNES specific */ - uint ir; /* Instruction Register */ - uint irq_delay; /* delay 1 instruction before checking irq */ + uint a; /* Accumulator */ + uint b; /* holds high byte of accumulator */ + uint x; /* Index Register X */ + uint y; /* Index Register Y */ + uint s; /* Stack Pointer */ + uint pc; /* Program Counter */ + uint ppc; /* Previous Program Counter */ + uint pb; /* Program Bank (shifted left 16) */ + uint db; /* Data Bank (shifted left 16) */ + uint d; /* Direct Register */ + uint flag_e; /* Emulation Mode Flag */ + uint flag_m; /* Memory/Accumulator Select Flag */ + uint flag_x; /* Index Select Flag */ + uint flag_n; /* Negative Flag */ + uint flag_v; /* Overflow Flag */ + uint flag_d; /* Decimal Mode Flag */ + uint flag_i; /* Interrupt Mask Flag */ + uint flag_z; /* Zero Flag (inverted) */ + uint flag_c; /* Carry Flag */ + uint line_irq; /* Status of the IRQ line */ + uint line_nmi; /* Status of the NMI line */ + uint fastROM; /* SNES specific */ + uint ir; /* Instruction Register */ + uint irq_delay; /* delay 1 instruction before checking irq */ device_irq_acknowledge_callback int_ack; /* Interrupt Acknowledge */ legacy_cpu_device *device; address_space *program; - read8_delegate read_vector; /* Read vector override */ - uint stopped; /* Sets how the CPU is stopped */ + read8_delegate read_vector; /* Read vector override */ + uint stopped; /* Sets how the CPU is stopped */ void (*const *opcodes)(g65816i_cpu_struct *cpustate); uint (*get_reg)(g65816i_cpu_struct *cpustate, int regnum); void (*set_reg)(g65816i_cpu_struct *cpustate, int regnum, uint val); @@ -125,51 +125,51 @@ extern void (*const g65816i_set_line[])(g65816i_cpu_struct *cpustate, int line, extern int (*const g65816i_execute[])(g65816i_cpu_struct *cpustate, int cycles); extern int bus_5A22_cycle_burst(g65816i_cpu_struct *cpustate, uint addr); -#define REGISTER_A cpustate->a /* Accumulator */ -#define REGISTER_B cpustate->b /* Accumulator hi byte */ -#define REGISTER_X cpustate->x /* Index X Register */ -#define REGISTER_Y cpustate->y /* Index Y Register */ -#define REGISTER_S cpustate->s /* Stack Pointer */ -#define REGISTER_PC cpustate->pc /* Program Counter */ -#define REGISTER_PPC cpustate->ppc /* Previous Program Counter */ -#define REGISTER_PB cpustate->pb /* Program Bank */ -#define REGISTER_DB cpustate->db /* Data Bank */ -#define REGISTER_D cpustate->d /* Direct Register */ -#define FLAG_E cpustate->flag_e /* Emulation Mode Flag */ -#define FLAG_M cpustate->flag_m /* Memory/Accumulator Select Flag */ -#define FLAG_X cpustate->flag_x /* Index Select Flag */ -#define FLAG_N cpustate->flag_n /* Negative Flag */ -#define FLAG_V cpustate->flag_v /* Overflow Flag */ -#define FLAG_D cpustate->flag_d /* Decimal Mode Flag */ -#define FLAG_I cpustate->flag_i /* Interrupt Mask Flag */ -#define FLAG_Z cpustate->flag_z /* Zero Flag (inverted) */ -#define FLAG_C cpustate->flag_c /* Carry Flag */ -#define LINE_IRQ cpustate->line_irq /* Status of the IRQ line */ -#define LINE_NMI cpustate->line_nmi /* Status of the NMI line */ -#define REGISTER_IR cpustate->ir /* Instruction Register */ -#define INT_ACK cpustate->int_ack /* Interrupt Acknowledge function pointer */ -#define READ_VECTOR cpustate->read_vector /* Vector reading override */ -#define CLOCKS cpustate->ICount /* Clock cycles remaining */ -#define IRQ_DELAY cpustate->irq_delay /* Delay 1 instruction before checking IRQ */ -#define CPU_STOPPED cpustate->stopped /* Stopped status of the CPU */ - -#define FTABLE_OPCODES cpustate->opcodes -#define FTABLE_GET_REG cpustate->get_reg -#define FTABLE_SET_REG cpustate->set_reg -#define FTABLE_SET_LINE cpustate->set_line -#define FTABLE_EXECUTE cpustate->execute - -#define SRC cpustate->source /* Source Operand */ -#define DST cpustate->destination /* Destination Operand */ - -#define STOP_LEVEL_WAI 1 -#define STOP_LEVEL_STOP 2 - -#define EXECUTION_MODE_M0X0 0 -#define EXECUTION_MODE_M0X1 1 -#define EXECUTION_MODE_M1X0 2 -#define EXECUTION_MODE_M1X1 3 -#define EXECUTION_MODE_E 4 +#define REGISTER_A cpustate->a /* Accumulator */ +#define REGISTER_B cpustate->b /* Accumulator hi byte */ +#define REGISTER_X cpustate->x /* Index X Register */ +#define REGISTER_Y cpustate->y /* Index Y Register */ +#define REGISTER_S cpustate->s /* Stack Pointer */ +#define REGISTER_PC cpustate->pc /* Program Counter */ +#define REGISTER_PPC cpustate->ppc /* Previous Program Counter */ +#define REGISTER_PB cpustate->pb /* Program Bank */ +#define REGISTER_DB cpustate->db /* Data Bank */ +#define REGISTER_D cpustate->d /* Direct Register */ +#define FLAG_E cpustate->flag_e /* Emulation Mode Flag */ +#define FLAG_M cpustate->flag_m /* Memory/Accumulator Select Flag */ +#define FLAG_X cpustate->flag_x /* Index Select Flag */ +#define FLAG_N cpustate->flag_n /* Negative Flag */ +#define FLAG_V cpustate->flag_v /* Overflow Flag */ +#define FLAG_D cpustate->flag_d /* Decimal Mode Flag */ +#define FLAG_I cpustate->flag_i /* Interrupt Mask Flag */ +#define FLAG_Z cpustate->flag_z /* Zero Flag (inverted) */ +#define FLAG_C cpustate->flag_c /* Carry Flag */ +#define LINE_IRQ cpustate->line_irq /* Status of the IRQ line */ +#define LINE_NMI cpustate->line_nmi /* Status of the NMI line */ +#define REGISTER_IR cpustate->ir /* Instruction Register */ +#define INT_ACK cpustate->int_ack /* Interrupt Acknowledge function pointer */ +#define READ_VECTOR cpustate->read_vector /* Vector reading override */ +#define CLOCKS cpustate->ICount /* Clock cycles remaining */ +#define IRQ_DELAY cpustate->irq_delay /* Delay 1 instruction before checking IRQ */ +#define CPU_STOPPED cpustate->stopped /* Stopped status of the CPU */ + +#define FTABLE_OPCODES cpustate->opcodes +#define FTABLE_GET_REG cpustate->get_reg +#define FTABLE_SET_REG cpustate->set_reg +#define FTABLE_SET_LINE cpustate->set_line +#define FTABLE_EXECUTE cpustate->execute + +#define SRC cpustate->source /* Source Operand */ +#define DST cpustate->destination /* Destination Operand */ + +#define STOP_LEVEL_WAI 1 +#define STOP_LEVEL_STOP 2 + +#define EXECUTION_MODE_M0X0 0 +#define EXECUTION_MODE_M0X1 1 +#define EXECUTION_MODE_M1X0 2 +#define EXECUTION_MODE_M1X1 3 +#define EXECUTION_MODE_E 4 INLINE void g65816i_set_execution_mode(g65816i_cpu_struct *cpustate, uint mode) { @@ -182,80 +182,80 @@ INLINE void g65816i_set_execution_mode(g65816i_cpu_struct *cpustate, uint mode) -#define VECTOR_RESET 0xfffc /* Reset */ -#define VECTOR_IRQ_E 0xfffe /* Interrupt Request */ -#define VECTOR_NMI_E 0xfffa /* Non-Maskable Interrupt */ -#define VECTOR_ABORT_E 0xfff8 /* ABORT asserted */ -#define VECTOR_BRK_E 0xfffe /* Break Instruction */ -#define VECTOR_COP_E 0xfff4 /* Coprocessor instruction */ +#define VECTOR_RESET 0xfffc /* Reset */ +#define VECTOR_IRQ_E 0xfffe /* Interrupt Request */ +#define VECTOR_NMI_E 0xfffa /* Non-Maskable Interrupt */ +#define VECTOR_ABORT_E 0xfff8 /* ABORT asserted */ +#define VECTOR_BRK_E 0xfffe /* Break Instruction */ +#define VECTOR_COP_E 0xfff4 /* Coprocessor instruction */ -#define VECTOR_IRQ_N 0xffee /* Interrupt Request */ -#define VECTOR_NMI_N 0xffea /* Non-Maskable Interrupt */ -#define VECTOR_ABORT_N 0xffe8 /* ABORT asserted */ -#define VECTOR_BRK_N 0xffe6 /* Break Instruction */ -#define VECTOR_COP_N 0xffe4 /* Coprocessor instruction */ +#define VECTOR_IRQ_N 0xffee /* Interrupt Request */ +#define VECTOR_NMI_N 0xffea /* Non-Maskable Interrupt */ +#define VECTOR_ABORT_N 0xffe8 /* ABORT asserted */ +#define VECTOR_BRK_N 0xffe6 /* Break Instruction */ +#define VECTOR_COP_N 0xffe4 /* Coprocessor instruction */ /* ======================================================================== */ /* ================================= CLOCK ================================ */ /* ======================================================================== */ -#define CLK_OP 1 -#define CLK_R8 cpustate->rw8_cycles -#define CLK_R16 cpustate->rw16_cycles -#define CLK_R24 cpustate->rw24_cycles -#define CLK_W8 cpustate->rw8_cycles -#define CLK_W16 cpustate->rw16_cycles -#define CLK_W24 cpustate->rw24_cycles -#define CLK_RMW8 cpustate->rw8_cycles+cpustate->rw8_cycles + 1 -#define CLK_RMW16 cpustate->rw16_cycles+cpustate->rw16_cycles + 1 - -#define CLK_IMPLIED 1 -#define CLK_IMPLIED 1 -#define CLK_RELATIVE_8 1 -#define CLK_RELATIVE_16 2 -#define CLK_IMM 0 -#define CLK_AI 4 -#define CLK_AXI 4 -#define CLK_A 2 -#define CLK_AL 3 -#define CLK_ALX 3 -#define CLK_AX 2 -#define CLK_AY 2 -#define CLK_D 1 -#define CLK_DI 3 -#define CLK_DIY 3 -#define CLK_DLI 4 -#define CLK_DLIY 4 -#define CLK_DX 2 -#define CLK_DXI 4 -#define CLK_DY 2 -#define CLK_S 2 -#define CLK_SIY 5 +#define CLK_OP 1 +#define CLK_R8 cpustate->rw8_cycles +#define CLK_R16 cpustate->rw16_cycles +#define CLK_R24 cpustate->rw24_cycles +#define CLK_W8 cpustate->rw8_cycles +#define CLK_W16 cpustate->rw16_cycles +#define CLK_W24 cpustate->rw24_cycles +#define CLK_RMW8 cpustate->rw8_cycles+cpustate->rw8_cycles + 1 +#define CLK_RMW16 cpustate->rw16_cycles+cpustate->rw16_cycles + 1 + +#define CLK_IMPLIED 1 +#define CLK_IMPLIED 1 +#define CLK_RELATIVE_8 1 +#define CLK_RELATIVE_16 2 +#define CLK_IMM 0 +#define CLK_AI 4 +#define CLK_AXI 4 +#define CLK_A 2 +#define CLK_AL 3 +#define CLK_ALX 3 +#define CLK_AX 2 +#define CLK_AY 2 +#define CLK_D 1 +#define CLK_DI 3 +#define CLK_DIY 3 +#define CLK_DLI 4 +#define CLK_DLIY 4 +#define CLK_DX 2 +#define CLK_DXI 4 +#define CLK_DY 2 +#define CLK_S 2 +#define CLK_SIY 5 /* AX and AY addressing modes take 1 extra cycle when writing */ -#define CLK_W_IMM 0 -#define CLK_W_AI 4 -#define CLK_W_AXI 4 -#define CLK_W_A 2 -#define CLK_W_AL 3 -#define CLK_W_ALX 3 -#define CLK_W_AX 3 -#define CLK_W_AY 3 -#define CLK_W_D 1 -#define CLK_W_DI 3 -#define CLK_W_DIY 3 -#define CLK_W_DLI 4 -#define CLK_W_DLIY 4 -#define CLK_W_DX 2 -#define CLK_W_DXI 4 -#define CLK_W_DY 2 -#define CLK_W_S 2 -#define CLK_W_SIY 5 - -#define CLK(A) CLOCKS -= (cpustate->cpu_type == CPU_TYPE_G65816 ? A : A*6) -#define CLK_BUS(A) CLOCKS -= A -#define USE_ALL_CLKS() CLOCKS = 0 +#define CLK_W_IMM 0 +#define CLK_W_AI 4 +#define CLK_W_AXI 4 +#define CLK_W_A 2 +#define CLK_W_AL 3 +#define CLK_W_ALX 3 +#define CLK_W_AX 3 +#define CLK_W_AY 3 +#define CLK_W_D 1 +#define CLK_W_DI 3 +#define CLK_W_DIY 3 +#define CLK_W_DLI 4 +#define CLK_W_DLIY 4 +#define CLK_W_DX 2 +#define CLK_W_DXI 4 +#define CLK_W_DY 2 +#define CLK_W_S 2 +#define CLK_W_SIY 5 + +#define CLK(A) CLOCKS -= (cpustate->cpu_type == CPU_TYPE_G65816 ? A : A*6) +#define CLK_BUS(A) CLOCKS -= A +#define USE_ALL_CLKS() CLOCKS = 0 /* ======================================================================== */ @@ -264,62 +264,62 @@ INLINE void g65816i_set_execution_mode(g65816i_cpu_struct *cpustate, uint mode) /* Flag positions in Processor Status Register */ /* common */ -#define FLAGPOS_N BIT_7 /* Negative */ -#define FLAGPOS_V BIT_6 /* Overflow */ -#define FLAGPOS_D BIT_3 /* Decimal Mode */ -#define FLAGPOS_I BIT_2 /* Interrupt Mask */ -#define FLAGPOS_Z BIT_1 /* Zero */ -#define FLAGPOS_C BIT_0 /* Carry */ +#define FLAGPOS_N BIT_7 /* Negative */ +#define FLAGPOS_V BIT_6 /* Overflow */ +#define FLAGPOS_D BIT_3 /* Decimal Mode */ +#define FLAGPOS_I BIT_2 /* Interrupt Mask */ +#define FLAGPOS_Z BIT_1 /* Zero */ +#define FLAGPOS_C BIT_0 /* Carry */ /* emulation */ -#define FLAGPOS_R BIT_5 /* Reserved */ -#define FLAGPOS_B BIT_4 /* BRK Instruction */ +#define FLAGPOS_R BIT_5 /* Reserved */ +#define FLAGPOS_B BIT_4 /* BRK Instruction */ /* native */ -#define FLAGPOS_M BIT_5 /* Mem/Reg Select */ -#define FLAGPOS_X BIT_4 /* Index Select */ - -#define EFLAG_SET 1 -#define EFLAG_CLEAR 0 -#define MFLAG_SET FLAGPOS_M -#define MFLAG_CLEAR 0 -#define XFLAG_SET FLAGPOS_X -#define XFLAG_CLEAR 0 -#define NFLAG_SET 0x80 -#define NFLAG_CLEAR 0 -#define VFLAG_SET 0x80 -#define VFLAG_CLEAR 0 -#define DFLAG_SET FLAGPOS_D -#define DFLAG_CLEAR 0 -#define IFLAG_SET FLAGPOS_I -#define IFLAG_CLEAR 0 -#define BFLAG_SET FLAGPOS_B -#define BFLAG_CLEAR 0 -#define ZFLAG_SET 0 -#define ZFLAG_CLEAR 1 -#define CFLAG_SET 0x100 -#define CFLAG_CLEAR 0 +#define FLAGPOS_M BIT_5 /* Mem/Reg Select */ +#define FLAGPOS_X BIT_4 /* Index Select */ + +#define EFLAG_SET 1 +#define EFLAG_CLEAR 0 +#define MFLAG_SET FLAGPOS_M +#define MFLAG_CLEAR 0 +#define XFLAG_SET FLAGPOS_X +#define XFLAG_CLEAR 0 +#define NFLAG_SET 0x80 +#define NFLAG_CLEAR 0 +#define VFLAG_SET 0x80 +#define VFLAG_CLEAR 0 +#define DFLAG_SET FLAGPOS_D +#define DFLAG_CLEAR 0 +#define IFLAG_SET FLAGPOS_I +#define IFLAG_CLEAR 0 +#define BFLAG_SET FLAGPOS_B +#define BFLAG_CLEAR 0 +#define ZFLAG_SET 0 +#define ZFLAG_CLEAR 1 +#define CFLAG_SET 0x100 +#define CFLAG_CLEAR 0 /* Codition code tests */ -#define COND_CC() (!(FLAG_C&0x100)) /* Carry Clear */ -#define COND_CS() (FLAG_C&0x100) /* Carry Set */ -#define COND_EQ() (!FLAG_Z) /* Equal */ -#define COND_NE() FLAG_Z /* Not Equal */ -#define COND_MI() (FLAG_N&0x80) /* Minus */ -#define COND_PL() (!(FLAG_N&0x80)) /* Plus */ -#define COND_VC() (!(FLAG_V&0x80)) /* Overflow Clear */ -#define COND_VS() (FLAG_V&0x80) /* Overflow Set */ +#define COND_CC() (!(FLAG_C&0x100)) /* Carry Clear */ +#define COND_CS() (FLAG_C&0x100) /* Carry Set */ +#define COND_EQ() (!FLAG_Z) /* Equal */ +#define COND_NE() FLAG_Z /* Not Equal */ +#define COND_MI() (FLAG_N&0x80) /* Minus */ +#define COND_PL() (!(FLAG_N&0x80)) /* Plus */ +#define COND_VC() (!(FLAG_V&0x80)) /* Overflow Clear */ +#define COND_VS() (FLAG_V&0x80) /* Overflow Set */ /* Set Overflow flag in math operations */ -#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R)) -#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8) -#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D)) -#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8) +#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R)) +#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8) +#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D)) +#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8) -#define CFLAG_8(A) (A) -#define CFLAG_16(A) ((A)>>8) -#define NFLAG_8(A) (A) -#define NFLAG_16(A) ((A)>>8) +#define CFLAG_8(A) (A) +#define CFLAG_16(A) ((A)>>8) +#define NFLAG_8(A) (A) +#define NFLAG_16(A) ((A)>>8) -#define CFLAG_AS_1() ((FLAG_C>>8)&1) +#define CFLAG_AS_1() ((FLAG_C>>8)&1) diff --git a/src/emu/cpu/g65816/g65816ds.c b/src/emu/cpu/g65816/g65816ds.c index dd4a464e6c5..1228d7283ce 100644 --- a/src/emu/cpu/g65816/g65816ds.c +++ b/src/emu/cpu/g65816/g65816ds.c @@ -49,28 +49,28 @@ enum enum { - ADC , AND , ASL , BCC , BCS , BEQ , BIT , BMI , BNE , BPL , BRA , - BRK , BRL , BVC , BVS , CLC , CLD , CLI , CLV , CMP , COP , CPX , - CPY , DEA , DEC , DEX , DEY , EOR , INA , INC , INX , INY , JML , - JMP , JSL , JSR , LDA , LDX , LDY , LSR , MVN , MVP , NOP , ORA , - PEA , PEI , PER , PHA , PHB , PHD , PHK , PHP , PHX , PHY , PLA , - PLB , PLD , PLP , PLX , PLY , REP , ROL , ROR , RTI , RTL , RTS , - SBC , SEC , SED , SEI , SEP , STA , STP , STX , STY , STZ , TAX , - TAY , TCS , TCD , TDC , TRB , TSB , TSC , TSX , TXA , TXS , TXY , - TYA , TYX , WAI , WDM , XBA , XCE + ADC , AND , ASL , BCC , BCS , BEQ , BIT , BMI , BNE , BPL , BRA , + BRK , BRL , BVC , BVS , CLC , CLD , CLI , CLV , CMP , COP , CPX , + CPY , DEA , DEC , DEX , DEY , EOR , INA , INC , INX , INY , JML , + JMP , JSL , JSR , LDA , LDX , LDY , LSR , MVN , MVP , NOP , ORA , + PEA , PEI , PER , PHA , PHB , PHD , PHK , PHP , PHX , PHY , PLA , + PLB , PLD , PLP , PLX , PLY , REP , ROL , ROR , RTI , RTL , RTS , + SBC , SEC , SED , SEI , SEP , STA , STP , STX , STY , STZ , TAX , + TAY , TCS , TCD , TDC , TRB , TSB , TSC , TSX , TXA , TXS , TXY , + TYA , TYX , WAI , WDM , XBA , XCE }; static const char *const g_opnames[] = { - "ADC", "AND", "ASL", "BCC", "BCS", "BEQ", "BIT", "BMI", "BNE", "BPL", "BRA", - "BRK", "BRL", "BVC", "BVS", "CLC", "CLD", "CLI", "CLV", "CMP", "COP", "CPX", - "CPY", "DEA", "DEC", "DEX", "DEY", "EOR", "INA", "INC", "INX", "INY", "JML", - "JMP", "JSL", "JSR", "LDA", "LDX", "LDY", "LSR", "MVN", "MVP", "NOP", "ORA", - "PEA", "PEI", "PER", "PHA", "PHB", "PHD", "PHK", "PHP", "PHX", "PHY", "PLA", - "PLB", "PLD", "PLP", "PLX", "PLY", "REP", "ROL", "ROR", "RTI", "RTL", "RTS", - "SBC", "SEC", "SED", "SEI", "SEP", "STA", "STP", "STX", "STY", "STZ", "TAX", - "TAY", "TCS", "TCD", "TDC", "TRB", "TSB", "TSC", "TSX", "TXA", "TXS", "TXY", - "TYA", "TYX", "WAI", "WDM", "XBA", "XCE" + "ADC", "AND", "ASL", "BCC", "BCS", "BEQ", "BIT", "BMI", "BNE", "BPL", "BRA", + "BRK", "BRL", "BVC", "BVS", "CLC", "CLD", "CLI", "CLV", "CMP", "COP", "CPX", + "CPY", "DEA", "DEC", "DEX", "DEY", "EOR", "INA", "INC", "INX", "INY", "JML", + "JMP", "JSL", "JSR", "LDA", "LDX", "LDY", "LSR", "MVN", "MVP", "NOP", "ORA", + "PEA", "PEI", "PER", "PHA", "PHB", "PHD", "PHK", "PHP", "PHX", "PHY", "PLA", + "PLB", "PLD", "PLP", "PLX", "PLY", "REP", "ROL", "ROR", "RTI", "RTL", "RTS", + "SBC", "SEC", "SED", "SEI", "SEP", "STA", "STP", "STX", "STY", "STZ", "TAX", + "TAY", "TCS", "TCD", "TDC", "TRB", "TSB", "TSC", "TSX", "TXA", "TXS", "TXY", + "TYA", "TYX", "WAI", "WDM", "XBA", "XCE" }; static const opcode_struct g_opcodes[256] = @@ -165,30 +165,30 @@ INLINE unsigned int read_24(unsigned int address) INLINE char* int_8_str(unsigned int val) { - static char str[20]; + static char str[20]; - val &= 0xff; + val &= 0xff; - if(val & 0x80) - sprintf(str, "-$%x", (0-val) & 0x7f); - else - sprintf(str, "$%x", val & 0x7f); + if(val & 0x80) + sprintf(str, "-$%x", (0-val) & 0x7f); + else + sprintf(str, "$%x", val & 0x7f); - return str; + return str; } INLINE char* int_16_str(unsigned int val) { - static char str[20]; + static char str[20]; - val &= 0xffff; + val &= 0xffff; - if(val & 0x8000) - sprintf(str, "-$%x", (0-val) & 0x7fff); - else - sprintf(str, "$%x", val & 0x7fff); + if(val & 0x8000) + sprintf(str, "-$%x", (0-val) & 0x7fff); + else + sprintf(str, "$%x", val & 0x7fff); - return str; + return str; } diff --git a/src/emu/cpu/g65816/g65816op.h b/src/emu/cpu/g65816/g65816op.h index a56e85abc65..2748b37aa5a 100644 --- a/src/emu/cpu/g65816/g65816op.h +++ b/src/emu/cpu/g65816/g65816op.h @@ -35,17 +35,17 @@ #undef VECTOR_COP #if FLAG_SET_E -#define VECTOR_IRQ VECTOR_IRQ_E -#define VECTOR_NMI VECTOR_NMI_E -#define VECTOR_ABORT VECTOR_ABORT_E -#define VECTOR_BRK VECTOR_BRK_E -#define VECTOR_COP VECTOR_COP_E +#define VECTOR_IRQ VECTOR_IRQ_E +#define VECTOR_NMI VECTOR_NMI_E +#define VECTOR_ABORT VECTOR_ABORT_E +#define VECTOR_BRK VECTOR_BRK_E +#define VECTOR_COP VECTOR_COP_E #else /* FLAG_SET_E */ -#define VECTOR_IRQ VECTOR_IRQ_N -#define VECTOR_NMI VECTOR_NMI_N -#define VECTOR_ABORT VECTOR_ABORT_N -#define VECTOR_BRK VECTOR_BRK_N -#define VECTOR_COP VECTOR_COP_N +#define VECTOR_IRQ VECTOR_IRQ_N +#define VECTOR_NMI VECTOR_NMI_N +#define VECTOR_ABORT VECTOR_ABORT_N +#define VECTOR_BRK VECTOR_BRK_N +#define VECTOR_COP VECTOR_COP_N #endif @@ -111,13 +111,13 @@ INLINE void g65816i_write_8_direct(g65816i_cpu_struct *cpustate, uint address, u INLINE uint g65816i_read_16_normal(g65816i_cpu_struct *cpustate, uint address) { - return g65816i_read_8_normal(cpustate, address) | + return g65816i_read_8_normal(cpustate, address) | (g65816i_read_8_normal(cpustate, address+1)<<8); } INLINE uint g65816i_read_16_immediate(g65816i_cpu_struct *cpustate, uint address) { - return g65816i_read_8_immediate(cpustate, address) | + return g65816i_read_8_immediate(cpustate, address) | (g65816i_read_8_immediate(cpustate, address+1)<<8); } @@ -129,7 +129,7 @@ INLINE uint g65816i_read_16_direct(g65816i_cpu_struct *cpustate, uint address) INLINE uint g65816i_read_16_vector(g65816i_cpu_struct *cpustate, uint address) { - return g65816i_read_8_vector(cpustate, address) | + return g65816i_read_8_vector(cpustate, address) | (g65816i_read_8_vector(cpustate, address+1)<<8); } @@ -147,21 +147,21 @@ INLINE void g65816i_write_16_direct(g65816i_cpu_struct *cpustate, uint address, INLINE uint g65816i_read_24_normal(g65816i_cpu_struct *cpustate, uint address) { - return g65816i_read_8_normal(cpustate, address) | + return g65816i_read_8_normal(cpustate, address) | (g65816i_read_8_normal(cpustate, address+1)<<8) | (g65816i_read_8_normal(cpustate, address+2)<<16); } INLINE uint g65816i_read_24_immediate(g65816i_cpu_struct *cpustate, uint address) { - return g65816i_read_8_immediate(cpustate, address) | + return g65816i_read_8_immediate(cpustate, address) | (g65816i_read_8_immediate(cpustate, address+1)<<8) | (g65816i_read_8_immediate(cpustate, address+2)<<16); } INLINE uint g65816i_read_24_direct(g65816i_cpu_struct *cpustate, uint address) { - return g65816i_read_8_direct(cpustate, address) | + return g65816i_read_8_direct(cpustate, address) | (g65816i_read_8_direct(cpustate, address+1)<<8) | (g65816i_read_8_direct(cpustate, address+2)<<16); } @@ -343,13 +343,13 @@ INLINE void g65816i_set_flag_i(g65816i_cpu_struct *cpustate, uint value) /* Get the Processor Status Register */ INLINE uint g65816i_get_reg_p(g65816i_cpu_struct *cpustate) { - return (FLAG_N&0x80) | - ((FLAG_V>>1)&0x40) | - FLAG_M | - FLAG_X | - FLAG_D | - FLAG_I | - ((!FLAG_Z)<<1) | + return (FLAG_N&0x80) | + ((FLAG_V>>1)&0x40) | + FLAG_M | + FLAG_X | + FLAG_D | + FLAG_I | + ((!FLAG_Z)<<1) | ((FLAG_C>>8)&1); } @@ -461,169 +461,169 @@ INLINE void g65816i_check_maskable_interrupt(g65816i_cpu_struct *cpustate) /* ======================================================================== */ /* Effective-address based memory access macros */ -#define read_8_NORM(A) g65816i_read_8_normal(cpustate, A) -#define read_8_IMM(A) g65816i_read_8_immediate(cpustate, A) -#define read_8_D(A) g65816i_read_8_direct(cpustate, A) -#define read_8_A(A) g65816i_read_8_normal(cpustate, A) -#define read_8_AL(A) g65816i_read_8_normal(cpustate, A) -#define read_8_DX(A) g65816i_read_8_direct(cpustate, A) -#define read_8_DY(A) g65816i_read_8_direct(cpustate, A) -#define read_8_AX(A) g65816i_read_8_normal(cpustate, A) -#define read_8_ALX(A) g65816i_read_8_normal(cpustate, A) -#define read_8_AY(A) g65816i_read_8_normal(cpustate, A) -#define read_8_DI(A) g65816i_read_8_normal(cpustate, A) -#define read_8_DLI(A) g65816i_read_8_normal(cpustate, A) -#define read_8_AI(A) g65816i_read_8_normal(cpustate, A) -#define read_8_ALI(A) g65816i_read_8_normal(cpustate, A) -#define read_8_DXI(A) g65816i_read_8_normal(cpustate, A) -#define read_8_DIY(A) g65816i_read_8_normal(cpustate, A) -#define read_8_DLIY(A) g65816i_read_8_normal(cpustate, A) -#define read_8_AXI(A) g65816i_read_8_normal(cpustate, A) -#define read_8_S(A) g65816i_read_8_normal(cpustate, A) -#define read_8_SIY(A) g65816i_read_8_normal(cpustate, A) - -#define read_16_NORM(A) g65816i_read_16_normal(cpustate, A) -#define read_16_IMM(A) g65816i_read_16_immediate(cpustate, A) -#define read_16_D(A) g65816i_read_16_direct(cpustate, A) -#define read_16_A(A) g65816i_read_16_normal(cpustate, A) -#define read_16_AL(A) g65816i_read_16_normal(cpustate, A) -#define read_16_DX(A) g65816i_read_16_direct(cpustate, A) -#define read_16_DY(A) g65816i_read_16_direct(cpustate, A) -#define read_16_AX(A) g65816i_read_16_normal(cpustate, A) -#define read_16_ALX(A) g65816i_read_16_normal(cpustate, A) -#define read_16_AY(A) g65816i_read_16_normal(cpustate, A) -#define read_16_DI(A) g65816i_read_16_normal(cpustate, A) -#define read_16_DLI(A) g65816i_read_16_normal(cpustate, A) -#define read_16_AI(A) g65816i_read_16_normal(cpustate, A) -#define read_16_ALI(A) g65816i_read_16_normal(cpustate, A) -#define read_16_DXI(A) g65816i_read_16_normal(cpustate, A) -#define read_16_DIY(A) g65816i_read_16_normal(cpustate, A) -#define read_16_DLIY(A) g65816i_read_16_normal(cpustate, A) -#define read_16_AXI(A) g65816i_read_16_normal(cpustate, A) -#define read_16_S(A) g65816i_read_16_normal(cpustate, A) -#define read_16_SIY(A) g65816i_read_16_normal(cpustate, A) - -#define read_24_NORM(A) g65816i_read_24_normal(cpustate, A) -#define read_24_IMM(A) g65816i_read_24_immediate(cpustate, A) -#define read_24_D(A) g65816i_read_24_direct(cpustate, A) -#define read_24_A(A) g65816i_read_24_normal(cpustate, A) -#define read_24_AL(A) g65816i_read_24_normal(cpustate, A) -#define read_24_DX(A) g65816i_read_24_direct(cpustate, A) -#define read_24_DY(A) g65816i_read_24_direct(cpustate, A) -#define read_24_AX(A) g65816i_read_24_normal(cpustate, A) -#define read_24_ALX(A) g65816i_read_24_normal(cpustate, A) -#define read_24_AY(A) g65816i_read_24_normal(cpustate, A) -#define read_24_DI(A) g65816i_read_24_normal(cpustate, A) -#define read_24_DLI(A) g65816i_read_24_normal(cpustate, A) -#define read_24_AI(A) g65816i_read_24_normal(cpustate, A) -#define read_24_ALI(A) g65816i_read_24_normal(cpustate, A) -#define read_24_DXI(A) g65816i_read_24_normal(cpustate, A) -#define read_24_DIY(A) g65816i_read_24_normal(cpustate, A) -#define read_24_DLIY(A) g65816i_read_24_normal(cpustate, A) -#define read_24_AXI(A) g65816i_read_24_normal(cpustate, A) -#define read_24_S(A) g65816i_read_24_normal(cpustate, A) -#define read_24_SIY(A) g65816i_read_24_normal(cpustate, A) - -#define write_8_NORM(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_D(A, V) g65816i_write_8_direct(cpustate, A, V) -#define write_8_A(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_AL(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_DX(A, V) g65816i_write_8_direct(cpustate, A, V) -#define write_8_DY(A, V) g65816i_write_8_direct(cpustate, A, V) -#define write_8_AX(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_ALX(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_AY(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_DI(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_DLI(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_AI(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_ALI(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_DXI(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_DIY(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_DLIY(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_AXI(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_S(A, V) g65816i_write_8_normal(cpustate, A, V) -#define write_8_SIY(A, V) g65816i_write_8_normal(cpustate, A, V) - -#define write_16_NORM(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_D(A, V) g65816i_write_16_direct(cpustate, A, V) -#define write_16_A(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_AL(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_DX(A, V) g65816i_write_16_direct(cpustate, A, V) -#define write_16_DY(A, V) g65816i_write_16_direct(cpustate, A, V) -#define write_16_AX(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_ALX(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_AY(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_DI(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_DLI(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_AI(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_ALI(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_DXI(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_DIY(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_DLIY(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_AXI(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_S(A, V) g65816i_write_16_normal(cpustate, A, V) -#define write_16_SIY(A, V) g65816i_write_16_normal(cpustate, A, V) - - -#define OPER_8_IMM(cpustate) read_8_IMM(EA_IMM8(cpustate)) -#define OPER_8_D(cpustate) read_8_D(EA_D(cpustate)) -#define OPER_8_A(cpustate) read_8_A(EA_A(cpustate)) -#define OPER_8_AL(cpustate) read_8_AL(EA_AL(cpustate)) -#define OPER_8_DX(cpustate) read_8_DX(EA_DX(cpustate)) -#define OPER_8_DY(cpustate) read_8_DY(EA_DY(cpustate)) -#define OPER_8_AX(cpustate) read_8_AX(EA_AX(cpustate)) -#define OPER_8_ALX(cpustate) read_8_ALX(EA_ALX(cpustate)) -#define OPER_8_AY(cpustate) read_8_AY(EA_AY(cpustate)) -#define OPER_8_DI(cpustate) read_8_DI(EA_DI(cpustate)) -#define OPER_8_DLI(cpustate) read_8_DLI(EA_DLI(cpustate)) -#define OPER_8_AI(cpustate) read_8_AI(EA_AI(cpustate)) -#define OPER_8_ALI(cpustate) read_8_ALI(EA_ALI(cpustate)) -#define OPER_8_DXI(cpustate) read_8_DXI(EA_DXI(cpustate)) -#define OPER_8_DIY(cpustate) read_8_DIY(EA_DIY(cpustate)) -#define OPER_8_DLIY(cpustate) read_8_DLIY(EA_DLIY(cpustate)) -#define OPER_8_AXI(cpustate) read_8_AXI(EA_AXI(cpustate)) -#define OPER_8_S(cpustate) read_8_S(EA_S(cpustate)) -#define OPER_8_SIY(cpustate) read_8_SIY(EA_SIY(cpustate)) - -#define OPER_16_IMM(cpustate) read_16_IMM(EA_IMM16(cpustate)) -#define OPER_16_D(cpustate) read_16_D(EA_D(cpustate)) -#define OPER_16_A(cpustate) read_16_A(EA_A(cpustate)) -#define OPER_16_AL(cpustate) read_16_AL(EA_AL(cpustate)) -#define OPER_16_DX(cpustate) read_16_DX(EA_DX(cpustate)) -#define OPER_16_DY(cpustate) read_16_DY(EA_DY(cpustate)) -#define OPER_16_AX(cpustate) read_16_AX(EA_AX(cpustate)) -#define OPER_16_ALX(cpustate) read_16_ALX(EA_ALX(cpustate)) -#define OPER_16_AY(cpustate) read_16_AY(EA_AY(cpustate)) -#define OPER_16_DI(cpustate) read_16_DI(EA_DI(cpustate)) -#define OPER_16_DLI(cpustate) read_16_DLI(EA_DLI(cpustate)) -#define OPER_16_AI(cpustate) read_16_AI(EA_AI(cpustate)) -#define OPER_16_ALI(cpustate) read_16_ALI(EA_ALI(cpustate)) -#define OPER_16_DXI(cpustate) read_16_DXI(EA_DXI(cpustate)) -#define OPER_16_DIY(cpustate) read_16_DIY(EA_DIY(cpustate)) -#define OPER_16_DLIY(cpustate) read_16_DLIY(EA_DLIY(cpustate)) -#define OPER_16_AXI(cpustate) read_16_AXI(EA_AXI(cpustate)) -#define OPER_16_S(cpustate) read_16_S(EA_S(cpustate)) -#define OPER_16_SIY(cpustate) read_16_SIY(EA_SIY(cpustate)) - -#define OPER_24_IMM(cpustate) read_24_IMM(EA_IMM24(cpustate)) -#define OPER_24_D(cpustate) read_24_D(EA_D(cpustate)) -#define OPER_24_A(cpustate) read_24_A(EA_A(cpustate)) -#define OPER_24_AL(cpustate) read_24_AL(EA_AL(cpustate)) -#define OPER_24_DX(cpustate) read_24_DX(EA_DX(cpustate)) -#define OPER_24_DY(cpustate) read_24_DY(EA_DY(cpustate)) -#define OPER_24_AX(cpustate) read_24_AX(EA_AX(cpustate)) -#define OPER_24_ALX(cpustate) read_24_ALX(EA_ALX(cpustate)) -#define OPER_24_AY(cpustate) read_24_AY(EA_AY(cpustate)) -#define OPER_24_DI(cpustate) read_24_DI(EA_DI(cpustate)) -#define OPER_24_DLI(cpustate) read_24_DLI(EA_DLI(cpustate)) -#define OPER_24_AI(cpustate) read_24_AI(EA_AI(cpustate)) -#define OPER_24_ALI(cpustate) read_24_ALI(EA_ALI(cpustate)) -#define OPER_24_DXI(cpustate) read_24_DXI(EA_DXI(cpustate)) -#define OPER_24_DIY(cpustate) read_24_DIY(EA_DIY(cpustate)) -#define OPER_24_DLIY(cpustate) read_24_DLIY(EA_DLIY(cpustate)) -#define OPER_24_AXI(cpustate) read_24_AXI(EA_AXI(cpustate)) -#define OPER_24_S(cpustate) read_24_S(EA_S(cpustate)) -#define OPER_24_SIY(cpustate) read_24_SIY(EA_SIY(cpustate)) +#define read_8_NORM(A) g65816i_read_8_normal(cpustate, A) +#define read_8_IMM(A) g65816i_read_8_immediate(cpustate, A) +#define read_8_D(A) g65816i_read_8_direct(cpustate, A) +#define read_8_A(A) g65816i_read_8_normal(cpustate, A) +#define read_8_AL(A) g65816i_read_8_normal(cpustate, A) +#define read_8_DX(A) g65816i_read_8_direct(cpustate, A) +#define read_8_DY(A) g65816i_read_8_direct(cpustate, A) +#define read_8_AX(A) g65816i_read_8_normal(cpustate, A) +#define read_8_ALX(A) g65816i_read_8_normal(cpustate, A) +#define read_8_AY(A) g65816i_read_8_normal(cpustate, A) +#define read_8_DI(A) g65816i_read_8_normal(cpustate, A) +#define read_8_DLI(A) g65816i_read_8_normal(cpustate, A) +#define read_8_AI(A) g65816i_read_8_normal(cpustate, A) +#define read_8_ALI(A) g65816i_read_8_normal(cpustate, A) +#define read_8_DXI(A) g65816i_read_8_normal(cpustate, A) +#define read_8_DIY(A) g65816i_read_8_normal(cpustate, A) +#define read_8_DLIY(A) g65816i_read_8_normal(cpustate, A) +#define read_8_AXI(A) g65816i_read_8_normal(cpustate, A) +#define read_8_S(A) g65816i_read_8_normal(cpustate, A) +#define read_8_SIY(A) g65816i_read_8_normal(cpustate, A) + +#define read_16_NORM(A) g65816i_read_16_normal(cpustate, A) +#define read_16_IMM(A) g65816i_read_16_immediate(cpustate, A) +#define read_16_D(A) g65816i_read_16_direct(cpustate, A) +#define read_16_A(A) g65816i_read_16_normal(cpustate, A) +#define read_16_AL(A) g65816i_read_16_normal(cpustate, A) +#define read_16_DX(A) g65816i_read_16_direct(cpustate, A) +#define read_16_DY(A) g65816i_read_16_direct(cpustate, A) +#define read_16_AX(A) g65816i_read_16_normal(cpustate, A) +#define read_16_ALX(A) g65816i_read_16_normal(cpustate, A) +#define read_16_AY(A) g65816i_read_16_normal(cpustate, A) +#define read_16_DI(A) g65816i_read_16_normal(cpustate, A) +#define read_16_DLI(A) g65816i_read_16_normal(cpustate, A) +#define read_16_AI(A) g65816i_read_16_normal(cpustate, A) +#define read_16_ALI(A) g65816i_read_16_normal(cpustate, A) +#define read_16_DXI(A) g65816i_read_16_normal(cpustate, A) +#define read_16_DIY(A) g65816i_read_16_normal(cpustate, A) +#define read_16_DLIY(A) g65816i_read_16_normal(cpustate, A) +#define read_16_AXI(A) g65816i_read_16_normal(cpustate, A) +#define read_16_S(A) g65816i_read_16_normal(cpustate, A) +#define read_16_SIY(A) g65816i_read_16_normal(cpustate, A) + +#define read_24_NORM(A) g65816i_read_24_normal(cpustate, A) +#define read_24_IMM(A) g65816i_read_24_immediate(cpustate, A) +#define read_24_D(A) g65816i_read_24_direct(cpustate, A) +#define read_24_A(A) g65816i_read_24_normal(cpustate, A) +#define read_24_AL(A) g65816i_read_24_normal(cpustate, A) +#define read_24_DX(A) g65816i_read_24_direct(cpustate, A) +#define read_24_DY(A) g65816i_read_24_direct(cpustate, A) +#define read_24_AX(A) g65816i_read_24_normal(cpustate, A) +#define read_24_ALX(A) g65816i_read_24_normal(cpustate, A) +#define read_24_AY(A) g65816i_read_24_normal(cpustate, A) +#define read_24_DI(A) g65816i_read_24_normal(cpustate, A) +#define read_24_DLI(A) g65816i_read_24_normal(cpustate, A) +#define read_24_AI(A) g65816i_read_24_normal(cpustate, A) +#define read_24_ALI(A) g65816i_read_24_normal(cpustate, A) +#define read_24_DXI(A) g65816i_read_24_normal(cpustate, A) +#define read_24_DIY(A) g65816i_read_24_normal(cpustate, A) +#define read_24_DLIY(A) g65816i_read_24_normal(cpustate, A) +#define read_24_AXI(A) g65816i_read_24_normal(cpustate, A) +#define read_24_S(A) g65816i_read_24_normal(cpustate, A) +#define read_24_SIY(A) g65816i_read_24_normal(cpustate, A) + +#define write_8_NORM(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_D(A, V) g65816i_write_8_direct(cpustate, A, V) +#define write_8_A(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_AL(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_DX(A, V) g65816i_write_8_direct(cpustate, A, V) +#define write_8_DY(A, V) g65816i_write_8_direct(cpustate, A, V) +#define write_8_AX(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_ALX(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_AY(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_DI(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_DLI(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_AI(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_ALI(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_DXI(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_DIY(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_DLIY(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_AXI(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_S(A, V) g65816i_write_8_normal(cpustate, A, V) +#define write_8_SIY(A, V) g65816i_write_8_normal(cpustate, A, V) + +#define write_16_NORM(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_D(A, V) g65816i_write_16_direct(cpustate, A, V) +#define write_16_A(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_AL(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_DX(A, V) g65816i_write_16_direct(cpustate, A, V) +#define write_16_DY(A, V) g65816i_write_16_direct(cpustate, A, V) +#define write_16_AX(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_ALX(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_AY(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_DI(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_DLI(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_AI(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_ALI(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_DXI(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_DIY(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_DLIY(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_AXI(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_S(A, V) g65816i_write_16_normal(cpustate, A, V) +#define write_16_SIY(A, V) g65816i_write_16_normal(cpustate, A, V) + + +#define OPER_8_IMM(cpustate) read_8_IMM(EA_IMM8(cpustate)) +#define OPER_8_D(cpustate) read_8_D(EA_D(cpustate)) +#define OPER_8_A(cpustate) read_8_A(EA_A(cpustate)) +#define OPER_8_AL(cpustate) read_8_AL(EA_AL(cpustate)) +#define OPER_8_DX(cpustate) read_8_DX(EA_DX(cpustate)) +#define OPER_8_DY(cpustate) read_8_DY(EA_DY(cpustate)) +#define OPER_8_AX(cpustate) read_8_AX(EA_AX(cpustate)) +#define OPER_8_ALX(cpustate) read_8_ALX(EA_ALX(cpustate)) +#define OPER_8_AY(cpustate) read_8_AY(EA_AY(cpustate)) +#define OPER_8_DI(cpustate) read_8_DI(EA_DI(cpustate)) +#define OPER_8_DLI(cpustate) read_8_DLI(EA_DLI(cpustate)) +#define OPER_8_AI(cpustate) read_8_AI(EA_AI(cpustate)) +#define OPER_8_ALI(cpustate) read_8_ALI(EA_ALI(cpustate)) +#define OPER_8_DXI(cpustate) read_8_DXI(EA_DXI(cpustate)) +#define OPER_8_DIY(cpustate) read_8_DIY(EA_DIY(cpustate)) +#define OPER_8_DLIY(cpustate) read_8_DLIY(EA_DLIY(cpustate)) +#define OPER_8_AXI(cpustate) read_8_AXI(EA_AXI(cpustate)) +#define OPER_8_S(cpustate) read_8_S(EA_S(cpustate)) +#define OPER_8_SIY(cpustate) read_8_SIY(EA_SIY(cpustate)) + +#define OPER_16_IMM(cpustate) read_16_IMM(EA_IMM16(cpustate)) +#define OPER_16_D(cpustate) read_16_D(EA_D(cpustate)) +#define OPER_16_A(cpustate) read_16_A(EA_A(cpustate)) +#define OPER_16_AL(cpustate) read_16_AL(EA_AL(cpustate)) +#define OPER_16_DX(cpustate) read_16_DX(EA_DX(cpustate)) +#define OPER_16_DY(cpustate) read_16_DY(EA_DY(cpustate)) +#define OPER_16_AX(cpustate) read_16_AX(EA_AX(cpustate)) +#define OPER_16_ALX(cpustate) read_16_ALX(EA_ALX(cpustate)) +#define OPER_16_AY(cpustate) read_16_AY(EA_AY(cpustate)) +#define OPER_16_DI(cpustate) read_16_DI(EA_DI(cpustate)) +#define OPER_16_DLI(cpustate) read_16_DLI(EA_DLI(cpustate)) +#define OPER_16_AI(cpustate) read_16_AI(EA_AI(cpustate)) +#define OPER_16_ALI(cpustate) read_16_ALI(EA_ALI(cpustate)) +#define OPER_16_DXI(cpustate) read_16_DXI(EA_DXI(cpustate)) +#define OPER_16_DIY(cpustate) read_16_DIY(EA_DIY(cpustate)) +#define OPER_16_DLIY(cpustate) read_16_DLIY(EA_DLIY(cpustate)) +#define OPER_16_AXI(cpustate) read_16_AXI(EA_AXI(cpustate)) +#define OPER_16_S(cpustate) read_16_S(EA_S(cpustate)) +#define OPER_16_SIY(cpustate) read_16_SIY(EA_SIY(cpustate)) + +#define OPER_24_IMM(cpustate) read_24_IMM(EA_IMM24(cpustate)) +#define OPER_24_D(cpustate) read_24_D(EA_D(cpustate)) +#define OPER_24_A(cpustate) read_24_A(EA_A(cpustate)) +#define OPER_24_AL(cpustate) read_24_AL(EA_AL(cpustate)) +#define OPER_24_DX(cpustate) read_24_DX(EA_DX(cpustate)) +#define OPER_24_DY(cpustate) read_24_DY(EA_DY(cpustate)) +#define OPER_24_AX(cpustate) read_24_AX(EA_AX(cpustate)) +#define OPER_24_ALX(cpustate) read_24_ALX(EA_ALX(cpustate)) +#define OPER_24_AY(cpustate) read_24_AY(EA_AY(cpustate)) +#define OPER_24_DI(cpustate) read_24_DI(EA_DI(cpustate)) +#define OPER_24_DLI(cpustate) read_24_DLI(EA_DLI(cpustate)) +#define OPER_24_AI(cpustate) read_24_AI(EA_AI(cpustate)) +#define OPER_24_ALI(cpustate) read_24_ALI(EA_ALI(cpustate)) +#define OPER_24_DXI(cpustate) read_24_DXI(EA_DXI(cpustate)) +#define OPER_24_DIY(cpustate) read_24_DIY(EA_DIY(cpustate)) +#define OPER_24_DLIY(cpustate) read_24_DLIY(EA_DLIY(cpustate)) +#define OPER_24_AXI(cpustate) read_24_AXI(EA_AXI(cpustate)) +#define OPER_24_S(cpustate) read_24_S(EA_S(cpustate)) +#define OPER_24_SIY(cpustate) read_24_SIY(EA_SIY(cpustate)) INLINE uint EA_IMM8(g65816i_cpu_struct *cpustate) {REGISTER_PC += 1; return REGISTER_PB | MAKE_UINT_16(REGISTER_PC-1);} INLINE uint EA_IMM16(g65816i_cpu_struct *cpustate) {REGISTER_PC += 2; return REGISTER_PB | MAKE_UINT_16(REGISTER_PC-2);} @@ -656,215 +656,215 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ /* M6502 Add With Carry */ #undef OP_ADC #if FLAG_SET_M -#define OP_ADC(MODE) \ - { \ - unsigned tmp16; \ - CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - SRC = OPER_8_##MODE(cpustate); \ - if(FLAG_D) \ - { \ - INT32 result, r0, r1, carry; \ - r0 = REGISTER_A; \ - r1 = SRC; \ - carry = CFLAG_AS_1(); \ - result = (r0 & 0x0f) + (r1 & 0x0f) + (carry << 0); \ - if (result > 0x09) result += 0x06; \ - carry = result > 0x0f; \ - result = (r0 & 0xf0) + (r1 & 0xf0) + (carry << 4) + (result & 0x0f); \ - FLAG_V = ~(r0 ^ SRC) & (r0 ^ result) & 0x80; \ - if (result > 0x9f) result += 0x60; \ - FLAG_C = (result > 0xff) ? 0x100 : 0; \ - FLAG_N = (result & 0x80); \ - FLAG_Z = REGISTER_A = MAKE_UINT_8(result); \ - } \ - else \ - { \ - FLAG_C = tmp16 = REGISTER_A + SRC + CFLAG_AS_1(); \ - FLAG_V = VFLAG_ADD_8(SRC, REGISTER_A, FLAG_C); \ - FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(tmp16); \ - } \ +#define OP_ADC(MODE) \ + { \ + unsigned tmp16; \ + CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ + SRC = OPER_8_##MODE(cpustate); \ + if(FLAG_D) \ + { \ + INT32 result, r0, r1, carry; \ + r0 = REGISTER_A; \ + r1 = SRC; \ + carry = CFLAG_AS_1(); \ + result = (r0 & 0x0f) + (r1 & 0x0f) + (carry << 0); \ + if (result > 0x09) result += 0x06; \ + carry = result > 0x0f; \ + result = (r0 & 0xf0) + (r1 & 0xf0) + (carry << 4) + (result & 0x0f); \ + FLAG_V = ~(r0 ^ SRC) & (r0 ^ result) & 0x80; \ + if (result > 0x9f) result += 0x60; \ + FLAG_C = (result > 0xff) ? 0x100 : 0; \ + FLAG_N = (result & 0x80); \ + FLAG_Z = REGISTER_A = MAKE_UINT_8(result); \ + } \ + else \ + { \ + FLAG_C = tmp16 = REGISTER_A + SRC + CFLAG_AS_1(); \ + FLAG_V = VFLAG_ADD_8(SRC, REGISTER_A, FLAG_C); \ + FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(tmp16); \ + } \ } #else -#define OP_ADC(MODE) \ - CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - SRC = OPER_16_##MODE(cpustate); \ - INT32 result, r0, r1, carry; \ - r0 = REGISTER_A; \ - r1 = SRC; \ - carry = CFLAG_AS_1(); \ - if (!FLAG_D) \ - { \ - result = r0 + r1 + carry; \ - } \ - else \ - { \ - result = (r0 & 0x000f) + (r1 & 0x000f) + (carry << 0); \ - if(result > 0x0009) result += 0x0006; \ - carry = result > 0x000f; \ - result = (r0 & 0x00f0) + (r1 & 0x00f0) + (carry << 4) + (result & 0x000f); \ - if(result > 0x009f) result += 0x0060; \ - carry = result > 0x00ff; \ - result = (r0 & 0x0f00) + (r1 & 0x0f00) + (carry << 8) + (result & 0x00ff); \ - if(result > 0x09ff) result += 0x0600; \ - carry = result > 0x0fff; \ - result = (r0 & 0xf000) + (r1 & 0xf000) + (carry << 12) + (result & 0x0fff); \ - } \ - FLAG_V = ~(r0 ^ r1) & (r0 ^ result) & 0x8000; \ - FLAG_V >>= 8; \ - if (FLAG_D && result > 0x9fff) result += 0x6000; \ - FLAG_C = (result > 0xffff) ? 0x100 : 0; \ - FLAG_Z = REGISTER_A = MAKE_UINT_16(result); \ +#define OP_ADC(MODE) \ + CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ + SRC = OPER_16_##MODE(cpustate); \ + INT32 result, r0, r1, carry; \ + r0 = REGISTER_A; \ + r1 = SRC; \ + carry = CFLAG_AS_1(); \ + if (!FLAG_D) \ + { \ + result = r0 + r1 + carry; \ + } \ + else \ + { \ + result = (r0 & 0x000f) + (r1 & 0x000f) + (carry << 0); \ + if(result > 0x0009) result += 0x0006; \ + carry = result > 0x000f; \ + result = (r0 & 0x00f0) + (r1 & 0x00f0) + (carry << 4) + (result & 0x000f); \ + if(result > 0x009f) result += 0x0060; \ + carry = result > 0x00ff; \ + result = (r0 & 0x0f00) + (r1 & 0x0f00) + (carry << 8) + (result & 0x00ff); \ + if(result > 0x09ff) result += 0x0600; \ + carry = result > 0x0fff; \ + result = (r0 & 0xf000) + (r1 & 0xf000) + (carry << 12) + (result & 0x0fff); \ + } \ + FLAG_V = ~(r0 ^ r1) & (r0 ^ result) & 0x8000; \ + FLAG_V >>= 8; \ + if (FLAG_D && result > 0x9fff) result += 0x6000; \ + FLAG_C = (result > 0xffff) ? 0x100 : 0; \ + FLAG_Z = REGISTER_A = MAKE_UINT_16(result); \ FLAG_N = NFLAG_16(REGISTER_A); #endif /* M6502 Logical AND with accumulator */ #undef OP_AND #if FLAG_SET_M -#define OP_AND(MODE) \ - CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ +#define OP_AND(MODE) \ + CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ FLAG_N = FLAG_Z = REGISTER_A &= OPER_8_##MODE(cpustate) #else -#define OP_AND(MODE) \ - CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REGISTER_A &= OPER_16_##MODE(cpustate); \ +#define OP_AND(MODE) \ + CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ + FLAG_Z = REGISTER_A &= OPER_16_##MODE(cpustate); \ FLAG_N = NFLAG_16(REGISTER_A) #endif /* M6502 Arithmetic Shift Left accumulator */ #undef OP_ASL #if FLAG_SET_M -#define OP_ASL() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_C = REGISTER_A << 1; \ +#define OP_ASL() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_C = REGISTER_A << 1; \ FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(FLAG_C) #else -#define OP_ASL() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_C = REGISTER_A << 1; \ - FLAG_Z = REGISTER_A = MAKE_UINT_16(FLAG_C); \ - FLAG_N = NFLAG_16(FLAG_C); \ +#define OP_ASL() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_C = REGISTER_A << 1; \ + FLAG_Z = REGISTER_A = MAKE_UINT_16(FLAG_C); \ + FLAG_N = NFLAG_16(FLAG_C); \ FLAG_C = CFLAG_16(FLAG_C) #endif /* M6502 Arithmetic Shift Left operand */ #undef OP_ASLM #if FLAG_SET_M -#define OP_ASLM(MODE) \ - CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_C = read_8_##MODE(DST) << 1; \ - FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ +#define OP_ASLM(MODE) \ + CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_C = read_8_##MODE(DST) << 1; \ + FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ write_8_##MODE(DST, FLAG_Z) #else -#define OP_ASLM(MODE) \ - CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_C = read_16_##MODE(DST) << 1; \ - FLAG_Z = MAKE_UINT_16(FLAG_C); \ - FLAG_N = NFLAG_16(FLAG_C); \ - FLAG_C = CFLAG_16(FLAG_C); \ +#define OP_ASLM(MODE) \ + CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_C = read_16_##MODE(DST) << 1; \ + FLAG_Z = MAKE_UINT_16(FLAG_C); \ + FLAG_N = NFLAG_16(FLAG_C); \ + FLAG_C = CFLAG_16(FLAG_C); \ write_16_##MODE(DST, FLAG_Z) #endif /* M6502 Branch on Condition Code */ #undef OP_BCC -#define OP_BCC(COND) \ - DST = OPER_8_IMM(cpustate); \ - if(COND) \ - { \ - CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ - g65816i_branch_8(cpustate, DST); \ - BREAKOUT; \ - } \ - CLK(CLK_OP + CLK_RELATIVE_8); \ +#define OP_BCC(COND) \ + DST = OPER_8_IMM(cpustate); \ + if(COND) \ + { \ + CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ + g65816i_branch_8(cpustate, DST); \ + BREAKOUT; \ + } \ + CLK(CLK_OP + CLK_RELATIVE_8); \ /* M6502 Set flags according to bits */ #undef OP_BIT #if FLAG_SET_M -#define OP_BIT(MODE) \ - CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_N = OPER_8_##MODE(cpustate); \ - FLAG_Z = FLAG_N & REGISTER_A; \ +#define OP_BIT(MODE) \ + CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ + FLAG_N = OPER_8_##MODE(cpustate); \ + FLAG_Z = FLAG_N & REGISTER_A; \ FLAG_V = FLAG_N << 1 #else -#define OP_BIT(MODE) \ - CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_N = OPER_16_##MODE(cpustate); \ - FLAG_Z = FLAG_N & REGISTER_A; \ - FLAG_N = NFLAG_16(FLAG_N); \ +#define OP_BIT(MODE) \ + CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ + FLAG_N = OPER_16_##MODE(cpustate); \ + FLAG_Z = FLAG_N & REGISTER_A; \ + FLAG_N = NFLAG_16(FLAG_N); \ FLAG_V = FLAG_N << 1 #endif /* G65816 Set flags according to bits (immediate addressing mode) */ #undef OP_BITI #if FLAG_SET_M -#define OP_BITI() \ - CLK(CLK_OP + CLK_R8 + CLK_IMM); \ +#define OP_BITI() \ + CLK(CLK_OP + CLK_R8 + CLK_IMM); \ FLAG_Z = REGISTER_A & OPER_8_IMM(cpustate) #else -#define OP_BITI() \ - CLK(CLK_OP + CLK_R16 + CLK_IMM); \ +#define OP_BITI() \ + CLK(CLK_OP + CLK_R16 + CLK_IMM); \ FLAG_Z = REGISTER_A & OPER_16_IMM(cpustate) #endif /* M6502 Cause a Break interrupt */ #undef OP_BRK -#define OP_BRK() \ - REGISTER_PC++; \ +#define OP_BRK() \ + REGISTER_PC++; \ g65816i_interrupt_software(cpustate, VECTOR_BRK) /* G65816 Branch Always */ #undef OP_BRA -#define OP_BRA() \ - CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_8); \ +#define OP_BRA() \ + CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_8); \ g65816i_branch_8(cpustate, OPER_8_IMM(cpustate)) /* G65816 Branch Always Long */ #undef OP_BRL -#define OP_BRL() \ - CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_16); \ +#define OP_BRL() \ + CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_16); \ g65816i_branch_16(cpustate, OPER_16_IMM(cpustate)) /* M6502 Clear Carry flag */ #undef OP_CLC -#define OP_CLC() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_CLC() \ + CLK(CLK_OP + CLK_IMPLIED); \ FLAG_C = CFLAG_CLEAR /* M6502 Clear Decimal flag */ #undef OP_CLD -#define OP_CLD() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_CLD() \ + CLK(CLK_OP + CLK_IMPLIED); \ FLAG_D = DFLAG_CLEAR /* M6502 Clear Interrupt Mask flag */ #undef OP_CLI -#define OP_CLI() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_CLI() \ + CLK(CLK_OP + CLK_IMPLIED); \ g65816i_set_flag_i(cpustate, IFLAG_CLEAR) /* M6502 Clear oVerflow flag */ #undef OP_CLV -#define OP_CLV() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_CLV() \ + CLK(CLK_OP + CLK_IMPLIED); \ FLAG_V = VFLAG_CLEAR /* M6502 Compare operand to accumulator */ /* Unusual behavior: C flag is inverted */ #undef OP_CMP #if FLAG_SET_M -#define OP_CMP(MODE) \ - CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_C = REGISTER_A - OPER_8_##MODE(cpustate); \ - FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ +#define OP_CMP(MODE) \ + CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ + FLAG_C = REGISTER_A - OPER_8_##MODE(cpustate); \ + FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ FLAG_C ^= CFLAG_SET #else -#define OP_CMP(MODE) \ - CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_C = REGISTER_A - OPER_16_##MODE(cpustate); \ - FLAG_Z = MAKE_UINT_16(FLAG_C); \ - FLAG_N = NFLAG_16(FLAG_C); \ +#define OP_CMP(MODE) \ + CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ + FLAG_C = REGISTER_A - OPER_16_##MODE(cpustate); \ + FLAG_Z = MAKE_UINT_16(FLAG_C); \ + FLAG_N = NFLAG_16(FLAG_C); \ FLAG_C = ~CFLAG_16(FLAG_C) #endif @@ -872,238 +872,238 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ /* Unusual behavior: C flag is inverted */ #undef OP_CMPX #if FLAG_SET_X -#define OP_CMPX(REG, MODE) \ - CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - FLAG_C = REG - OPER_8_##MODE(cpustate); \ - FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ +#define OP_CMPX(REG, MODE) \ + CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ + FLAG_C = REG - OPER_8_##MODE(cpustate); \ + FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ FLAG_C ^= CFLAG_SET #else -#define OP_CMPX(REG, MODE) \ - CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_C = REG - OPER_16_##MODE(cpustate); \ - FLAG_Z = MAKE_UINT_16(FLAG_C); \ - FLAG_N = NFLAG_16(FLAG_C); \ +#define OP_CMPX(REG, MODE) \ + CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ + FLAG_C = REG - OPER_16_##MODE(cpustate); \ + FLAG_Z = MAKE_UINT_16(FLAG_C); \ + FLAG_N = NFLAG_16(FLAG_C); \ FLAG_C = ~CFLAG_16(FLAG_C) #endif /* G65816 Coprocessor operation */ #undef OP_COP -#define OP_COP() \ - REGISTER_PC++; \ +#define OP_COP() \ + REGISTER_PC++; \ g65816i_interrupt_software(cpustate, VECTOR_COP) /* M6502 Decrement accumulator */ #undef OP_DEC #if FLAG_SET_M -#define OP_DEC() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_DEC() \ + CLK(CLK_OP + CLK_IMPLIED); \ FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(REGISTER_A - 1) #else -#define OP_DEC() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_A = MAKE_UINT_16(REGISTER_A - 1); \ +#define OP_DEC() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_A = MAKE_UINT_16(REGISTER_A - 1); \ FLAG_N = NFLAG_16(REGISTER_A) #endif /* M6502 Decrement operand */ #undef OP_DECM #if FLAG_SET_M -#define OP_DECM(MODE) \ - CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) - 1); \ +#define OP_DECM(MODE) \ + CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) - 1); \ write_8_##MODE(DST, FLAG_Z) #else -#define OP_DECM(MODE) \ - CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) - 1); \ - FLAG_N = NFLAG_16(FLAG_Z); \ +#define OP_DECM(MODE) \ + CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) - 1); \ + FLAG_N = NFLAG_16(FLAG_Z); \ write_16_##MODE(DST, FLAG_Z) #endif /* M6502 Decrement index register */ #undef OP_DECX #if FLAG_SET_X -#define OP_DECX(REG) \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_DECX(REG) \ + CLK(CLK_OP + CLK_IMPLIED); \ FLAG_N = FLAG_Z = REG = MAKE_UINT_8(REG - 1) #else -#define OP_DECX(REG) \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REG = MAKE_UINT_16(REG - 1); \ +#define OP_DECX(REG) \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REG = MAKE_UINT_16(REG - 1); \ FLAG_N = NFLAG_16(REG) #endif /* M6502 Exclusive Or operand to accumulator */ #undef OP_EOR #if FLAG_SET_M -#define OP_EOR(MODE) \ - CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ +#define OP_EOR(MODE) \ + CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ FLAG_N = FLAG_Z = REGISTER_A ^= OPER_8_##MODE(cpustate) #else -#define OP_EOR(MODE) \ - CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REGISTER_A ^= OPER_16_##MODE(cpustate); \ +#define OP_EOR(MODE) \ + CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ + FLAG_Z = REGISTER_A ^= OPER_16_##MODE(cpustate); \ FLAG_N = NFLAG_16(REGISTER_A) #endif /* M6502 Increment accumulator */ #undef OP_INC #if FLAG_SET_M -#define OP_INC() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_INC() \ + CLK(CLK_OP + CLK_IMPLIED); \ FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(REGISTER_A + 1) #else -#define OP_INC() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_A = MAKE_UINT_16(REGISTER_A + 1); \ +#define OP_INC() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_A = MAKE_UINT_16(REGISTER_A + 1); \ FLAG_N = NFLAG_16(REGISTER_A) #endif /* M6502 Increment operand */ #undef OP_INCM #if FLAG_SET_M -#define OP_INCM(MODE) \ - CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) + 1); \ +#define OP_INCM(MODE) \ + CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) + 1); \ write_8_##MODE(DST, FLAG_Z) #else -#define OP_INCM(MODE) \ - CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) + 1); \ - FLAG_N = NFLAG_16(FLAG_Z); \ +#define OP_INCM(MODE) \ + CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) + 1); \ + FLAG_N = NFLAG_16(FLAG_Z); \ write_16_##MODE(DST, FLAG_Z) #endif /* M6502 Increment index register */ #undef OP_INCX #if FLAG_SET_X -#define OP_INCX(REG) \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_INCX(REG) \ + CLK(CLK_OP + CLK_IMPLIED); \ FLAG_N = FLAG_Z = REG = MAKE_UINT_8(REG + 1) #else -#define OP_INCX(REG) \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REG = MAKE_UINT_16(REG + 1); \ +#define OP_INCX(REG) \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REG = MAKE_UINT_16(REG + 1); \ FLAG_N = NFLAG_16(REG) #endif /* G65816 Jump Long */ #undef OP_JMLAI -#define OP_JMLAI() \ - CLK(CLK_OP + CLK_AI + 1); \ +#define OP_JMLAI() \ + CLK(CLK_OP + CLK_AI + 1); \ g65816i_jump_24(cpustate, read_24_A(OPER_16_IMM(cpustate))) /* M6502 Jump */ #undef OP_JMP -#define OP_JMP(MODE) \ - CLK(CLK_OP + CLK_##MODE); \ +#define OP_JMP(MODE) \ + CLK(CLK_OP + CLK_##MODE); \ g65816i_jump_16(cpustate, EA_##MODE(cpustate)) /* M6502 Jump absolute indexed indirect */ #undef OP_JMPAXI -#define OP_JMPAXI() \ - CLK(CLK_OP + CLK_AXI); \ +#define OP_JMPAXI() \ + CLK(CLK_OP + CLK_AXI); \ g65816i_jump_16(cpustate, read_16_AXI(REGISTER_PB | (MAKE_UINT_16(OPER_16_IMM(cpustate) + REGISTER_X)))) /* G65816 Jump absolute long */ #undef OP_JMPAL -#define OP_JMPAL() \ - CLK(CLK_OP + CLK_AL); \ +#define OP_JMPAL() \ + CLK(CLK_OP + CLK_AL); \ g65816i_jump_24(cpustate, EA_AL(cpustate)) /* G65816 Jump to Subroutine Long */ /* Unusual behavior: stacks PC-1 */ #undef OP_JSL -#define OP_JSL(MODE) \ - CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1); \ - DST = EA_##MODE(cpustate); \ - g65816i_push_8(cpustate, REGISTER_PB>>16); \ - g65816i_push_16(cpustate, REGISTER_PC-1); \ +#define OP_JSL(MODE) \ + CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1); \ + DST = EA_##MODE(cpustate); \ + g65816i_push_8(cpustate, REGISTER_PB>>16); \ + g65816i_push_16(cpustate, REGISTER_PC-1); \ g65816i_jump_24(cpustate, DST) /* M6502 Jump to Subroutine */ /* Unusual behavior: stacks PC-1 */ #undef OP_JSR -#define OP_JSR(MODE) \ - CLK(CLK_OP + CLK_W16 + CLK_##MODE); \ - DST = EA_##MODE(cpustate); \ - g65816i_push_16(cpustate, REGISTER_PC-1); \ +#define OP_JSR(MODE) \ + CLK(CLK_OP + CLK_W16 + CLK_##MODE); \ + DST = EA_##MODE(cpustate); \ + g65816i_push_16(cpustate, REGISTER_PC-1); \ g65816i_jump_16(cpustate, DST) /* M6502 Jump to Subroutine */ /* Unusual behavior: stacks PC-1 */ #undef OP_JSRAXI -#define OP_JSRAXI() \ - CLK(CLK_OP + CLK_W16 + CLK_AXI); \ +#define OP_JSRAXI() \ + CLK(CLK_OP + CLK_W16 + CLK_AXI); \ DST = read_16_AXI(REGISTER_PB | (MAKE_UINT_16(OPER_16_IMM(cpustate) + REGISTER_X))); \ - g65816i_push_16(cpustate, REGISTER_PC-1); \ + g65816i_push_16(cpustate, REGISTER_PC-1); \ g65816i_jump_16(cpustate, DST) /* M6502 Load accumulator with operand */ #undef OP_LDA #if FLAG_SET_M -#define OP_LDA(MODE) \ - CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ +#define OP_LDA(MODE) \ + CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ FLAG_N = FLAG_Z = REGISTER_A = OPER_8_##MODE(cpustate) #else -#define OP_LDA(MODE) \ - CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REGISTER_A = OPER_16_##MODE(cpustate); \ +#define OP_LDA(MODE) \ + CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ + FLAG_Z = REGISTER_A = OPER_16_##MODE(cpustate); \ FLAG_N = NFLAG_16(REGISTER_A) #endif /* M6502 Load index register with operand */ #undef OP_LDX #if FLAG_SET_X -#define OP_LDX(REG, MODE) \ - CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ +#define OP_LDX(REG, MODE) \ + CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ FLAG_N = FLAG_Z = REG = OPER_8_##MODE(cpustate) #else -#define OP_LDX(REG, MODE) \ - CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REG = OPER_16_##MODE(cpustate); \ +#define OP_LDX(REG, MODE) \ + CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ + FLAG_Z = REG = OPER_16_##MODE(cpustate); \ FLAG_N = NFLAG_16(REG) #endif /* M6502 Logical Shift Right accumulator */ #undef OP_LSR #if FLAG_SET_M -#define OP_LSR() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_N = 0; \ - FLAG_C = REGISTER_A << 8; \ +#define OP_LSR() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_N = 0; \ + FLAG_C = REGISTER_A << 8; \ FLAG_Z = REGISTER_A >>= 1 #else -#define OP_LSR() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_N = 0; \ - FLAG_C = REGISTER_A << 8; \ +#define OP_LSR() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_N = 0; \ + FLAG_C = REGISTER_A << 8; \ FLAG_Z = REGISTER_A >>= 1 #endif /* M6502 Logical Shift Right operand */ #undef OP_LSRM #if FLAG_SET_M -#define OP_LSRM(MODE) \ - CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_N = 0; \ - FLAG_Z = read_8_##MODE(DST); \ - FLAG_C = FLAG_Z << 8; \ - FLAG_Z >>= 1; \ +#define OP_LSRM(MODE) \ + CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_N = 0; \ + FLAG_Z = read_8_##MODE(DST); \ + FLAG_C = FLAG_Z << 8; \ + FLAG_Z >>= 1; \ write_8_##MODE(DST, FLAG_Z) #else -#define OP_LSRM(MODE) \ - CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_N = 0; \ - FLAG_Z = read_16_##MODE(DST); \ - FLAG_C = FLAG_Z << 8; \ - FLAG_Z >>= 1; \ +#define OP_LSRM(MODE) \ + CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_N = 0; \ + FLAG_Z = read_16_##MODE(DST); \ + FLAG_C = FLAG_Z << 8; \ + FLAG_Z >>= 1; \ write_16_##MODE(DST, FLAG_Z) #endif @@ -1111,15 +1111,15 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_MVN #if FLAG_SET_M #if FLAG_SET_X -#define OP_MVN() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ - REGISTER_DB = DST; \ - CLK(7); \ - write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ - REGISTER_X = MAKE_UINT_8(REGISTER_X+1); \ - REGISTER_Y = MAKE_UINT_8(REGISTER_Y+1); \ - REGISTER_A--; \ +#define OP_MVN() \ + DST = OPER_8_IMM(cpustate)<<16; \ + SRC = OPER_8_IMM(cpustate)<<16; \ + REGISTER_DB = DST; \ + CLK(7); \ + write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ + REGISTER_X = MAKE_UINT_8(REGISTER_X+1); \ + REGISTER_Y = MAKE_UINT_8(REGISTER_Y+1); \ + REGISTER_A--; \ REGISTER_A &= 0xff; \ if ((REGISTER_A&0xff) != 0xff) \ {\ @@ -1130,20 +1130,20 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ REGISTER_B -= 0x100;\ REGISTER_B &= 0xff00; \ if ((REGISTER_B & 0xff00) != 0xff00)\ - { \ + { \ REGISTER_PC -= 3;\ - } \ + } \ } #else -#define OP_MVN() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ - REGISTER_DB = DST; \ - CLK(7); \ - write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ - REGISTER_X = MAKE_UINT_16(REGISTER_X+1); \ - REGISTER_Y = MAKE_UINT_16(REGISTER_Y+1); \ - REGISTER_A--; \ +#define OP_MVN() \ + DST = OPER_8_IMM(cpustate)<<16; \ + SRC = OPER_8_IMM(cpustate)<<16; \ + REGISTER_DB = DST; \ + CLK(7); \ + write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ + REGISTER_X = MAKE_UINT_16(REGISTER_X+1); \ + REGISTER_Y = MAKE_UINT_16(REGISTER_Y+1); \ + REGISTER_A--; \ REGISTER_A &= 0xff; \ if ((REGISTER_A&0xff) != 0xff) \ {\ @@ -1154,38 +1154,38 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ REGISTER_B -= 0x100;\ REGISTER_B &= 0xff00; \ if ((REGISTER_B & 0xff00) != 0xff00)\ - { \ + { \ REGISTER_PC -= 3;\ - } \ + } \ } #endif #else #if FLAG_SET_X -#define OP_MVN() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ - REGISTER_DB = DST; \ - REGISTER_A |= REGISTER_B; \ - CLK(7); \ - write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ - REGISTER_X = MAKE_UINT_8(REGISTER_X+1); \ - REGISTER_Y = MAKE_UINT_8(REGISTER_Y+1); \ - REGISTER_A--; \ +#define OP_MVN() \ + DST = OPER_8_IMM(cpustate)<<16; \ + SRC = OPER_8_IMM(cpustate)<<16; \ + REGISTER_DB = DST; \ + REGISTER_A |= REGISTER_B; \ + CLK(7); \ + write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ + REGISTER_X = MAKE_UINT_8(REGISTER_X+1); \ + REGISTER_Y = MAKE_UINT_8(REGISTER_Y+1); \ + REGISTER_A--; \ if ((REGISTER_A&0xffff) != 0xffff) \ {\ REGISTER_PC -= 3; \ } #else -#define OP_MVN() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ - REGISTER_DB = DST; \ - REGISTER_A |= REGISTER_B; \ - CLK(7); \ - write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ - REGISTER_X = MAKE_UINT_16(REGISTER_X+1); \ - REGISTER_Y = MAKE_UINT_16(REGISTER_Y+1); \ - REGISTER_A--; \ +#define OP_MVN() \ + DST = OPER_8_IMM(cpustate)<<16; \ + SRC = OPER_8_IMM(cpustate)<<16; \ + REGISTER_DB = DST; \ + REGISTER_A |= REGISTER_B; \ + CLK(7); \ + write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ + REGISTER_X = MAKE_UINT_16(REGISTER_X+1); \ + REGISTER_Y = MAKE_UINT_16(REGISTER_Y+1); \ + REGISTER_A--; \ if ((REGISTER_A&0xffff) != 0xffff) \ {\ REGISTER_PC -= 3; \ @@ -1197,15 +1197,15 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #undef OP_MVP #if FLAG_SET_M #if FLAG_SET_X -#define OP_MVP() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ - REGISTER_DB = DST; \ - CLK(7); \ - write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ - REGISTER_X = MAKE_UINT_8(REGISTER_X-1); \ - REGISTER_Y = MAKE_UINT_8(REGISTER_Y-1); \ - REGISTER_A--; \ +#define OP_MVP() \ + DST = OPER_8_IMM(cpustate)<<16; \ + SRC = OPER_8_IMM(cpustate)<<16; \ + REGISTER_DB = DST; \ + CLK(7); \ + write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ + REGISTER_X = MAKE_UINT_8(REGISTER_X-1); \ + REGISTER_Y = MAKE_UINT_8(REGISTER_Y-1); \ + REGISTER_A--; \ REGISTER_A &= 0xff; \ if ((REGISTER_A&0xff) != 0xff) \ {\ @@ -1216,20 +1216,20 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ REGISTER_B -= 0x100;\ REGISTER_B &= 0xff00; \ if ((REGISTER_B & 0xff00) != 0xff00)\ - { \ + { \ REGISTER_PC -= 3;\ - } \ + } \ } #else -#define OP_MVP() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ - REGISTER_DB = DST; \ - CLK(7); \ - write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ - REGISTER_X = MAKE_UINT_16(REGISTER_X-1); \ - REGISTER_Y = MAKE_UINT_16(REGISTER_Y-1); \ - REGISTER_A--; \ +#define OP_MVP() \ + DST = OPER_8_IMM(cpustate)<<16; \ + SRC = OPER_8_IMM(cpustate)<<16; \ + REGISTER_DB = DST; \ + CLK(7); \ + write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ + REGISTER_X = MAKE_UINT_16(REGISTER_X-1); \ + REGISTER_Y = MAKE_UINT_16(REGISTER_Y-1); \ + REGISTER_A--; \ REGISTER_A &= 0xff; \ if ((REGISTER_A&0xff) != 0xff) \ {\ @@ -1240,38 +1240,38 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ REGISTER_B -= 0x100;\ REGISTER_B &= 0xff00; \ if ((REGISTER_B & 0xff00) != 0xff00)\ - { \ + { \ REGISTER_PC -= 3;\ - } \ + } \ } #endif #else #if FLAG_SET_X -#define OP_MVP() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ - REGISTER_DB = DST; \ - REGISTER_A |= REGISTER_B; \ - CLK(7); \ - write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ - REGISTER_X = MAKE_UINT_8(REGISTER_X-1); \ - REGISTER_Y = MAKE_UINT_8(REGISTER_Y-1); \ - REGISTER_A--; \ +#define OP_MVP() \ + DST = OPER_8_IMM(cpustate)<<16; \ + SRC = OPER_8_IMM(cpustate)<<16; \ + REGISTER_DB = DST; \ + REGISTER_A |= REGISTER_B; \ + CLK(7); \ + write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ + REGISTER_X = MAKE_UINT_8(REGISTER_X-1); \ + REGISTER_Y = MAKE_UINT_8(REGISTER_Y-1); \ + REGISTER_A--; \ if ((REGISTER_A&0xffff) != 0xffff) \ {\ REGISTER_PC -= 3; \ } #else -#define OP_MVP() \ - DST = OPER_8_IMM(cpustate)<<16; \ - SRC = OPER_8_IMM(cpustate)<<16; \ - REGISTER_DB = DST; \ - REGISTER_A |= REGISTER_B; \ - CLK(7); \ - write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ - REGISTER_X = MAKE_UINT_16(REGISTER_X-1); \ - REGISTER_Y = MAKE_UINT_16(REGISTER_Y-1); \ - REGISTER_A--; \ +#define OP_MVP() \ + DST = OPER_8_IMM(cpustate)<<16; \ + SRC = OPER_8_IMM(cpustate)<<16; \ + REGISTER_DB = DST; \ + REGISTER_A |= REGISTER_B; \ + CLK(7); \ + write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \ + REGISTER_X = MAKE_UINT_16(REGISTER_X-1); \ + REGISTER_Y = MAKE_UINT_16(REGISTER_Y-1); \ + REGISTER_A--; \ if ((REGISTER_A&0xffff) != 0xffff) \ {\ REGISTER_PC -= 3; \ @@ -1281,402 +1281,402 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ /* M6502 No Operation */ #undef OP_NOP -#define OP_NOP() \ +#define OP_NOP() \ CLK(CLK_OP + CLK_IMPLIED) /* M6502 Logical OR operand to accumulator */ #undef OP_ORA #if FLAG_SET_M -#define OP_ORA(MODE) \ - CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ +#define OP_ORA(MODE) \ + CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ FLAG_N = FLAG_Z = REGISTER_A |= OPER_8_ ## MODE(cpustate) #else -#define OP_ORA(MODE) \ - CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - FLAG_Z = REGISTER_A |= OPER_16_##MODE(cpustate); \ +#define OP_ORA(MODE) \ + CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ + FLAG_Z = REGISTER_A |= OPER_16_##MODE(cpustate); \ FLAG_N = NFLAG_16(REGISTER_A) #endif /* G65816 Push Effective Address */ #undef OP_PEA -#define OP_PEA() \ - CLK(CLK_OP + CLK_R16 + CLK_W16); \ +#define OP_PEA() \ + CLK(CLK_OP + CLK_R16 + CLK_W16); \ g65816i_push_16(cpustate, OPER_16_IMM(cpustate)) /* G65816 Push Effective Indirect Address */ #undef OP_PEI -#define OP_PEI() \ - CLK(CLK_OP + CLK_R16 + CLK_W16 + CLK_D); \ +#define OP_PEI() \ + CLK(CLK_OP + CLK_R16 + CLK_W16 + CLK_D); \ g65816i_push_16(cpustate, EA_DI(cpustate)) /* G65816 Push Effective PC-Relative Address */ #undef OP_PER -#define OP_PER() \ - CLK(CLK_OP + CLK_R16 + CLK_W16 + 1); \ - SRC = OPER_16_IMM(cpustate); \ +#define OP_PER() \ + CLK(CLK_OP + CLK_R16 + CLK_W16 + 1); \ + SRC = OPER_16_IMM(cpustate); \ g65816i_push_16(cpustate, REGISTER_PC + SRC) /* M6502 Push accumulator to the stack */ #undef OP_PHA #if FLAG_SET_M -#define OP_PHA() \ - CLK(CLK_OP + CLK_W8 + 1); \ +#define OP_PHA() \ + CLK(CLK_OP + CLK_W8 + 1); \ g65816i_push_8(cpustate, REGISTER_A) #else -#define OP_PHA() \ - CLK(CLK_OP + CLK_W16 + 1); \ +#define OP_PHA() \ + CLK(CLK_OP + CLK_W16 + 1); \ g65816i_push_16(cpustate, REGISTER_A) #endif /* M6502 Push index register to the stack */ #undef OP_PHX #if FLAG_SET_X -#define OP_PHX(REG) \ - CLK(CLK_OP + CLK_W8 + 1); \ +#define OP_PHX(REG) \ + CLK(CLK_OP + CLK_W8 + 1); \ g65816i_push_8(cpustate, REG) #else -#define OP_PHX(REG) \ - CLK(CLK_OP + CLK_W16 + 1); \ +#define OP_PHX(REG) \ + CLK(CLK_OP + CLK_W16 + 1); \ g65816i_push_16(cpustate, REG) #endif /* G65816 Push data bank register */ #undef OP_PHB -#define OP_PHB() \ - CLK(CLK_OP + CLK_W8 + 1); \ +#define OP_PHB() \ + CLK(CLK_OP + CLK_W8 + 1); \ g65816i_push_8(cpustate, REGISTER_DB>>16) /* G65816 Push direct register */ #undef OP_PHD -#define OP_PHD() \ - CLK(CLK_OP + CLK_W16 + 1); \ +#define OP_PHD() \ + CLK(CLK_OP + CLK_W16 + 1); \ g65816i_push_16(cpustate, REGISTER_D) /* G65816 Push program bank register */ #undef OP_PHK -#define OP_PHK() \ - CLK(CLK_OP + CLK_W8 + 1); \ +#define OP_PHK() \ + CLK(CLK_OP + CLK_W8 + 1); \ g65816i_push_8(cpustate, REGISTER_PB>>16) /* M6502 Push the Processor Status Register to the stack */ #undef OP_PHP -#define OP_PHP() \ - CLK(CLK_OP + CLK_W8 + 1); \ +#define OP_PHP() \ + CLK(CLK_OP + CLK_W8 + 1); \ g65816i_push_8(cpustate, g65816i_get_reg_p(cpustate)) /* M6502 Pull accumulator from the stack */ #undef OP_PLA #if FLAG_SET_M -#define OP_PLA() \ - CLK(CLK_OP + CLK_R8 + 2); \ +#define OP_PLA() \ + CLK(CLK_OP + CLK_R8 + 2); \ FLAG_N = FLAG_Z = REGISTER_A = g65816i_pull_8(cpustate) #else -#define OP_PLA() \ - CLK(CLK_OP + CLK_R16 + 2); \ - FLAG_Z = REGISTER_A = g65816i_pull_16(cpustate); \ +#define OP_PLA() \ + CLK(CLK_OP + CLK_R16 + 2); \ + FLAG_Z = REGISTER_A = g65816i_pull_16(cpustate); \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* M6502 Pull index register from the stack */ #undef OP_PLX #if FLAG_SET_X -#define OP_PLX(REG) \ - CLK(CLK_OP + CLK_R8 + 2); \ +#define OP_PLX(REG) \ + CLK(CLK_OP + CLK_R8 + 2); \ FLAG_N = FLAG_Z = REG = g65816i_pull_8(cpustate) #else -#define OP_PLX(REG) \ - CLK(CLK_OP + CLK_R16 + 2); \ - FLAG_Z = REG = g65816i_pull_16(cpustate); \ +#define OP_PLX(REG) \ + CLK(CLK_OP + CLK_R16 + 2); \ + FLAG_Z = REG = g65816i_pull_16(cpustate); \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* G65816 Pull data bank register */ #undef OP_PLB -#define OP_PLB() \ - CLK(CLK_OP + CLK_R8 + 2); \ - FLAG_N = FLAG_Z = g65816i_pull_8(cpustate); \ +#define OP_PLB() \ + CLK(CLK_OP + CLK_R8 + 2); \ + FLAG_N = FLAG_Z = g65816i_pull_8(cpustate); \ REGISTER_DB = FLAG_Z << 16 /* G65816 Pull direct register */ #undef OP_PLD -#define OP_PLD() \ - CLK(CLK_OP + CLK_R16 + 2); \ - FLAG_Z = REGISTER_D = g65816i_pull_16(cpustate); \ +#define OP_PLD() \ + CLK(CLK_OP + CLK_R16 + 2); \ + FLAG_Z = REGISTER_D = g65816i_pull_16(cpustate); \ FLAG_N = NFLAG_16(FLAG_Z) /* M6502 Pull the Processor Status Register from the stack */ #undef OP_PLP -#define OP_PLP() \ - CLK(CLK_OP + CLK_R8 + 2); \ +#define OP_PLP() \ + CLK(CLK_OP + CLK_R8 + 2); \ g65816i_set_reg_p(cpustate, g65816i_pull_8(cpustate)) /* G65816 Reset Program status word */ #undef OP_REP -#define OP_REP() \ - CLK(CLK_OP + CLK_R8 + 1); \ +#define OP_REP() \ + CLK(CLK_OP + CLK_R8 + 1); \ g65816i_set_reg_p(cpustate, g65816i_get_reg_p(cpustate) & ~OPER_8_IMM(cpustate)) /* M6502 Rotate Left the accumulator */ #undef OP_ROL #if FLAG_SET_M -#define OP_ROL() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_C = (REGISTER_A<<1) | CFLAG_AS_1(); \ +#define OP_ROL() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_C = (REGISTER_A<<1) | CFLAG_AS_1(); \ FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(FLAG_C) #else -#define OP_ROL() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_C = (REGISTER_A<<1) | CFLAG_AS_1(); \ - FLAG_Z = REGISTER_A = MAKE_UINT_16(FLAG_C); \ - FLAG_N = NFLAG_16(FLAG_C); \ +#define OP_ROL() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_C = (REGISTER_A<<1) | CFLAG_AS_1(); \ + FLAG_Z = REGISTER_A = MAKE_UINT_16(FLAG_C); \ + FLAG_N = NFLAG_16(FLAG_C); \ FLAG_C = CFLAG_16(FLAG_C) #endif /* M6502 Rotate Left an operand */ #undef OP_ROLM #if FLAG_SET_M -#define OP_ROLM(MODE) \ - CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_C = (read_8_##MODE(DST)<<1) | CFLAG_AS_1(); \ - FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ +#define OP_ROLM(MODE) \ + CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_C = (read_8_##MODE(DST)<<1) | CFLAG_AS_1(); \ + FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ write_8_##MODE(DST, FLAG_Z) #else -#define OP_ROLM(MODE) \ - CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_C = (read_16_##MODE(DST)<<1) | CFLAG_AS_1(); \ - FLAG_Z = MAKE_UINT_16(FLAG_C); \ - FLAG_N = NFLAG_16(FLAG_C); \ - FLAG_C = CFLAG_16(FLAG_C); \ +#define OP_ROLM(MODE) \ + CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_C = (read_16_##MODE(DST)<<1) | CFLAG_AS_1(); \ + FLAG_Z = MAKE_UINT_16(FLAG_C); \ + FLAG_N = NFLAG_16(FLAG_C); \ + FLAG_C = CFLAG_16(FLAG_C); \ write_16_##MODE(DST, FLAG_Z) #endif /* M6502 Rotate Right the accumulator */ #undef OP_ROR #if FLAG_SET_M -#define OP_ROR() \ - CLK(CLK_OP + CLK_IMPLIED); \ - REGISTER_A |= FLAG_C & 0x100; \ - FLAG_C = REGISTER_A << 8; \ +#define OP_ROR() \ + CLK(CLK_OP + CLK_IMPLIED); \ + REGISTER_A |= FLAG_C & 0x100; \ + FLAG_C = REGISTER_A << 8; \ FLAG_N = FLAG_Z = REGISTER_A >>= 1 #else -#define OP_ROR() \ - CLK(CLK_OP + CLK_IMPLIED); \ - REGISTER_A |= (FLAG_C<<8) & 0x10000; \ - FLAG_C = REGISTER_A << 8; \ - FLAG_Z = REGISTER_A >>= 1; \ +#define OP_ROR() \ + CLK(CLK_OP + CLK_IMPLIED); \ + REGISTER_A |= (FLAG_C<<8) & 0x10000; \ + FLAG_C = REGISTER_A << 8; \ + FLAG_Z = REGISTER_A >>= 1; \ FLAG_N = NFLAG_16(REGISTER_A) #endif /* M6502 Rotate Right an operand */ #undef OP_RORM #if FLAG_SET_M -#define OP_RORM(MODE) \ - CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_Z = read_8_##MODE(DST) | (FLAG_C & 0x100); \ - FLAG_C = FLAG_Z << 8; \ - FLAG_N = FLAG_Z >>= 1; \ +#define OP_RORM(MODE) \ + CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_Z = read_8_##MODE(DST) | (FLAG_C & 0x100); \ + FLAG_C = FLAG_Z << 8; \ + FLAG_N = FLAG_Z >>= 1; \ write_8_##MODE(DST, FLAG_Z) #else -#define OP_RORM(MODE) \ - CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_Z = read_16_##MODE(DST) | ((FLAG_C<<8) & 0x10000); \ - FLAG_C = FLAG_Z << 8; \ - FLAG_Z >>= 1; \ - FLAG_N = NFLAG_16(FLAG_Z); \ +#define OP_RORM(MODE) \ + CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_Z = read_16_##MODE(DST) | ((FLAG_C<<8) & 0x10000); \ + FLAG_C = FLAG_Z << 8; \ + FLAG_Z >>= 1; \ + FLAG_N = NFLAG_16(FLAG_Z); \ write_16_##MODE(DST, FLAG_Z) #endif /* M6502 Return from Interrupt */ #undef OP_RTI #if FLAG_SET_E -#define OP_RTI() \ - CLK(7); \ - g65816i_set_reg_p(cpustate, g65816i_pull_8(cpustate)); \ +#define OP_RTI() \ + CLK(7); \ + g65816i_set_reg_p(cpustate, g65816i_pull_8(cpustate)); \ g65816i_jump_16(cpustate, g65816i_pull_16(cpustate)) #else -#define OP_RTI() \ - CLK(8); \ - g65816i_set_reg_p(cpustate, g65816i_pull_8(cpustate)); \ - g65816i_jump_16(cpustate, g65816i_pull_16(cpustate)); \ +#define OP_RTI() \ + CLK(8); \ + g65816i_set_reg_p(cpustate, g65816i_pull_8(cpustate)); \ + g65816i_jump_16(cpustate, g65816i_pull_16(cpustate)); \ REGISTER_PB = g65816i_pull_8(cpustate) << 16 #endif /* G65816 Return from Subroutine Long */ /* Unusual behavior: Gets PC and increments */ #undef OP_RTL -#define OP_RTL() \ - CLK(6); \ +#define OP_RTL() \ + CLK(6); \ g65816i_jump_24(cpustate, g65816i_pull_24(cpustate)) /* M6502 Return from Subroutine */ /* Unusual behavior: Gets PC and increments */ #undef OP_RTS -#define OP_RTS() \ - CLK(6); \ +#define OP_RTS() \ + CLK(6); \ g65816i_jump_16(cpustate, g65816i_pull_16(cpustate)+1) /* M6502 Subtract with Carry */ /* Unusual behavior: C flag is inverted */ #undef OP_SBC #if FLAG_SET_M -#define OP_SBC(MODE) \ - CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ - SRC = OPER_8_##MODE(cpustate); \ - if(!FLAG_D) \ - { \ - FLAG_C = ~FLAG_C; \ - FLAG_C = REGISTER_A - SRC - CFLAG_AS_1(); \ - FLAG_V = VFLAG_SUB_8(SRC, REGISTER_A, FLAG_C); \ - FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(FLAG_C); \ - FLAG_C = ~FLAG_C; \ - BREAKOUT; \ - } \ - else \ - { \ - INT32 result, r0, r1, carry; \ - r0 = REGISTER_A; \ - r1 = SRC; \ - r1 ^= 0xff; \ - carry = CFLAG_AS_1(); \ - result = (r0 & 0x0f) + (r1 & 0x0f) + (carry << 0); \ - if (result <= 0x0f) result -= 0x06; \ - carry = result > 0x0f; \ - result = (r0 & 0xf0) + (r1 & 0xf0) + (carry << 4) + (result & 0x0f); \ - FLAG_V = ~(r0 ^ r1) & (r0 ^ result) & 0x80; \ - if (result <= 0xff) result -= 0x60; \ - FLAG_C = (result > 0xff) ? 0x100 : 0; \ - FLAG_N = (result & 0x80); \ - FLAG_Z = REGISTER_A = MAKE_UINT_8(result); \ +#define OP_SBC(MODE) \ + CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ + SRC = OPER_8_##MODE(cpustate); \ + if(!FLAG_D) \ + { \ + FLAG_C = ~FLAG_C; \ + FLAG_C = REGISTER_A - SRC - CFLAG_AS_1(); \ + FLAG_V = VFLAG_SUB_8(SRC, REGISTER_A, FLAG_C); \ + FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(FLAG_C); \ + FLAG_C = ~FLAG_C; \ + BREAKOUT; \ + } \ + else \ + { \ + INT32 result, r0, r1, carry; \ + r0 = REGISTER_A; \ + r1 = SRC; \ + r1 ^= 0xff; \ + carry = CFLAG_AS_1(); \ + result = (r0 & 0x0f) + (r1 & 0x0f) + (carry << 0); \ + if (result <= 0x0f) result -= 0x06; \ + carry = result > 0x0f; \ + result = (r0 & 0xf0) + (r1 & 0xf0) + (carry << 4) + (result & 0x0f); \ + FLAG_V = ~(r0 ^ r1) & (r0 ^ result) & 0x80; \ + if (result <= 0xff) result -= 0x60; \ + FLAG_C = (result > 0xff) ? 0x100 : 0; \ + FLAG_N = (result & 0x80); \ + FLAG_Z = REGISTER_A = MAKE_UINT_8(result); \ } #else -#define OP_SBC(MODE) \ - CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ - SRC = OPER_16_##MODE(cpustate); \ - INT32 result, r0, r1, carry; \ - r0 = REGISTER_A; \ - r1 = SRC; \ - r1 ^= 0xffff; \ - carry = CFLAG_AS_1(); \ - if (!FLAG_D) \ - { \ - result = r0 + r1 + carry; \ - } \ - else \ - { \ - result = (r0 & 0x000f) + (r1 & 0x000f) + (carry << 0); \ - if(result <= 0x000f) result -= 0x0006; \ - carry = result > 0x000f; \ - result = (r0 & 0x00f0) + (r1 & 0x00f0) + (carry << 4) + (result & 0x000f); \ - if(result <= 0x00ff) result -= 0x0060; \ - carry = result > 0x00ff; \ - result = (r0 & 0x0f00) + (r1 & 0x0f00) + (carry << 8) + (result & 0x00ff); \ - if(result <= 0x0fff) result -= 0x0600; \ - carry = result > 0x0fff; \ - result = (r0 & 0xf000) + (r1 & 0xf000) + (carry << 12) + (result & 0x0fff); \ - } \ - FLAG_V = ~(r0 ^ r1) & (r0 ^ result) & 0x8000; \ - FLAG_V >>= 8; \ - if (FLAG_D && result <= 0xffff) result -= 0x6000; \ - FLAG_C = (result > 0xffff) ? 0x100 : 0; \ - FLAG_Z = REGISTER_A = MAKE_UINT_16(result); \ +#define OP_SBC(MODE) \ + CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ + SRC = OPER_16_##MODE(cpustate); \ + INT32 result, r0, r1, carry; \ + r0 = REGISTER_A; \ + r1 = SRC; \ + r1 ^= 0xffff; \ + carry = CFLAG_AS_1(); \ + if (!FLAG_D) \ + { \ + result = r0 + r1 + carry; \ + } \ + else \ + { \ + result = (r0 & 0x000f) + (r1 & 0x000f) + (carry << 0); \ + if(result <= 0x000f) result -= 0x0006; \ + carry = result > 0x000f; \ + result = (r0 & 0x00f0) + (r1 & 0x00f0) + (carry << 4) + (result & 0x000f); \ + if(result <= 0x00ff) result -= 0x0060; \ + carry = result > 0x00ff; \ + result = (r0 & 0x0f00) + (r1 & 0x0f00) + (carry << 8) + (result & 0x00ff); \ + if(result <= 0x0fff) result -= 0x0600; \ + carry = result > 0x0fff; \ + result = (r0 & 0xf000) + (r1 & 0xf000) + (carry << 12) + (result & 0x0fff); \ + } \ + FLAG_V = ~(r0 ^ r1) & (r0 ^ result) & 0x8000; \ + FLAG_V >>= 8; \ + if (FLAG_D && result <= 0xffff) result -= 0x6000; \ + FLAG_C = (result > 0xffff) ? 0x100 : 0; \ + FLAG_Z = REGISTER_A = MAKE_UINT_16(result); \ FLAG_N = NFLAG_16(REGISTER_A); #endif /* M6502 Set Carry flag */ #undef OP_SEC -#define OP_SEC() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_SEC() \ + CLK(CLK_OP + CLK_IMPLIED); \ FLAG_C = CFLAG_SET /* M6502 Set Decimal flag */ #undef OP_SED -#define OP_SED() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_SED() \ + CLK(CLK_OP + CLK_IMPLIED); \ FLAG_D = DFLAG_SET /* M6502 Set Interrupt Mask flag */ #undef OP_SEI -#define OP_SEI() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_SEI() \ + CLK(CLK_OP + CLK_IMPLIED); \ g65816i_set_flag_i(cpustate, IFLAG_SET) /* G65816 Set Program status word */ #undef OP_SEP -#define OP_SEP() \ - CLK(CLK_OP + CLK_R8 + 1); \ +#define OP_SEP() \ + CLK(CLK_OP + CLK_R8 + 1); \ g65816i_set_reg_p(cpustate, g65816i_get_reg_p(cpustate) | OPER_8_IMM(cpustate)) /* M6502 Store accumulator to memory */ #undef OP_STA #if FLAG_SET_M -#define OP_STA(MODE) \ - CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ +#define OP_STA(MODE) \ + CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ write_8_##MODE(EA_##MODE(cpustate), REGISTER_A) #else -#define OP_STA(MODE) \ - CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ +#define OP_STA(MODE) \ + CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ write_16_##MODE(EA_##MODE(cpustate), REGISTER_A) #endif /* M6502 Store index register to memory */ #undef OP_STX #if FLAG_SET_X -#define OP_STX(REG, MODE) \ - CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ +#define OP_STX(REG, MODE) \ + CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ write_8_##MODE(EA_##MODE(cpustate), REG) #else -#define OP_STX(REG, MODE) \ - CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ +#define OP_STX(REG, MODE) \ + CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ write_16_##MODE(EA_##MODE(cpustate), REG) #endif /* M6502 Store zero to memory */ #undef OP_STZ #if FLAG_SET_M -#define OP_STZ(MODE) \ - CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ +#define OP_STZ(MODE) \ + CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ write_8_##MODE(EA_##MODE(cpustate), 0) #else -#define OP_STZ(MODE) \ - CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ +#define OP_STZ(MODE) \ + CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ write_16_##MODE(EA_##MODE(cpustate), 0) #endif /* G65816 Stop the clock */ #undef OP_STP -#define OP_STP() \ - USE_ALL_CLKS(); \ +#define OP_STP() \ + USE_ALL_CLKS(); \ CPU_STOPPED |= STOP_LEVEL_STOP /* M6502 Transfer accumulator to index */ #undef OP_TAX #if FLAG_SET_M #if FLAG_SET_X -#define OP_TAX(REG) \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REG = REGISTER_A; \ +#define OP_TAX(REG) \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REG = REGISTER_A; \ FLAG_N = NFLAG_8(FLAG_Z) #else /* FLAG_SET_X */ -#define OP_TAX(REG) \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REG = REGISTER_B | REGISTER_A; \ +#define OP_TAX(REG) \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REG = REGISTER_B | REGISTER_A; \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* FLAG_SET_X */ #else /* FLAG_SET_M */ #if FLAG_SET_X -#define OP_TAX(REG) \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REG = MAKE_UINT_8(REGISTER_A); \ +#define OP_TAX(REG) \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REG = MAKE_UINT_8(REGISTER_A); \ FLAG_N = NFLAG_8(FLAG_Z) #else /* FLAG_SET_X */ -#define OP_TAX(REG) \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REG = REGISTER_A; \ +#define OP_TAX(REG) \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REG = REGISTER_A; \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* FLAG_SET_X */ #endif /* FLAG_SET_M */ @@ -1685,200 +1685,200 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ /* M6502 Transfer index to accumulator */ #undef OP_TXA #if FLAG_SET_M -#define OP_TXA(REG) \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_A = MAKE_UINT_8(REG); \ +#define OP_TXA(REG) \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_A = MAKE_UINT_8(REG); \ FLAG_N = NFLAG_8(FLAG_Z) #else -#define OP_TXA(REG) \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_A = REG; \ +#define OP_TXA(REG) \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_A = REG; \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* G65816 Transfer C to direct register */ #undef OP_TCD #if FLAG_SET_M -#define OP_TCD() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_D = REGISTER_A | REGISTER_B; \ +#define OP_TCD() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_D = REGISTER_A | REGISTER_B; \ FLAG_N = NFLAG_16(FLAG_Z) #else -#define OP_TCD() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_D = REGISTER_A; \ +#define OP_TCD() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_D = REGISTER_A; \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* G65816 Transfer direct register to C */ #undef OP_TDC #if FLAG_SET_M -#define OP_TDC() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_D; \ - FLAG_N = NFLAG_16(FLAG_Z); \ - REGISTER_A = MAKE_UINT_8(REGISTER_D); \ +#define OP_TDC() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_D; \ + FLAG_N = NFLAG_16(FLAG_Z); \ + REGISTER_A = MAKE_UINT_8(REGISTER_D); \ REGISTER_B = REGISTER_D & 0xff00 #else -#define OP_TDC() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_A = REGISTER_D; \ +#define OP_TDC() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_A = REGISTER_D; \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* G65816 Transfer C to stack pointer */ #undef OP_TCS #if FLAG_SET_E -#define OP_TCS() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_TCS() \ + CLK(CLK_OP + CLK_IMPLIED); \ REGISTER_S = MAKE_UINT_8(REGISTER_A) | 0x100 #else -#define OP_TCS() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_TCS() \ + CLK(CLK_OP + CLK_IMPLIED); \ REGISTER_S = REGISTER_A | REGISTER_B #endif /* G65816 Transfer stack pointer to C */ #undef OP_TSC #if FLAG_SET_M -#define OP_TSC() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_S; \ - FLAG_N = NFLAG_16(FLAG_Z); \ - REGISTER_A = MAKE_UINT_8(REGISTER_S); \ +#define OP_TSC() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_S; \ + FLAG_N = NFLAG_16(FLAG_Z); \ + REGISTER_A = MAKE_UINT_8(REGISTER_S); \ REGISTER_B = REGISTER_S & 0xff00 #else -#define OP_TSC() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_A = REGISTER_S; \ +#define OP_TSC() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_A = REGISTER_S; \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* M6502 Transfer stack pointer to X */ #undef OP_TSX #if FLAG_SET_X -#define OP_TSX() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_X = MAKE_UINT_8(REGISTER_S); \ +#define OP_TSX() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_X = MAKE_UINT_8(REGISTER_S); \ FLAG_N = NFLAG_8(FLAG_Z) #else -#define OP_TSX() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_X = REGISTER_S; \ +#define OP_TSX() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_X = REGISTER_S; \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* M6502 Transfer X to stack pointer */ #undef OP_TXS #if FLAG_SET_E -#define OP_TXS() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_TXS() \ + CLK(CLK_OP + CLK_IMPLIED); \ REGISTER_S = MAKE_UINT_8(REGISTER_X) | 0x100 #else -#define OP_TXS() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_TXS() \ + CLK(CLK_OP + CLK_IMPLIED); \ REGISTER_S = REGISTER_X #endif /* G65816 Transfer X to Y */ #undef OP_TXY #if FLAG_SET_X -#define OP_TXY() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_Y = REGISTER_X; \ +#define OP_TXY() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_Y = REGISTER_X; \ FLAG_N = NFLAG_8(FLAG_Z) #else -#define OP_TXY() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_Y = REGISTER_X; \ +#define OP_TXY() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_Y = REGISTER_X; \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* G65816 Transfer Y to X */ #undef OP_TYX #if FLAG_SET_X -#define OP_TYX() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_X = REGISTER_Y; \ +#define OP_TYX() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_X = REGISTER_Y; \ FLAG_N = NFLAG_8(FLAG_Z) #else -#define OP_TYX() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_X = REGISTER_Y; \ +#define OP_TYX() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_X = REGISTER_Y; \ FLAG_N = NFLAG_16(FLAG_Z) #endif /* G65816 Test and reset bit */ #undef OP_TRB #if FLAG_SET_M -#define OP_TRB(MODE) \ - CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_Z = read_8_##MODE(DST); \ - write_8_##MODE(DST, FLAG_Z & ~REGISTER_A); \ +#define OP_TRB(MODE) \ + CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_Z = read_8_##MODE(DST); \ + write_8_##MODE(DST, FLAG_Z & ~REGISTER_A); \ FLAG_Z &= REGISTER_A #else -#define OP_TRB(MODE) \ - CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_Z = read_16_##MODE(DST); \ - write_16_##MODE(DST, FLAG_Z & ~REGISTER_A); \ +#define OP_TRB(MODE) \ + CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_Z = read_16_##MODE(DST); \ + write_16_##MODE(DST, FLAG_Z & ~REGISTER_A); \ FLAG_Z &= REGISTER_A #endif /* G65816 Test and set bit */ #undef OP_TSB #if FLAG_SET_M -#define OP_TSB(MODE) \ - CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_Z = read_8_##MODE(DST); \ - write_8_##MODE(DST, FLAG_Z | REGISTER_A); \ +#define OP_TSB(MODE) \ + CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_Z = read_8_##MODE(DST); \ + write_8_##MODE(DST, FLAG_Z | REGISTER_A); \ FLAG_Z &= REGISTER_A #else -#define OP_TSB(MODE) \ - CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ - DST = EA_##MODE(cpustate); \ - FLAG_Z = read_16_##MODE(DST); \ - write_16_##MODE(DST, FLAG_Z | REGISTER_A); \ +#define OP_TSB(MODE) \ + CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ + DST = EA_##MODE(cpustate); \ + FLAG_Z = read_16_##MODE(DST); \ + write_16_##MODE(DST, FLAG_Z | REGISTER_A); \ FLAG_Z &= REGISTER_A #endif /* G65816 Wait for interrupt */ #undef OP_WAI -#define OP_WAI() \ - USE_ALL_CLKS(); \ +#define OP_WAI() \ + USE_ALL_CLKS(); \ CPU_STOPPED |= STOP_LEVEL_WAI /* G65816 William D. Mensch, JR. (65816 designer) - future expansion */ #undef OP_WDM -#define OP_WDM() \ - CLK(CLK_OP + CLK_IMPLIED); \ +#define OP_WDM() \ + CLK(CLK_OP + CLK_IMPLIED); \ REGISTER_PC++ /* G65816 Exchange accum high and low bytes */ #undef OP_XBA #if FLAG_SET_M -#define OP_XBA() \ - CLK(CLK_OP + CLK_IMPLIED); \ - FLAG_Z = REGISTER_B>>8; \ - REGISTER_B = REGISTER_A<<8; \ - REGISTER_A = FLAG_Z; \ +#define OP_XBA() \ + CLK(CLK_OP + CLK_IMPLIED); \ + FLAG_Z = REGISTER_B>>8; \ + REGISTER_B = REGISTER_A<<8; \ + REGISTER_A = FLAG_Z; \ FLAG_N = NFLAG_8(FLAG_Z) #else -#define OP_XBA() \ - CLK(CLK_OP + CLK_IMPLIED + 1); \ - FLAG_Z = REGISTER_A >> 8; \ - REGISTER_A = MAKE_UINT_16(REGISTER_A<<8) | FLAG_Z; \ +#define OP_XBA() \ + CLK(CLK_OP + CLK_IMPLIED + 1); \ + FLAG_Z = REGISTER_A >> 8; \ + REGISTER_A = MAKE_UINT_16(REGISTER_A<<8) | FLAG_Z; \ FLAG_N = NFLAG_8(FLAG_Z) #endif /* G65816 Exchange carry and emulation bits */ #undef OP_XCE -#define OP_XCE() \ - CLK(CLK_OP + CLK_IMPLIED); \ - SRC = CFLAG_AS_1(); \ - FLAG_C = FLAG_E<<8; \ +#define OP_XCE() \ + CLK(CLK_OP + CLK_IMPLIED); \ + SRC = CFLAG_AS_1(); \ + FLAG_C = FLAG_E<<8; \ g65816i_set_flag_e(cpustate, SRC) @@ -1897,7 +1897,7 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #define OP(CODE, OPERATION) static void g65816i_ ## CODE ## _E(g65816i_cpu_struct *cpustate) {OPERATION;} #define O(CODE) g65816i_ ## CODE ## _E #define TABLE_OPCODES void (*const g65816i_opcodes_E[256])(g65816i_cpu_struct *cpustate) -#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816i_ ## NAME ## _E ARGS +#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816i_ ## NAME ## _E ARGS #else @@ -1905,28 +1905,28 @@ INLINE uint EA_SIY(g65816i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_ #define OP(CODE, OPERATION) static void g65816i_ ## CODE ## _M0X0(g65816i_cpu_struct *cpustate) {OPERATION;} #define O(CODE) g65816i_ ## CODE ## _M0X0 #define TABLE_OPCODES void (*const g65816i_opcodes_M0X0[256])(g65816i_cpu_struct *cpustate) -#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816i_ ## NAME ## _M0X0 ARGS +#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816i_ ## NAME ## _M0X0 ARGS #elif !FLAG_SET_M && FLAG_SET_X #define OP(CODE, OPERATION) static void g65816i_ ## CODE ## _M0X1(g65816i_cpu_struct *cpustate) {OPERATION;} #define O(CODE) g65816i_ ## CODE ## _M0X1 #define TABLE_OPCODES void (*const g65816i_opcodes_M0X1[256])(g65816i_cpu_struct *cpustate) -#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816i_ ## NAME ## _M0X1 ARGS +#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816i_ ## NAME ## _M0X1 ARGS #elif FLAG_SET_M && !FLAG_SET_X #define OP(CODE, OPERATION) static void g65816i_ ## CODE ## _M1X0(g65816i_cpu_struct *cpustate) {OPERATION;} #define O(CODE) g65816i_ ## CODE ## _M1X0 #define TABLE_OPCODES void (*const g65816i_opcodes_M1X0[256])(g65816i_cpu_struct *cpustate) -#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816i_ ## NAME ## _M1X0 ARGS +#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816i_ ## NAME ## _M1X0 ARGS #elif FLAG_SET_M && FLAG_SET_X #define OP(CODE, OPERATION) static void g65816i_ ## CODE ## _M1X1(g65816i_cpu_struct *cpustate) {OPERATION;} #define O(CODE) g65816i_ ## CODE ## _M1X1 #define TABLE_OPCODES void (*const g65816i_opcodes_M1X1[256])(g65816i_cpu_struct *cpustate) -#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816i_ ## NAME ## _M1X1 ARGS +#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816i_ ## NAME ## _M1X1 ARGS #endif #endif @@ -2374,9 +2374,9 @@ TABLE_FUNCTION(int, execute, (g65816i_cpu_struct *cpustate, int clocks)) do { /* Note that I'm doing a per-instruction interrupt - * check until this core is working well enough - * to start trying fancy stuff. - */ + * check until this core is working well enough + * to start trying fancy stuff. + */ g65816i_check_maskable_interrupt(cpustate); REGISTER_PPC = REGISTER_PC; |