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author Olivier Galibert <galibert@pobox.com>2020-05-25 16:42:42 +0200
committer Olivier Galibert <galibert@pobox.com>2020-05-25 16:42:57 +0200
commit22513fb6fe281f5ccb75aaddb6417a12a66c313d (patch)
tree3cf84032cc6482d685a8dbb57e015bd17c7f7fdc /src/devices/machine/s_smp.h
parente42c2d2874cf9c1092c01ab5ce9ef997d465ce25 (diff)
emumem: A little more speedup. cache and specific change syntax, and are not pointers anymore [O. Galibert]
The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
Diffstat (limited to 'src/devices/machine/s_smp.h')
-rw-r--r--src/devices/machine/s_smp.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/devices/machine/s_smp.h b/src/devices/machine/s_smp.h
index 5fe04b1880a..9fd0232329c 100644
--- a/src/devices/machine/s_smp.h
+++ b/src/devices/machine/s_smp.h
@@ -39,17 +39,17 @@ protected:
address_space_config m_data_config;
private:
- address_space *m_data;
- memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_dcache;
+ memory_access<16, 0, 0, ENDIANNESS_LITTLE>::cache m_dcache;
+ memory_access<16, 0, 0, ENDIANNESS_LITTLE>::specific m_data;
inline u8 data_read_byte(offs_t a)
{
/* IPL ROM enabled */
if (a >= 0xffc0 && m_ctrl & 0x80)
return m_ipl_region[a & 0x3f];
- return m_dcache->read_byte(a);
+ return m_dcache.read_byte(a);
}
- inline void data_write_byte(offs_t a, u8 d) { m_data->write_byte(a, d); }
+ inline void data_write_byte(offs_t a, u8 d) { m_data.write_byte(a, d); }
required_region_ptr<u8> m_ipl_region; /* SPC top 64 bytes */