summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/machine/68340sim.cpp
diff options
context:
space:
mode:
author smf- <smf-@users.noreply.github.com>2017-12-14 14:41:18 +0000
committer smf- <smf-@users.noreply.github.com>2017-12-14 14:42:21 +0000
commitb0b96416eb8685ce9948aa80882e960938c95bca (patch)
tree0fb63b5b5a46d85eeea57df2e04cd5f05ad622ed /src/devices/machine/68340sim.cpp
parent8b9246599a837d4f40cc47ceb73ecbdcc87cd2bb (diff)
remove safe_pc() (nw)
Diffstat (limited to 'src/devices/machine/68340sim.cpp')
-rw-r--r--src/devices/machine/68340sim.cpp88
1 files changed, 39 insertions, 49 deletions
diff --git a/src/devices/machine/68340sim.cpp b/src/devices/machine/68340sim.cpp
index 62497ad61b7..601830f7515 100644
--- a/src/devices/machine/68340sim.cpp
+++ b/src/devices/machine/68340sim.cpp
@@ -48,48 +48,47 @@ READ16_MEMBER( m68340_cpu_device::m68340_internal_sim_r )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int val = 0;
- int pc = space.device().safe_pc();
switch (offset * 2)
{
case m68340_sim::REG_MCR:
- LOGSIM("- %08x %s %04x, (%04x) (MCR - Module Configuration Register) - not implemented\n", pc, FUNCNAME, offset * 2, mem_mask);
+ LOGSIM("- %08x %s %04x, (%04x) (MCR - Module Configuration Register) - not implemented\n", m_ppc, FUNCNAME, offset * 2, mem_mask);
val = sim.m_mcr;
break;
case m68340_sim::REG_SYNCR:
- LOGSIM("- %08x %s %04x, (%04x) (SYNCR - Clock Synthesizer Register) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
+ LOGSIM("- %08x %s %04x, (%04x) (SYNCR - Clock Synthesizer Register) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_syncr;
break;
case m68340_sim::REG_AVR_RSR:
- LOGSIM("- %08x %s %04x, (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
+ LOGSIM("- %08x %s %04x, (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_avr_rsr;
break;
case m68340_sim::REG_SWIV_SYPCR:
- LOGSIM("- %08x %s %04x, (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
+ LOGSIM("- %08x %s %04x, (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_swiv_sypcr;
break;
case m68340_sim::REG_PICR:
- LOGPIT("- %08x %s %04x, (%04x) (PICR - Periodic Interrupt Control Register) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
+ LOGPIT("- %08x %s %04x, (%04x) (PICR - Periodic Interrupt Control Register) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_picr;
break;
case m68340_sim::REG_PITR:
- LOGPIT("- %08x %s %04x, (%04x) (PITR - Periodic Interrupt Timer Register) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
+ LOGPIT("- %08x %s %04x, (%04x) (PITR - Periodic Interrupt Timer Register) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_pitr;
break;
case m68340_sim::REG_SWSR:
- LOGSIM("- %08x %s %04x, (%04x) (SWSR - Software Service) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
+ LOGSIM("- %08x %s %04x, (%04x) (SWSR - Software Service) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_swsr;
break;
default:
- logerror("- %08x %s %04x, (%04x) (unsupported register)\n", pc, FUNCNAME, offset * 2, mem_mask);
- LOGSIM("- %08x %s %04x, (%04x) (unsupported register)\n", pc, FUNCNAME, offset * 2, mem_mask);
+ logerror("- %08x %s %04x, (%04x) (unsupported register)\n", m_ppc, FUNCNAME, offset * 2, mem_mask);
+ LOGSIM("- %08x %s %04x, (%04x) (unsupported register)\n", m_ppc, FUNCNAME, offset * 2, mem_mask);
}
LOGR(" * Reg %02x -> %02x - %s\n", offset * 2, val,
@@ -109,13 +108,11 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
- int pc = space.device().safe_pc();
-
switch (offset<<1)
{
case m68340_sim::REG_MCR:
COMBINE_DATA(&sim.m_mcr);
- LOGSIM("PC: %08x %s %04x, %04x (%04x) (MCR - Module Configuration Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
+ LOGSIM("PC: %08x %s %04x, %04x (%04x) (MCR - Module Configuration Register)\n", m_ppc, FUNCNAME, offset * 2, data, mem_mask);
LOGPIT("- FRZ1: Watchdog and PIT timer are %s\n", (data & m68340_sim::REG_MCR_FRZ1) == 0 ? "enabled" : "disabled");
LOGSIM("- FRZ0: The BUS monitor is %s\n", (data & m68340_sim::REG_MCR_FRZ0) == 0 ? "enabled" : "disabled");
LOGSIM("- FIRQ: Full Interrupt Request Mode %s\n", data & m68340_sim::REG_MCR_FIRQ ? "used on port B" : "supressed, adding 4 chip select lines on Port B");
@@ -125,7 +122,7 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
break;
case m68340_sim::REG_SYNCR:
- LOGSIM("PC: %08x %s %04x, %04x (%04x) (SYNCR - Clock Synthesizer Register) - not implemented\n", pc, FUNCNAME, offset * 2, data, mem_mask);
+ LOGSIM("PC: %08x %s %04x, %04x (%04x) (SYNCR - Clock Synthesizer Register) - not implemented\n", m_ppc, FUNCNAME, offset * 2, data, mem_mask);
COMBINE_DATA(&sim.m_syncr);
LOGSIM("- W : VCO x %d\n", data & m68340_sim::REG_SYNCR_W ? 4 : 1);
LOGSIM("- X : System clock / %d\n", data & m68340_sim::REG_SYNCR_X ? 1 : 2);
@@ -147,14 +144,14 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
break;
case m68340_sim::REG_AVR_RSR:
- LOGSIM("PC: %08x %s %04x, %04x (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
+ LOGSIM("PC: %08x %s %04x, %04x (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register)\n", m_ppc, FUNCNAME, offset * 2, data, mem_mask);
COMBINE_DATA(&sim.m_avr_rsr);
LOGSIM("- AVR: AV7-AV1 autovector bits: %02x\n", ((data & m68340_sim::REG_AVR_VEC) >> 8) & 0xff);
LOGSIM("- RSR: Last reset type: %02x - not implemented\n", (data & m68340_sim::REG_RSR_RESBITS) & 0xff);
break;
case m68340_sim::REG_SWIV_SYPCR:
- LOGSIM("PC: %08x %s %04x, %04x (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register) - not implemented\n", pc, FUNCNAME, offset * 2, data, mem_mask);
+ LOGSIM("PC: %08x %s %04x, %04x (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register) - not implemented\n", m_ppc, FUNCNAME, offset * 2, data, mem_mask);
COMBINE_DATA(&sim.m_swiv_sypcr);
LOGSIM("- SWIV: Software watchdog Interrupt Vector: %02x\n", ((data & m68340_sim::REG_SWIV_VEC) >> 8) & 0xff);
LOGSIM("- SWE : Software watchdog %s\n", (data & m68340_sim::REG_SYPCR_SWE) ? "enabled" : "disabled");
@@ -164,14 +161,14 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
break;
case m68340_sim::REG_PICR:
- LOGPIT("PC: %08x %s %04x, %04x (%04x) (PICR - Periodic Interrupt Control Register)\n", pc, FUNCNAME, offset*2,data,mem_mask);
+ LOGPIT("PC: %08x %s %04x, %04x (%04x) (PICR - Periodic Interrupt Control Register)\n", m_ppc, FUNCNAME, offset*2,data,mem_mask);
COMBINE_DATA(&sim.m_picr);
LOGPIT("- PIRQL: Periodic Interrupt Level %d%s\n", (data & m68340_sim::REG_PICR_PIRQL) >> 8, (data & m68340_sim::REG_PICR_PIRQL) == 0 ? " (disabled)" : "");
LOGPIT("- PIV : Periodic Interrupt Vector %02x\n", (data & m68340_sim::REG_PICR_PIVEC));
break;
case m68340_sim::REG_PITR:
- LOGPIT("PC: %08x %s %04x, %04x (%04x) (PITR - Periodic Interrupt Timer Register)\n", pc, FUNCNAME, offset*2,data,mem_mask);
+ LOGPIT("PC: %08x %s %04x, %04x (%04x) (PITR - Periodic Interrupt Timer Register)\n", m_ppc, FUNCNAME, offset*2,data,mem_mask);
COMBINE_DATA(&sim.m_pitr);
LOGSIM("- SWP : Software watchdog prescale factor is %d\n", (data & m68340_sim::REG_PITR_SWP) ? 512 : 1);
LOGPIT("- PTP : Periodic timer prescale factor is %d\n", (data & m68340_sim::REG_PITR_PTP) ? 512 : 1);
@@ -187,11 +184,11 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
case m68340_sim::REG_SWSR:
// basically watchdog, you must write an alternating pattern of 0x55 / 0xaa to keep the watchdog from resetting the system
- //LOGSIM("- %08x %s %04x, %04x (%04x) (SWSR - Software Service)\n", pc, FUNCNAME, offset*2,data,mem_mask);
+ //LOGSIM("- %08x %s %04x, %04x (%04x) (SWSR - Software Service)\n", m_ppc, FUNCNAME, offset*2,data,mem_mask);
break;
default:
- LOGSIM("- %08x %s %04x, %04x (%04x) - not implemented\n", pc, FUNCNAME, offset*2,data,mem_mask);
+ LOGSIM("- %08x %s %04x, %04x (%04x) - not implemented\n", m_ppc, FUNCNAME, offset*2,data,mem_mask);
}
}
@@ -203,13 +200,12 @@ READ8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_r )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
- int pc = space.device().safe_pc();
int val = space.machine().rand();
switch (offset)
{
case m68340_sim::REG_PORTA:
- LOGR("- %08x %s %04x (PORTA - Port A Data)\n", pc, FUNCNAME, offset);
+ LOGR("- %08x %s %04x (PORTA - Port A Data)\n", m_ppc, FUNCNAME, offset);
sim.m_porta &= sim.m_ddra;
// TODO: call callback
@@ -227,25 +223,25 @@ READ8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_r )
break;
case m68340_sim::REG_DDRA:
- LOGR("- %08x %s %04x (DDRA - Port A Data Direction)\n", pc, FUNCNAME, offset);
+ LOGR("- %08x %s %04x (DDRA - Port A Data Direction)\n", m_ppc, FUNCNAME, offset);
val = sim.m_ddra;
break;
case m68340_sim::REG_PPARA1:
- LOGR("- %08x %s %04x (PPRA1 - Port A Pin Assignment 1)\n", pc, FUNCNAME, offset);
+ LOGR("- %08x %s %04x (PPRA1 - Port A Pin Assignment 1)\n", m_ppc, FUNCNAME, offset);
val = sim.m_ppara1;
break;
case m68340_sim::REG_PPARA2:
- LOGR("- %08x %s %04x (PPRA2 - Port A Pin Assignment 2) - not implemented\n", pc, FUNCNAME, offset);
+ LOGR("- %08x %s %04x (PPRA2 - Port A Pin Assignment 2) - not implemented\n", m_ppc, FUNCNAME, offset);
val = sim.m_ppara2;
break;
case m68340_sim::REG_PORTB1:
- LOGR("- %08x %s %04x (PORTB1 - Port B Data 1)\n", pc, FUNCNAME, offset);
+ LOGR("- %08x %s %04x (PORTB1 - Port B Data 1)\n", m_ppc, FUNCNAME, offset);
// Fallthrough to mirror register
case m68340_sim::REG_PORTB:
- LOGR("- %08x %s %04x (PORTB - Port B Data 0)\n", pc, FUNCNAME, offset);
+ LOGR("- %08x %s %04x (PORTB - Port B Data 0)\n", m_ppc, FUNCNAME, offset);
sim.m_portb &= sim.m_ddrb;
// TODO: call callback
@@ -263,18 +259,18 @@ READ8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_r )
break;
case m68340_sim::REG_DDRB:
- LOGR("- %08x %s %04x (DDR - Port B Data Direction)\n", pc, FUNCNAME, offset);
+ LOGR("- %08x %s %04x (DDR - Port B Data Direction)\n", m_ppc, FUNCNAME, offset);
val = sim.m_ddrb;
break;
case m68340_sim::REG_PPARB:
- LOGR("- %08x %s %04x (PPARB - Port B Pin Assignment)\n", pc, FUNCNAME, offset);
+ LOGR("- %08x %s %04x (PPARB - Port B Pin Assignment)\n", m_ppc, FUNCNAME, offset);
val = sim.m_pparb;
break;
default:
- LOGR("- %08x %s %04x (ILLEGAL?)\n", pc, FUNCNAME, offset);
- logerror("%08x m68340_internal_sim_r %04x (ILLEGAL?)\n", pc, FUNCNAME, offset);
+ LOGR("- %08x %s %04x (ILLEGAL?)\n", m_ppc, FUNCNAME, offset);
+ logerror("%08x m68340_internal_sim_r %04x (ILLEGAL?)\n", m_ppc, FUNCNAME, offset);
break;
}
LOGR(" * Reg %02x -> %02x - %s\n", offset, val, std::array<char const *, 16>
@@ -290,14 +286,12 @@ WRITE8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_w )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
- int pc = space.device().safe_pc();
-
LOGSETUP(" * Reg %02x <- %02x - %s\n", offset, data, std::array<char const *, 8>
{{"PORTA", "DDRA", "PPRA1", "PPRA2", "PORTB", "PORTB1", "DDRB", "PPARB"}}[(offset - 0x10) / 2]);
switch (offset)
{
case m68340_sim::REG_PORTA:
- LOGDATA("- %08x %04x, %02x (PORTA - Port A Data)\n", pc, offset,data);
+ LOGDATA("- %08x %04x, %02x (PORTA - Port A Data)\n", m_ppc, offset,data);
sim.m_porta = (data & sim.m_ddra & sim.m_ppara1);
// callback
@@ -305,25 +299,25 @@ WRITE8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_w )
break;
case m68340_sim::REG_DDRA:
- LOGPORTS("- %08x %04x, %02x (DDRA - Port A Data Direction)\n", pc, offset,data);
+ LOGPORTS("- %08x %04x, %02x (DDRA - Port A Data Direction)\n", m_ppc, offset,data);
sim.m_ddra = data;
break;
case m68340_sim::REG_PPARA1:
- LOGPORTS("- %08x %04x, %02x (PPARA1 - Port A Pin Assignment 1)\n", pc, offset,data);
+ LOGPORTS("- %08x %04x, %02x (PPARA1 - Port A Pin Assignment 1)\n", m_ppc, offset,data);
sim.m_ppara1 = data;
break;
case m68340_sim::REG_PPARA2:
- LOGPORTS("- %08x %04x, %02x (PPARA2 - Port A Pin Assignment 2)\n", pc, offset,data);
+ LOGPORTS("- %08x %04x, %02x (PPARA2 - Port A Pin Assignment 2)\n", m_ppc, offset,data);
sim.m_ppara2 = data;
break;
case m68340_sim::REG_PORTB1:
- LOGDATA("- %08x %04x, %02x (PORTB1 - Port B Data - mirror)\n", pc, offset,data);
+ LOGDATA("- %08x %04x, %02x (PORTB1 - Port B Data - mirror)\n", m_ppc, offset,data);
// Falling through to mirrored register portb
case m68340_sim::REG_PORTB:
- LOGDATA("- %08x %04x, %02x (PORTB - Port B Data)\n", pc, offset,data);
+ LOGDATA("- %08x %04x, %02x (PORTB - Port B Data)\n", m_ppc, offset,data);
sim.m_portb = (data & sim.m_ddrb & sim.m_pparb);
// callback
@@ -331,18 +325,18 @@ WRITE8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_w )
break;
case m68340_sim::REG_DDRB:
- LOGPORTS("- %08x %04x, %02x (DDR - Port B Data Direction)\n", pc, offset,data);
+ LOGPORTS("- %08x %04x, %02x (DDR - Port B Data Direction)\n", m_ppc, offset,data);
sim.m_ddrb = data;
break;
case m68340_sim::REG_PPARB:
- LOGPORTS("- %08x %04x, %02x (PPARB - Port B Pin Assignment)\n", pc, offset,data);
+ LOGPORTS("- %08x %04x, %02x (PPARB - Port B Pin Assignment)\n", m_ppc, offset,data);
sim.m_pparb = data;
break;
default:
- LOGPORTS("- %08x %s %04x, %02x (ILLEGAL?) - not implemented\n", pc, FUNCNAME, offset,data);
- logerror("%08x m68340_internal_sim_ports_w %04x, %02x (ILLEGAL?)\n", pc, offset,data);
+ LOGPORTS("- %08x %s %04x, %02x (ILLEGAL?) - not implemented\n", m_ppc, FUNCNAME, offset,data);
+ logerror("%08x m68340_internal_sim_ports_w %04x, %02x (ILLEGAL?)\n", m_ppc, offset,data);
break;
}
}
@@ -355,8 +349,6 @@ READ32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_r )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
- int pc = space.device().safe_pc();
-
switch (offset<<2)
{
case m68340_sim::REG_AM_CS0: return sim.m_am[0];
@@ -369,7 +361,7 @@ READ32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_r )
case m68340_sim::REG_BA_CS3: return sim.m_ba[3];
default:
- logerror("%08x m68340_internal_sim_r %08x, (%08x)\n", pc, offset*4,mem_mask);
+ logerror("%08x m68340_internal_sim_r %08x, (%08x)\n", m_ppc, offset*4,mem_mask);
}
return 0x00000000;
@@ -394,8 +386,6 @@ WRITE32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_w )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
- int pc = space.device().safe_pc();
-
switch (offset << 2)
{
case m68340_sim::REG_AM_CS0:
@@ -431,7 +421,7 @@ WRITE32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_w )
break;
default:
- logerror("%08x m68340_internal_sim_cs_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
+ logerror("%08x m68340_internal_sim_cs_w %08x, %08x (%08x)\n", m_ppc, offset*4,data,mem_mask);
break;
}
}