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| author | 2019-09-10 17:19:56 -0400 | |
|---|---|---|
| committer | 2019-09-10 17:19:56 -0400 | |
| commit | ec4e6bdf0fc42c64eea2ec3fe1e63bb3db9bbe53 (patch) | |
| tree | 859bce96d198ba37fbdf19efce0ade5acbaf13c4 /src/devices/cpu/rii/riidasm.cpp | |
| parent | 29575e47048c0864726392b0c0fc796823293a9d (diff) | |
Add preliminary RISC II execution core
Diffstat (limited to 'src/devices/cpu/rii/riidasm.cpp')
| -rw-r--r-- | src/devices/cpu/rii/riidasm.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/devices/cpu/rii/riidasm.cpp b/src/devices/cpu/rii/riidasm.cpp index ab27b3fa291..cad53e121c9 100644 --- a/src/devices/cpu/rii/riidasm.cpp +++ b/src/devices/cpu/rii/riidasm.cpp @@ -321,6 +321,7 @@ offs_t riscii_disassembler::disassemble(std::ostream &stream, offs_t pc, const r case 0x2700: util::stream_format(stream, "%-8s", "RPT"); format_register(stream, opcode & 0x00ff); + words |= STEP_OVER | step_over_extra(1); break; case 0x2b00: |
