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author AJR <ajrhacker@users.noreply.github.com>2019-09-25 11:48:22 -0400
committer AJR <ajrhacker@users.noreply.github.com>2019-09-25 11:57:56 -0400
commita24caaede8da2f17d6f8d28d6ea2292b07f044bf (patch)
tree2c0b0031e015893b22615be1581eab0d97dc0432 /src/devices/cpu/rii/riidasm.cpp
parenta73d55f52edf0abcba904cd1939beb3dfc81ac02 (diff)
rii: Many updates
- Identify CPU type used by vreadere as ePG3231 - Add preliminary port I/O handlers and callbacks - Add stub handlers and state variables for interrupt controller, timers, synthesizer, UART and SPI - Fix TBRD addressing of external data memory - Fix calculation of carry flag for normal additive operations - Implement multi-byte carry/borrow for applicable registers - Implement signed multiplication option - Add internal stack buffer for saving PCH during calls/interrupts
Diffstat (limited to 'src/devices/cpu/rii/riidasm.cpp')
-rw-r--r--src/devices/cpu/rii/riidasm.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/devices/cpu/rii/riidasm.cpp b/src/devices/cpu/rii/riidasm.cpp
index cad53e121c9..aa8087c6fcc 100644
--- a/src/devices/cpu/rii/riidasm.cpp
+++ b/src/devices/cpu/rii/riidasm.cpp
@@ -16,8 +16,8 @@ using osd::u32;
using util::BIT;
using offs_t = u32;
-// FIXME: this set is an amalgam of ePG3231-EM202, EPD3332 and EPD3338
-const char *const riscii_disassembler::s_regs[0x60] =
+// TODO: add register sets for other models
+const char *const epg3231_disassembler::s_regs[0x60] =
{
"INDF0", "FSR0", "PCL", "PCM", "PCH", "BSR", "STKPTR", "BSR1",
"INDF1", "FSR1", "ACC", "TABPTRL", "TABPTRM", "TABPTRH", "CPUCON", "STATUS",
@@ -27,8 +27,8 @@ const char *const riscii_disassembler::s_regs[0x60] =
"TR2CON", "TRLIR", nullptr, "POST_ID", "ADCON", "PAINTEN", "PAINTSTA", "PAWAKE",
"UARTCON", "UARTSTA", "PORTJ", "PORTK", "DCRB", "DCRC", "DCRDE", "DCRFG",
"DCRHI", "DCRJK", "PBCON", "PCCON", "PLLF", "T0CL", "T0CH", "SPICON",
- "SPISTA", "SPRL", "SPRM", "SPRH", "SFCR", "ADDL1~ADDL4", "ADDM1~ADDM4", "ADDH1~ADDH4",
- "ENV1~4/SPHDR", "MTCON1~4/SPHTCON", "MTRL1~4/SPHTRL", "VOCON", "TR1C", "TR2C", "ADCF", nullptr,
+ "SPISTA", "SPRL", "SPRM", "SPRH", "SFCR", "ADDL", "ADDM", "ADDH",
+ "ENV/SPHDR", "MTCON/SPHTCON", "MTRL/SPHTRL", "VOCON", "TR1C", "TR2C", "ADCF", nullptr,
nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr,
nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr
};