summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/mcs51/mcs51.cpp
diff options
context:
space:
mode:
author Olivier Galibert <galibert@pobox.com>2020-05-25 16:42:42 +0200
committer Olivier Galibert <galibert@pobox.com>2020-05-25 16:42:57 +0200
commit22513fb6fe281f5ccb75aaddb6417a12a66c313d (patch)
tree3cf84032cc6482d685a8dbb57e015bd17c7f7fdc /src/devices/cpu/mcs51/mcs51.cpp
parente42c2d2874cf9c1092c01ab5ce9ef997d465ce25 (diff)
emumem: A little more speedup. cache and specific change syntax, and are not pointers anymore [O. Galibert]
The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
Diffstat (limited to 'src/devices/cpu/mcs51/mcs51.cpp')
-rw-r--r--src/devices/cpu/mcs51/mcs51.cpp43
1 files changed, 21 insertions, 22 deletions
diff --git a/src/devices/cpu/mcs51/mcs51.cpp b/src/devices/cpu/mcs51/mcs51.cpp
index a76e2bb5ea4..66eb3f50316 100644
--- a/src/devices/cpu/mcs51/mcs51.cpp
+++ b/src/devices/cpu/mcs51/mcs51.cpp
@@ -418,15 +418,15 @@ device_memory_interface::space_config_vector mcs51_cpu_device::memory_space_conf
***************************************************************************/
/* Read Opcode/Opcode Arguments from Program Code */
-#define ROP(pc) m_cache->read_byte(pc)
-#define ROP_ARG(pc) m_cache->read_byte(pc)
+#define ROP(pc) m_program.read_byte(pc)
+#define ROP_ARG(pc) m_program.read_byte(pc)
/* Read a byte from External Code Memory (Usually Program Rom(s) Space) */
-#define CODEMEM_R(a) (uint8_t)m_program->read_byte(a)
+#define CODEMEM_R(a) (uint8_t)m_program.read_byte(a)
/* Read/Write a byte from/to External Data Memory (Usually RAM or other I/O) */
-#define DATAMEM_R(a) (uint8_t)m_io->read_byte(a)
-#define DATAMEM_W(a,v) m_io->write_byte(a, v)
+#define DATAMEM_R(a) (uint8_t)m_io.read_byte(a)
+#define DATAMEM_W(a,v) m_io.write_byte(a, v)
/* Read/Write a byte from/to the Internal RAM */
@@ -435,8 +435,8 @@ device_memory_interface::space_config_vector mcs51_cpu_device::memory_space_conf
/* Read/Write a byte from/to the Internal RAM indirectly */
/* (called from indirect addressing) */
-uint8_t mcs51_cpu_device::iram_iread(offs_t a) { return (a <= m_ram_mask) ? m_data->read_byte(a) : 0xff; }
-void mcs51_cpu_device::iram_iwrite(offs_t a, uint8_t d) { if (a <= m_ram_mask) m_data->write_byte(a, d); }
+uint8_t mcs51_cpu_device::iram_iread(offs_t a) { return (a <= m_ram_mask) ? m_data.read_byte(a) : 0xff; }
+void mcs51_cpu_device::iram_iwrite(offs_t a, uint8_t d) { if (a <= m_ram_mask) m_data.write_byte(a, d); }
#define IRAM_IR(a) iram_iread(a)
#define IRAM_IW(a, d) iram_iwrite(a, d)
@@ -829,13 +829,13 @@ offs_t mcs51_cpu_device::external_ram_iaddr(offs_t offset, offs_t mem_mask)
uint8_t mcs51_cpu_device::iram_read(size_t offset)
{
- return (((offset) < 0x80) ? m_data->read_byte(offset) : sfr_read(offset));
+ return (((offset) < 0x80) ? m_data.read_byte(offset) : sfr_read(offset));
}
void mcs51_cpu_device::iram_write(size_t offset, uint8_t data)
{
if ((offset) < 0x80)
- m_data->write_byte(offset, data);
+ m_data.write_byte(offset, data);
else
sfr_write(offset, data);
}
@@ -2012,7 +2012,7 @@ void mcs51_cpu_device::execute_run()
/* Read next opcode */
PPC = PC;
debugger_instruction_hook(PC);
- op = m_cache->read_byte(PC++);
+ op = m_program.read_byte(PC++);
/* process opcode and count cycles */
m_inst_cycles = mcs51_cycles[op];
@@ -2079,7 +2079,7 @@ void mcs51_cpu_device::sfr_write(size_t offset, uint8_t data)
/* no write in this case according to manual */
return;
}
- m_data->write_byte((size_t)offset | 0x100, data);
+ m_data.write_byte((size_t)offset | 0x100, data);
}
uint8_t mcs51_cpu_device::sfr_read(size_t offset)
@@ -2114,7 +2114,7 @@ uint8_t mcs51_cpu_device::sfr_read(size_t offset)
case ADDR_SBUF:
case ADDR_IE:
case ADDR_IP:
- return m_data->read_byte((size_t) offset | 0x100);
+ return m_data.read_byte((size_t) offset | 0x100);
/* Illegal or non-implemented sfr */
default:
LOG(("mcs51 '%s': attemping to read an invalid/non-implemented SFR address: %x at 0x%04x\n", tag(), (uint32_t)offset,PC));
@@ -2126,10 +2126,9 @@ uint8_t mcs51_cpu_device::sfr_read(size_t offset)
void mcs51_cpu_device::device_start()
{
- m_program = &space(AS_PROGRAM);
- m_cache = m_program->cache<0, 0, ENDIANNESS_LITTLE>();
- m_data = &space(AS_DATA);
- m_io = &space(AS_IO);
+ space(AS_PROGRAM).cache(m_program);
+ space(AS_DATA).specific(m_data);
+ space(AS_IO).specific(m_io);
m_port_in_cb.resolve_all_safe(0xff);
m_port_out_cb.resolve_all_safe();
@@ -2321,7 +2320,7 @@ void i8052_device::sfr_write(size_t offset, uint8_t data)
case ADDR_RCAP2H:
case ADDR_TL2:
case ADDR_TH2:
- m_data->write_byte((size_t) offset | 0x100, data);
+ m_data.write_byte((size_t) offset | 0x100, data);
break;
default:
@@ -2339,7 +2338,7 @@ uint8_t i8052_device::sfr_read(size_t offset)
case ADDR_RCAP2H:
case ADDR_TL2:
case ADDR_TH2:
- return m_data->read_byte((size_t) offset | 0x100);
+ return m_data.read_byte((size_t) offset | 0x100);
default:
return mcs51_cpu_device::sfr_read(offset);
}
@@ -2369,7 +2368,7 @@ void i80c52_device::sfr_write(size_t offset, uint8_t data)
i8052_device::sfr_write(offset, data);
return;
}
- m_data->write_byte((size_t) offset | 0x100, data);
+ m_data.write_byte((size_t) offset | 0x100, data);
}
uint8_t i80c52_device::sfr_read(size_t offset)
@@ -2380,7 +2379,7 @@ uint8_t i80c52_device::sfr_read(size_t offset)
case ADDR_IPH:
case ADDR_SADDR:
case ADDR_SADEN:
- return m_data->read_byte((size_t) offset | 0x100);
+ return m_data.read_byte((size_t) offset | 0x100);
default:
return i8052_device::sfr_read(offset);
}
@@ -2434,7 +2433,7 @@ void ds5002fp_device::sfr_write(size_t offset, uint8_t data)
mcs51_cpu_device::sfr_write(offset, data);
return;
}
- m_data->write_byte((size_t) offset | 0x100, data);
+ m_data.write_byte((size_t) offset | 0x100, data);
}
uint8_t ds5002fp_device::sfr_read(size_t offset)
@@ -2455,7 +2454,7 @@ uint8_t ds5002fp_device::sfr_read(size_t offset)
default:
return mcs51_cpu_device::sfr_read(offset);
}
- return m_data->read_byte((size_t) offset | 0x100);
+ return m_data.read_byte((size_t) offset | 0x100);
}
/*