diff options
author | 2022-03-27 14:23:03 -0400 | |
---|---|---|
committer | 2022-03-27 14:29:51 -0400 | |
commit | c7597225b4f0a3531d53dd806048b136956eb850 (patch) | |
tree | 3ed5b758cbd0a94a43d9c6fe9f83f402b169657d /src/devices/cpu/m32c/m32cdasm.cpp | |
parent | c3162e739d625d31ca207ab8b591ea87c5f1fe03 (diff) |
Debugger feature improvements
- Add 'gbt' and 'gbf' debugger commands to step until a true or false conditional branch has been detected.
- Update over 100 of the disassemblers in MAME to output a new STEP_COND flag for all conditional branches. Besides being used for execution of the new 'gbt' and 'gbf' commands, this flag also now helps the debugger 'out' command to properly handle conditional return instructions.
- Remove STEP_OVER from many instructions that aren't actually subroutine calls (e.g. DJNZ on Z80). A 'gni' debugger command (go next instruction) has been added to accommodate some of the misuse.
- Add instruction flag support to several more disassemblers that lacked them entirely (e.g. st62xx)
- Don't pass over delay slots for debugging in ASAP core
Diffstat (limited to 'src/devices/cpu/m32c/m32cdasm.cpp')
-rw-r--r-- | src/devices/cpu/m32c/m32cdasm.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/devices/cpu/m32c/m32cdasm.cpp b/src/devices/cpu/m32c/m32cdasm.cpp index 9c687a37f47..a198971e965 100644 --- a/src/devices/cpu/m32c/m32cdasm.cpp +++ b/src/devices/cpu/m32c/m32cdasm.cpp @@ -856,7 +856,7 @@ void m32c_disassembler::dasm_1101(std::ostream &stream, offs_t &pc, const m32c_d stream << "und"; } -void m32c_disassembler::dasm_111x(std::ostream &stream, offs_t &pc, const m32c_disassembler::data_buffer &opcodes, u8 op1, bool indirect_dest) const +void m32c_disassembler::dasm_111x(std::ostream &stream, offs_t &pc, offs_t &flags, const m32c_disassembler::data_buffer &opcodes, u8 op1, bool indirect_dest) const { u8 op2 = opcodes.r8(pc++); if ((op2 & 0x30) == 0 || ((op2 & 0x30) == 0x20 && !BIT(op1, 4))) @@ -877,6 +877,7 @@ void m32c_disassembler::dasm_111x(std::ostream &stream, offs_t &pc, const m32c_d dasm_operand(stream, pc, opcodes, (op1 & 0x0e) << 1 | BIT(op2, 6, 2), op1 & 1, indirect_dest); stream << ", "; format_label(stream, pc + s8(opcodes.r8(pc))); + flags |= STEP_COND; ++pc; } else if ((op2 & 0x30) == 0x30 && BIT(op1, 4)) @@ -1050,6 +1051,7 @@ offs_t m32c_disassembler::disassemble(std::ostream &stream, offs_t pc, const m32 util::stream_format(stream, "%-11s", util::string_format("j%s", s_cnds[bitswap<4>(op1, 6, 5, 4, 0)])); format_label(stream, pc + s8(opcodes.r8(pc))); ++pc; + flags |= STEP_COND; break; case 0x8c: case 0x8d: @@ -1211,7 +1213,7 @@ offs_t m32c_disassembler::disassemble(std::ostream &stream, offs_t pc, const m32 case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7: case 0xe8: case 0xe9: case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: case 0xf8: case 0xf9: - dasm_111x(stream, pc, opcodes, op1, indirect_dest); + dasm_111x(stream, pc, flags, opcodes, op1, indirect_dest); break; case 0xec: |