diff options
author | 2017-12-13 21:01:10 -0700 | |
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committer | 2017-12-13 21:01:10 -0700 | |
commit | 54155441e9ba9941e85d80c4834a66376a11e791 (patch) | |
tree | aa44bdaf0035cbe188d64c447f225f10f7d76d8d /src/devices/cpu/i386/i386.cpp | |
parent | f537428e5a40ba6dde8ca9bf0fe9ae6b1f189ac4 (diff) |
Revert "Merge branch 'master' of https://github.com/mamedev/mame"
This reverts commit f537428e5a40ba6dde8ca9bf0fe9ae6b1f189ac4, reversing
changes made to 0d70d798107d4e4e8fb9f230410aeb1e888d65c5.
Diffstat (limited to 'src/devices/cpu/i386/i386.cpp')
-rw-r--r-- | src/devices/cpu/i386/i386.cpp | 106 |
1 files changed, 53 insertions, 53 deletions
diff --git a/src/devices/cpu/i386/i386.cpp b/src/devices/cpu/i386/i386.cpp index dd6d86928e2..15379c18d7b 100644 --- a/src/devices/cpu/i386/i386.cpp +++ b/src/devices/cpu/i386/i386.cpp @@ -3788,59 +3788,59 @@ void i386_device::pentium_smi() m_smi_latched = false; // save state - WRITE32(smram_state + SMRAM_IP5_CR4, m_cr[4]); - WRITE32(smram_state + SMRAM_IP5_ESLIM, m_sreg[ES].limit); - WRITE32(smram_state + SMRAM_IP5_ESBASE, m_sreg[ES].base); - WRITE32(smram_state + SMRAM_IP5_ESACC, m_sreg[ES].flags); - WRITE32(smram_state + SMRAM_IP5_CSLIM, m_sreg[CS].limit); - WRITE32(smram_state + SMRAM_IP5_CSBASE, m_sreg[CS].base); - WRITE32(smram_state + SMRAM_IP5_CSACC, m_sreg[CS].flags); - WRITE32(smram_state + SMRAM_IP5_SSLIM, m_sreg[SS].limit); - WRITE32(smram_state + SMRAM_IP5_SSBASE, m_sreg[SS].base); - WRITE32(smram_state + SMRAM_IP5_SSACC, m_sreg[SS].flags); - WRITE32(smram_state + SMRAM_IP5_DSLIM, m_sreg[DS].limit); - WRITE32(smram_state + SMRAM_IP5_DSBASE, m_sreg[DS].base); - WRITE32(smram_state + SMRAM_IP5_DSACC, m_sreg[DS].flags); - WRITE32(smram_state + SMRAM_IP5_FSLIM, m_sreg[FS].limit); - WRITE32(smram_state + SMRAM_IP5_FSBASE, m_sreg[FS].base); - WRITE32(smram_state + SMRAM_IP5_FSACC, m_sreg[FS].flags); - WRITE32(smram_state + SMRAM_IP5_GSLIM, m_sreg[GS].limit); - WRITE32(smram_state + SMRAM_IP5_GSBASE, m_sreg[GS].base); - WRITE32(smram_state + SMRAM_IP5_GSACC, m_sreg[GS].flags); - WRITE32(smram_state + SMRAM_IP5_LDTACC, m_ldtr.flags); - WRITE32(smram_state + SMRAM_IP5_LDTLIM, m_ldtr.limit); - WRITE32(smram_state + SMRAM_IP5_LDTBASE, m_ldtr.base); - WRITE32(smram_state + SMRAM_IP5_GDTLIM, m_gdtr.limit); - WRITE32(smram_state + SMRAM_IP5_GDTBASE, m_gdtr.base); - WRITE32(smram_state + SMRAM_IP5_IDTLIM, m_idtr.limit); - WRITE32(smram_state + SMRAM_IP5_IDTBASE, m_idtr.base); - WRITE32(smram_state + SMRAM_IP5_TRLIM, m_task.limit); - WRITE32(smram_state + SMRAM_IP5_TRBASE, m_task.base); - WRITE32(smram_state + SMRAM_IP5_TRACC, m_task.flags); - - WRITE32(smram_state + SMRAM_ES, m_sreg[ES].selector); - WRITE32(smram_state + SMRAM_CS, m_sreg[CS].selector); - WRITE32(smram_state + SMRAM_SS, m_sreg[SS].selector); - WRITE32(smram_state + SMRAM_DS, m_sreg[DS].selector); - WRITE32(smram_state + SMRAM_FS, m_sreg[FS].selector); - WRITE32(smram_state + SMRAM_GS, m_sreg[GS].selector); - WRITE32(smram_state + SMRAM_LDTR, m_ldtr.segment); - WRITE32(smram_state + SMRAM_TR, m_task.segment); - - WRITE32(smram_state + SMRAM_DR7, m_dr[7]); - WRITE32(smram_state + SMRAM_DR6, m_dr[6]); - WRITE32(smram_state + SMRAM_EAX, REG32(EAX)); - WRITE32(smram_state + SMRAM_ECX, REG32(ECX)); - WRITE32(smram_state + SMRAM_EDX, REG32(EDX)); - WRITE32(smram_state + SMRAM_EBX, REG32(EBX)); - WRITE32(smram_state + SMRAM_ESP, REG32(ESP)); - WRITE32(smram_state + SMRAM_EBP, REG32(EBP)); - WRITE32(smram_state + SMRAM_ESI, REG32(ESI)); - WRITE32(smram_state + SMRAM_EDI, REG32(EDI)); - WRITE32(smram_state + SMRAM_EIP, m_eip); - WRITE32(smram_state + SMRAM_EFLAGS, old_flags); - WRITE32(smram_state + SMRAM_CR3, m_cr[3]); - WRITE32(smram_state + SMRAM_CR0, old_cr0); + WRITE32(m_cr[4], smram_state+SMRAM_IP5_CR4); + WRITE32(m_sreg[ES].limit, smram_state+SMRAM_IP5_ESLIM); + WRITE32(m_sreg[ES].base, smram_state+SMRAM_IP5_ESBASE); + WRITE32(m_sreg[ES].flags, smram_state+SMRAM_IP5_ESACC); + WRITE32(m_sreg[CS].limit, smram_state+SMRAM_IP5_CSLIM); + WRITE32(m_sreg[CS].base, smram_state+SMRAM_IP5_CSBASE); + WRITE32(m_sreg[CS].flags, smram_state+SMRAM_IP5_CSACC); + WRITE32(m_sreg[SS].limit, smram_state+SMRAM_IP5_SSLIM); + WRITE32(m_sreg[SS].base, smram_state+SMRAM_IP5_SSBASE); + WRITE32(m_sreg[SS].flags, smram_state+SMRAM_IP5_SSACC); + WRITE32(m_sreg[DS].limit, smram_state+SMRAM_IP5_DSLIM); + WRITE32(m_sreg[DS].base, smram_state+SMRAM_IP5_DSBASE); + WRITE32(m_sreg[DS].flags, smram_state+SMRAM_IP5_DSACC); + WRITE32(m_sreg[FS].limit, smram_state+SMRAM_IP5_FSLIM); + WRITE32(m_sreg[FS].base, smram_state+SMRAM_IP5_FSBASE); + WRITE32(m_sreg[FS].flags, smram_state+SMRAM_IP5_FSACC); + WRITE32(m_sreg[GS].limit, smram_state+SMRAM_IP5_GSLIM); + WRITE32(m_sreg[GS].base, smram_state+SMRAM_IP5_GSBASE); + WRITE32(m_sreg[GS].flags, smram_state+SMRAM_IP5_GSACC); + WRITE32(m_ldtr.flags, smram_state+SMRAM_IP5_LDTACC); + WRITE32(m_ldtr.limit, smram_state+SMRAM_IP5_LDTLIM); + WRITE32(m_ldtr.base, smram_state+SMRAM_IP5_LDTBASE); + WRITE32(m_gdtr.limit, smram_state+SMRAM_IP5_GDTLIM); + WRITE32(m_gdtr.base, smram_state+SMRAM_IP5_GDTBASE); + WRITE32(m_idtr.limit, smram_state+SMRAM_IP5_IDTLIM); + WRITE32(m_idtr.base, smram_state+SMRAM_IP5_IDTBASE); + WRITE32(m_task.limit, smram_state+SMRAM_IP5_TRLIM); + WRITE32(m_task.base, smram_state+SMRAM_IP5_TRBASE); + WRITE32(m_task.flags, smram_state+SMRAM_IP5_TRACC); + + WRITE32(m_sreg[ES].selector, smram_state+SMRAM_ES); + WRITE32(m_sreg[CS].selector, smram_state+SMRAM_CS); + WRITE32(m_sreg[SS].selector, smram_state+SMRAM_SS); + WRITE32(m_sreg[DS].selector, smram_state+SMRAM_DS); + WRITE32(m_sreg[FS].selector, smram_state+SMRAM_FS); + WRITE32(m_sreg[GS].selector, smram_state+SMRAM_GS); + WRITE32(m_ldtr.segment, smram_state+SMRAM_LDTR); + WRITE32(m_task.segment, smram_state+SMRAM_TR); + + WRITE32(m_dr[7], smram_state+SMRAM_DR7); + WRITE32(m_dr[6], smram_state+SMRAM_DR6); + WRITE32(REG32(EAX), smram_state+SMRAM_EAX); + WRITE32(REG32(ECX), smram_state+SMRAM_ECX); + WRITE32(REG32(EDX), smram_state+SMRAM_EDX); + WRITE32(REG32(EBX), smram_state+SMRAM_EBX); + WRITE32(REG32(ESP), smram_state+SMRAM_ESP); + WRITE32(REG32(EBP), smram_state+SMRAM_EBP); + WRITE32(REG32(ESI), smram_state+SMRAM_ESI); + WRITE32(REG32(EDI), smram_state+SMRAM_EDI); + WRITE32(m_eip, smram_state+SMRAM_EIP); + WRITE32(old_flags, smram_state+SMRAM_EFLAGS); + WRITE32(m_cr[3], smram_state+SMRAM_CR3); + WRITE32(old_cr0, smram_state+SMRAM_CR0); m_sreg[DS].selector = m_sreg[ES].selector = m_sreg[FS].selector = m_sreg[GS].selector = m_sreg[SS].selector = 0; m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000; |