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author Olivier Galibert <galibert@pobox.com>2020-05-25 16:42:42 +0200
committer Olivier Galibert <galibert@pobox.com>2020-05-25 16:42:57 +0200
commit22513fb6fe281f5ccb75aaddb6417a12a66c313d (patch)
tree3cf84032cc6482d685a8dbb57e015bd17c7f7fdc /src/devices/cpu/i386/athlon.cpp
parente42c2d2874cf9c1092c01ab5ce9ef997d465ce25 (diff)
emumem: A little more speedup. cache and specific change syntax, and are not pointers anymore [O. Galibert]
The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
Diffstat (limited to 'src/devices/cpu/i386/athlon.cpp')
-rw-r--r--src/devices/cpu/i386/athlon.cpp54
1 files changed, 30 insertions, 24 deletions
diff --git a/src/devices/cpu/i386/athlon.cpp b/src/devices/cpu/i386/athlon.cpp
index e47f99a2af6..7da09ef271b 100644
--- a/src/devices/cpu/i386/athlon.cpp
+++ b/src/devices/cpu/i386/athlon.cpp
@@ -28,10 +28,11 @@ void athlonxp_device::device_start()
{
i386_common_init();
register_state_i386_x87_xmm();
- m_data = &space(AS_DATA);
- m_opcodes = &space(AS_OPCODES);
- mmacache32 = m_data->cache<2, 0, ENDIANNESS_LITTLE>();
- m_opcodes->install_read_handler(0, 0xffffffff, read32_delegate(*this, FUNC(athlonxp_device::debug_read_memory)));
+ space(AS_DATA).specific(m_data);
+ space(AS_OPCODES).specific(m_opcodes);
+ space(AS_DATA).cache(mmacache32);
+
+ space(AS_OPCODES).install_read_handler(0, 0xffffffff, read32_delegate(*this, FUNC(athlonxp_device::debug_read_memory)));
build_x87_opcode_table();
build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE);
@@ -192,7 +193,6 @@ READ32_MEMBER(athlonxp_device::debug_read_memory)
offs_t address = offset << 2;
int mode = check_cacheable(address);
bool nocache = false;
- address_space *m = m_program;
u8 *data;
if ((mode & 7) == 0)
@@ -207,8 +207,8 @@ READ32_MEMBER(athlonxp_device::debug_read_memory)
return *(u32 *)(data + offset);
}
if (address_mode<1>(address))
- m = m_data;
- return m->read_dword(address);
+ return m_data.read_dword(address);
+ return m_program->read_dword(address);
}
template <class dt, offs_t xorle>
@@ -216,7 +216,6 @@ dt athlonxp_device::opcode_read_cache(offs_t address)
{
int mode = check_cacheable(address);
bool nocache = false;
- memory_access_cache<2, 0, ENDIANNESS_LITTLE> *m = macache32;
u8 *data;
if ((mode & 7) == 0)
@@ -238,28 +237,35 @@ dt athlonxp_device::opcode_read_cache(offs_t address)
offs_t old_address = cache.old();
for (int w = 0; w < 64; w += 4)
- m->write_dword(old_address + w, *(u32 *)(data + w));
+ macache32.write_dword(old_address + w, *(u32 *)(data + w));
}
for (int r = 0; r < 64; r += 4)
- *(u32 *)(data + r) = m->read_dword(address + r);
+ *(u32 *)(data + r) = macache32.read_dword(address + r);
return *(dt *)(data + offset);
}
}
if (address_mode<1>(address))
- m = mmacache32;
+ {
+ if (sizeof(dt) == 1)
+ return mmacache32.read_byte(address);
+ else if (sizeof(dt) == 2)
+ return mmacache32.read_word(address);
+ else
+ return mmacache32.read_dword(address);
+ }
if (sizeof(dt) == 1)
- return m->read_byte(address);
+ return macache32.read_byte(address);
else if (sizeof(dt) == 2)
- return m->read_word(address);
+ return macache32.read_word(address);
else
- return m->read_dword(address);
+ return macache32.read_dword(address);
+
}
uint32_t athlonxp_device::program_read_cache(offs_t address, uint32_t mask)
{
int mode = check_cacheable(address);
bool nocache = false;
- address_space *m = m_program;
u8 *data;
if ((mode & 7) == 0)
@@ -281,23 +287,22 @@ uint32_t athlonxp_device::program_read_cache(offs_t address, uint32_t mask)
offs_t old_address = cache.old();
for (int w = 0; w < 64; w += 4)
- m->write_dword(old_address + w, *(u32 *)(data + w));
+ m_program->write_dword(old_address + w, *(u32 *)(data + w));
}
for (int r = 0; r < 64; r += 4)
- *(u32 *)(data + r) = m->read_dword(address + r);
+ *(u32 *)(data + r) = m_program->read_dword(address + r);
return *(u32 *)(data + offset) & mask;
}
}
if (address_mode<1>(address))
- m = m_data;
- return m->read_dword(address, mask) & mask;
+ return m_data.read_dword(address, mask) & mask;
+ return m_program->read_dword(address, mask) & mask;
}
void athlonxp_device::program_write_cache(offs_t address, uint32_t data, uint32_t mask)
{
int mode = check_cacheable(address);
bool nocache = false;
- address_space *m = m_program;
u8 *dataw;
if ((mode & 7) == 0)
@@ -322,17 +327,18 @@ void athlonxp_device::program_write_cache(offs_t address, uint32_t data, uint32_
offs_t old_address = cache.old();
for (int w = 0; w < 64; w += 4)
- m->write_dword(old_address + w, *(u32 *)(dataw + w));
+ m_program->write_dword(old_address + w, *(u32 *)(dataw + w));
}
for (int r = 0; r < 64; r += 4)
- *(u32 *)(dataw + r) = m->read_dword(address + r);
+ *(u32 *)(dataw + r) = m_program->read_dword(address + r);
*(u32 *)(dataw + offset) = (*(u32 *)(dataw + offset) & ~mask) | (data & mask);
return;
}
}
if (address_mode<0>(address))
- m = m_data;
- m->write_dword(address, data, mask);
+ m_data.write_dword(address, data, mask);
+ else
+ m_program->write_dword(address, data, mask);
}
void athlonxp_device::cache_writeback()