diff options
author | 2018-03-25 02:03:24 +1100 | |
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committer | 2018-03-25 02:03:24 +1100 | |
commit | 08dde5eb0acb30b68b403a2b9ad2fd503067f2bd (patch) | |
tree | 9ea8ba7c97d124aa4f7600ebb183667609f81224 /src/devices/cpu/diablo/diablo1300dasm.cpp | |
parent | 8142f24c4307439397ffb2c01fab76e6f2c1b95e (diff) |
srcclean and regenerate localisations (nw)
Diffstat (limited to 'src/devices/cpu/diablo/diablo1300dasm.cpp')
-rw-r--r-- | src/devices/cpu/diablo/diablo1300dasm.cpp | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/devices/cpu/diablo/diablo1300dasm.cpp b/src/devices/cpu/diablo/diablo1300dasm.cpp index 3bc0a921dd2..ed62f3957a6 100644 --- a/src/devices/cpu/diablo/diablo1300dasm.cpp +++ b/src/devices/cpu/diablo/diablo1300dasm.cpp @@ -22,8 +22,8 @@ offs_t diablo1300_disassembler::disassemble(std::ostream &stream, offs_t pc, con { case 0: // OUTPUT Dport, Sreg util::stream_format(stream, "OUTPUT dv%d, r%02X", - (op & 0x0070) >> 4, - ((op & 0x0f00) >> 8) + ((op & 0x0008) ? 0x10 : 0)); + (op & 0x0070) >> 4, + ((op & 0x0f00) >> 8) + ((op & 0x0008) ? 0x10 : 0)); break; case 1: // JNC Addr util::stream_format(stream, "JNC %03X", ((op & 0xff00) >> 8) + ((op & 0x0008) ? 0x100 : 0)); @@ -33,25 +33,25 @@ offs_t diablo1300_disassembler::disassemble(std::ostream &stream, offs_t pc, con break; case 3: // LDBBIT Sreg, #val util::stream_format(stream, "LDBBIT r%02X, %02X", - ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), - (op & 0xff00) >> 8); + ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), + (op & 0xff00) >> 8); break; case 4: // switch (op & 0xc000) { case 0x4000: // XLAT Dreg util::stream_format(stream, "XLAT r%02X", - ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0)); + ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0)); break; case 0xc000: // MOVCPL Dreg, Sreg util::stream_format(stream, "MOVCPL r%02X, r%02X", - ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), - ((op & 0x0f00) >> 8) + ((op & 0x0008) ? 0x10 : 0)); + ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), + ((op & 0x0f00) >> 8) + ((op & 0x0008) ? 0x10 : 0)); break; case 0x8000: // INPUT Dreg, Sport util::stream_format(stream, "INPUT r%02X, dv%X", - ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), - ((op & 0x0f00) >> 8)); + ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), + ((op & 0x0f00) >> 8)); break; default: util::stream_format(stream, "???"); @@ -60,18 +60,18 @@ offs_t diablo1300_disassembler::disassemble(std::ostream &stream, offs_t pc, con break; case 5: // LOAD# Dreg,#val util::stream_format(stream, "LOAD# r%02X, %02X", - ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), - (op & 0xff00) >> 8); + ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), + (op & 0xff00) >> 8); break; case 6: // ADCCPL S/Dreg, Sreg util::stream_format(stream, "ADCCPL r%02X, r%02X", - ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), - ((op & 0x0f00) >> 8) + ((op & 0x0008) ? 0x10 : 0)); + ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), + ((op & 0x0f00) >> 8) + ((op & 0x0008) ? 0x10 : 0)); break; case 7: // ADC# S/Dreg, val util::stream_format(stream, "ADC# r%02X, %02X", - ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), - (op & 0xff00) >> 8); + ((op & 0x00f0) >> 4) + ((op & 0x0008) ? 0x10 : 0), + (op & 0xff00) >> 8); break; default: util::stream_format(stream, "???"); |