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author arbee <rb6502@users.noreply.github.com>2018-07-15 13:07:51 -0400
committer arbee <rb6502@users.noreply.github.com>2018-07-15 13:07:51 -0400
commit16336848af90c92c8945ad7503078b9d22bbcdd2 (patch)
tree6bfd76c7e8805504756ab10a217f02a655ec7039 /scripts/build/complay.py
parent7eff013f87079d580af28d5d85fb4ae90363703c (diff)
mc146818: support direct-access bus hookup method. [R. Belmont]
This chip has 8 address/data lines and an address/data strobe. Most users hooked it up so the low-order address bit is the address/data strobe, allowing you to write an address and then read/write data at an adjacent address. But if you don't mind using a few more gates you can latch the low-order address bits from the CPU into the chip then latch the data in or out of it so it works just like a RAM. The MIPS DECstations did this in their I/O ASICs.
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