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author hap <happppp@users.noreply.github.com>2023-06-16 13:01:35 +0200
committer hap <happppp@users.noreply.github.com>2023-06-16 13:01:35 +0200
commit95228a9955c04fd71884c25f721b864d1c00b21c (patch)
treeb7a034eacb000fce1c091c7c76dcbab6ef0d8965
parent3e94326fe23d2b62a27a69a720d6f36bbf620496 (diff)
m6801: add i/o ports tri-state callback,
misc: correct some typos
-rw-r--r--src/devices/cpu/i86/i286.cpp2
-rw-r--r--src/devices/cpu/m6800/m6801.cpp30
-rw-r--r--src/devices/cpu/m6800/m6801.h14
-rw-r--r--src/devices/machine/68340sim.cpp2
-rw-r--r--src/mame/bfm/rastersp.cpp2
-rw-r--r--src/mame/namco/namco06.cpp2
-rw-r--r--src/mame/namco/namcos1.cpp1
-rw-r--r--src/mame/namco/warpwarp.cpp6
-rw-r--r--src/mame/pc/calchase.cpp22
-rw-r--r--src/mame/shared/xbox_usb.h2
10 files changed, 50 insertions, 33 deletions
diff --git a/src/devices/cpu/i86/i286.cpp b/src/devices/cpu/i86/i286.cpp
index c13985bf2eb..ece39503c44 100644
--- a/src/devices/cpu/i86/i286.cpp
+++ b/src/devices/cpu/i86/i286.cpp
@@ -1344,7 +1344,7 @@ m_limit[sreg] = LIMIT(desc); }
LOADDESC(0x842, SS);
LOADDESC(0x848, DS);
#undef LOADDESC
- // void cast supresses warning
+ // void cast suppresses warning
#define LOADDESC(addr, reg, r) { desc[1] = read_word(addr); desc[2] = read_word(addr + 2); desc[0] = read_word(addr + 4); \
reg.base = BASE(desc); (void)(r); reg.limit = LIMIT(desc); }
LOADDESC(0x84e, m_gdtr, 1);
diff --git a/src/devices/cpu/m6800/m6801.cpp b/src/devices/cpu/m6800/m6801.cpp
index 0388134d0f6..9fd76e77645 100644
--- a/src/devices/cpu/m6800/m6801.cpp
+++ b/src/devices/cpu/m6800/m6801.cpp
@@ -317,6 +317,7 @@ m6801_cpu_device::m6801_cpu_device(const machine_config &mconfig, device_type ty
: m6800_cpu_device(mconfig, type, tag, owner, clock, insn, cycles, internal)
, m_in_port_func(*this)
, m_out_port_func(*this)
+ , m_tri_port_func(*this)
, m_out_sc2_func(*this)
, m_out_sertx_func(*this)
, m_sclk_divider(8)
@@ -357,6 +358,7 @@ hd6301x_cpu_device::hd6301x_cpu_device(const machine_config &mconfig, device_typ
: hd6301_cpu_device(mconfig, type, tag, owner, clock, hd63701_insn, cycles_63701)
, m_in_portx_func(*this)
, m_out_portx_func(*this)
+ , m_tri_portx_func(*this)
{
m_sclk_divider = 16;
}
@@ -1021,6 +1023,7 @@ void m6801_cpu_device::device_resolve_objects()
m_in_port_func.resolve_all_safe(0xff);
m_out_port_func.resolve_all_safe();
+ m_tri_port_func.resolve_all_safe(0xff);
m_out_sc2_func.resolve_safe();
m_out_sertx_func.resolve_safe();
}
@@ -1031,6 +1034,7 @@ void hd6301x_cpu_device::device_resolve_objects()
m_in_portx_func.resolve_all_safe(0xff);
m_out_portx_func.resolve_all_safe();
+ m_tri_portx_func.resolve_all_safe(0xff);
}
@@ -1226,7 +1230,7 @@ void m6801_cpu_device::write_port2()
if ((ddr != 0x1f) && ddr)
{
- data = (m_port_data[1] & ddr) | (ddr ^ 0xff);
+ data = (m_port_data[1] & ddr) | (~ddr & m_tri_port_func[1]());
}
if (m_trcsr & M6801_TRCSR_TE)
@@ -1250,7 +1254,7 @@ void hd6301x_cpu_device::write_port2()
if (m_tcsr2 & TCSR2_OE2)
ddr |= 0x20;
- uint8_t data = (m_port_data[1] & ddr) | (ddr ^ 0xff);
+ uint8_t data = (m_port_data[1] & ddr) | (~ddr & m_tri_port_func[1]());
if (m_trcsr & M6801_TRCSR_TE)
{
@@ -1289,7 +1293,7 @@ void m6801_cpu_device::p1_ddr_w(uint8_t data)
if (m_port_ddr[0] != data)
{
m_port_ddr[0] = data;
- m_out_port_func[0](0, (m_port_data[0] & m_port_ddr[0]) | (m_port_ddr[0] ^ 0xff), m_port_ddr[0]);
+ m_out_port_func[0](0, (m_port_data[0] & m_port_ddr[0]) | (~m_port_ddr[0] & m_tri_port_func[0]()), m_port_ddr[0]);
}
}
@@ -1306,7 +1310,7 @@ void m6801_cpu_device::p1_data_w(uint8_t data)
LOGPORT("Port 1 Data Register: %02x\n", data);
m_port_data[0] = data;
- m_out_port_func[0](0, (m_port_data[0] & m_port_ddr[0]) | (m_port_ddr[0] ^ 0xff), m_port_ddr[0]);
+ m_out_port_func[0](0, (m_port_data[0] & m_port_ddr[0]) | (~m_port_ddr[0] & m_tri_port_func[0]()), m_port_ddr[0]);
}
void m6801_cpu_device::p2_ddr_w(uint8_t data)
@@ -1357,7 +1361,7 @@ void m6801_cpu_device::p3_ddr_w(uint8_t data)
if (m_port_ddr[2] != data)
{
m_port_ddr[2] = data;
- m_out_port_func[2](0, (m_port_data[2] & m_port_ddr[2]) | (m_port_ddr[2] ^ 0xff), m_port_ddr[2]);
+ m_out_port_func[2](0, (m_port_data[2] & m_port_ddr[2]) | (~m_port_ddr[2] & m_tri_port_func[2]()), m_port_ddr[2]);
}
}
@@ -1414,7 +1418,7 @@ void m6801_cpu_device::p3_data_w(uint8_t data)
}
m_port_data[2] = data;
- m_out_port_func[2](0, (m_port_data[2] & m_port_ddr[2]) | (m_port_ddr[2] ^ 0xff), m_port_ddr[2]);
+ m_out_port_func[2](0, (m_port_data[2] & m_port_ddr[2]) | (~m_port_ddr[2] & m_tri_port_func[2]()), m_port_ddr[2]);
if (m_p3csr & M6801_P3CSR_OSS)
{
@@ -1437,7 +1441,7 @@ void hd6301x_cpu_device::p3_data_w(uint8_t data)
LOGPORT("Port 3 Data Register: %02x\n", data);
m_port_data[2] = data;
- m_out_port_func[2](0, (m_port_data[2] & m_port_ddr[2]) | (m_port_ddr[2] ^ 0xff), m_port_ddr[2]);
+ m_out_port_func[2](0, (m_port_data[2] & m_port_ddr[2]) | (~m_port_ddr[2] & m_tri_port_func[2]()), m_port_ddr[2]);
}
uint8_t m6801_cpu_device::p3_csr_r()
@@ -1464,7 +1468,7 @@ void m6801_cpu_device::p4_ddr_w(uint8_t data)
if (m_port_ddr[3] != data)
{
m_port_ddr[3] = data;
- m_out_port_func[3](0, (m_port_data[3] & m_port_ddr[3]) | (m_port_ddr[3] ^ 0xff), m_port_ddr[3]);
+ m_out_port_func[3](0, (m_port_data[3] & m_port_ddr[3]) | (~m_port_ddr[3] & m_tri_port_func[3]()), m_port_ddr[3]);
}
}
@@ -1481,7 +1485,7 @@ void m6801_cpu_device::p4_data_w(uint8_t data)
LOGPORT("Port 4 Data Register: %02x\n", data);
m_port_data[3] = data;
- m_out_port_func[3](0, (m_port_data[3] & m_port_ddr[3]) | (m_port_ddr[3] ^ 0xff), m_port_ddr[3]);
+ m_out_port_func[3](0, (m_port_data[3] & m_port_ddr[3]) | (~m_port_ddr[3] & m_tri_port_func[3]()), m_port_ddr[3]);
}
void hd6301y_cpu_device::p5_ddr_w(uint8_t data)
@@ -1491,7 +1495,7 @@ void hd6301y_cpu_device::p5_ddr_w(uint8_t data)
if (m_portx_ddr[0] != data)
{
m_portx_ddr[0] = data;
- m_out_portx_func[0](0, (m_portx_data[0] & m_portx_ddr[0]) | (m_portx_ddr[0] ^ 0xff), m_portx_ddr[0]);
+ m_out_portx_func[0](0, (m_portx_data[0] & m_portx_ddr[0]) | (~m_portx_ddr[0] & m_tri_portx_func[0]()), m_portx_ddr[0]);
}
}
@@ -1514,7 +1518,7 @@ void hd6301y_cpu_device::p5_data_w(uint8_t data)
LOGPORT("Port 5 Data Register: %02x\n", data);
m_portx_data[0] = data;
- m_out_portx_func[0](0, (m_portx_data[0] & m_portx_ddr[0]) | (m_portx_ddr[0] ^ 0xff), m_portx_ddr[0]);
+ m_out_portx_func[0](0, (m_portx_data[0] & m_portx_ddr[0]) | (~m_portx_ddr[0] & m_tri_portx_func[0]()), m_portx_ddr[0]);
}
void hd6301x_cpu_device::p6_ddr_w(uint8_t data)
@@ -1524,7 +1528,7 @@ void hd6301x_cpu_device::p6_ddr_w(uint8_t data)
if (m_portx_ddr[1] != data)
{
m_portx_ddr[1] = data;
- m_out_portx_func[1](0, (m_portx_data[1] & m_portx_ddr[1]) | (m_portx_ddr[1] ^ 0xff), m_portx_ddr[1]);
+ m_out_portx_func[1](0, (m_portx_data[1] & m_portx_ddr[1]) | (~m_portx_ddr[1] & m_tri_portx_func[1]()), m_portx_ddr[1]);
}
}
@@ -1541,7 +1545,7 @@ void hd6301x_cpu_device::p6_data_w(uint8_t data)
LOGPORT("Port 6 Data Register: %02x\n", data);
m_portx_data[1] = data;
- m_out_portx_func[1](0, (m_portx_data[1] & m_portx_ddr[1]) | (m_portx_ddr[1] ^ 0xff), m_portx_ddr[1]);
+ m_out_portx_func[1](0, (m_portx_data[1] & m_portx_ddr[1]) | (~m_portx_ddr[1] & m_tri_portx_func[1]()), m_portx_ddr[1]);
}
uint8_t hd6301y_cpu_device::p6_data_r()
diff --git a/src/devices/cpu/m6800/m6801.h b/src/devices/cpu/m6800/m6801.h
index 3a8a4553078..b680afe4dd0 100644
--- a/src/devices/cpu/m6800/m6801.h
+++ b/src/devices/cpu/m6800/m6801.h
@@ -45,6 +45,7 @@ class m6801_cpu_device : public m6800_cpu_device
public:
m6801_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ // port 1-4 I/O
auto in_p1_cb() { return m_in_port_func[0].bind(); }
auto out_p1_cb() { return m_out_port_func[0].bind(); }
auto in_p2_cb() { return m_in_port_func[1].bind(); }
@@ -54,6 +55,12 @@ public:
auto in_p4_cb() { return m_in_port_func[3].bind(); }
auto out_p4_cb() { return m_out_port_func[3].bind(); }
+ // port outputs when in tri-state (high-impedance), default 0xff
+ auto tri_p1_cb() { return m_tri_port_func[0].bind(); }
+ auto tri_p2_cb() { return m_tri_port_func[1].bind(); }
+ auto tri_p3_cb() { return m_tri_port_func[2].bind(); }
+ auto tri_p4_cb() { return m_tri_port_func[3].bind(); }
+
auto out_sc2_cb() { return m_out_sc2_func.bind(); }
auto out_ser_tx_cb() { return m_out_sertx_func.bind(); }
@@ -122,6 +129,7 @@ protected:
devcb_read8::array<4> m_in_port_func;
devcb_write8::array<4> m_out_port_func;
+ devcb_read8::array<4> m_tri_port_func;
devcb_write_line m_out_sc2_func;
devcb_write_line m_out_sertx_func;
@@ -251,12 +259,17 @@ public:
class hd6301x_cpu_device : public hd6301_cpu_device
{
public:
+ // port 5-7 I/O
auto in_p5_cb() { return m_in_portx_func[0].bind(); }
auto out_p5_cb() { return m_out_portx_func[0].bind(); }
auto in_p6_cb() { return m_in_portx_func[1].bind(); }
auto out_p6_cb() { return m_out_portx_func[1].bind(); }
auto out_p7_cb() { return m_out_portx_func[2].bind(); }
+ // port outputs when in tri-state (high-impedance), default 0xff
+ auto tri_p5_cb() { return m_tri_portx_func[0].bind(); }
+ auto tri_p6_cb() { return m_tri_portx_func[1].bind(); }
+
// TODO: privatize eventually
void hd6301x_io(address_map &map);
@@ -305,6 +318,7 @@ protected:
devcb_read8::array<2> m_in_portx_func;
devcb_write8::array<3> m_out_portx_func;
+ devcb_read8::array<2> m_tri_portx_func;
uint8_t m_portx_ddr[2];
uint8_t m_portx_data[3];
diff --git a/src/devices/machine/68340sim.cpp b/src/devices/machine/68340sim.cpp
index 3f23bdafc89..94483e625cc 100644
--- a/src/devices/machine/68340sim.cpp
+++ b/src/devices/machine/68340sim.cpp
@@ -113,7 +113,7 @@ void m68340_cpu_device::m68340_internal_sim_w(offs_t offset, uint16_t data, uint
LOGSIM("PC: %08x %s %04x, %04x (%04x) (MCR - Module Configuration Register)\n", m_ppc, FUNCNAME, offset * 2, data, mem_mask);
LOGPIT("- FRZ1: Watchdog and PIT timer are %s\n", (data & m68340_sim::REG_MCR_FRZ1) == 0 ? "enabled" : "disabled");
LOGSIM("- FRZ0: The BUS monitor is %s\n", (data & m68340_sim::REG_MCR_FRZ0) == 0 ? "enabled" : "disabled");
- LOGSIM("- FIRQ: Full Interrupt Request Mode %s\n", data & m68340_sim::REG_MCR_FIRQ ? "used on port B" : "supressed, adding 4 chip select lines on Port B");
+ LOGSIM("- FIRQ: Full Interrupt Request Mode %s\n", data & m68340_sim::REG_MCR_FIRQ ? "used on port B" : "suppressed, adding 4 chip select lines on Port B");
LOGSIM("- SHEN0-SHEN1: Show Cycle Enable %02x - not implemented\n", ((data & m68340_sim::REG_MCR_SHEN) >> 8));
LOGSIM("- Supervisor registers %s - not implemented\n", data & m68340_sim::REG_MCR_SVREG ? "requries supervisor privileges" : "can be accessed by user privileged software");
LOGSIM("- Interrupt Arbitration level: %02x\n", data & m68340_sim::REG_MCR_ARBLV);
diff --git a/src/mame/bfm/rastersp.cpp b/src/mame/bfm/rastersp.cpp
index 85cc5e551ff..2938cd7444c 100644
--- a/src/mame/bfm/rastersp.cpp
+++ b/src/mame/bfm/rastersp.cpp
@@ -924,7 +924,7 @@ void rastersp_state::interrupt_ctrl_w(offs_t offset, uint8_t data)
uint8_t rastersp_state::interrupt_status_r(offs_t offset)
{
// TODO: This returns something to do with interrupts
- // Is it a bit pattern of the current interupt or a
+ // Is it a bit pattern of the current interrupt or a
// bit pattern of all interrupts pending?
// Either way, 0 works anyway!
return 0;
diff --git a/src/mame/namco/namco06.cpp b/src/mame/namco/namco06.cpp
index c4435f040f8..8fb911e4f25 100644
--- a/src/mame/namco/namco06.cpp
+++ b/src/mame/namco/namco06.cpp
@@ -201,7 +201,7 @@ TIMER_CALLBACK_MEMBER( namco_06xx_device::ctrl_w_sync )
else
{
// NMI is cleared immediately if this is a read
- // It will be supressed the next clock cycle.
+ // It will be suppressed the next clock cycle.
if (BIT(m_control, 4))
{
set_nmi(CLEAR_LINE);
diff --git a/src/mame/namco/namcos1.cpp b/src/mame/namco/namcos1.cpp
index c511cf1d088..bf576b881ea 100644
--- a/src/mame/namco/namcos1.cpp
+++ b/src/mame/namco/namcos1.cpp
@@ -1019,6 +1019,7 @@ void namcos1_state::ns1(machine_config &config)
m_mcu->set_addrmap(AS_PROGRAM, &namcos1_state::mcu_map);
m_mcu->in_p1_cb().set_ioport("COIN");
m_mcu->out_p1_cb().set(FUNC(namcos1_state::coin_w));
+ m_mcu->tri_p1_cb().set_constant(0);
m_mcu->out_p2_cb().set(FUNC(namcos1_state::dac_gain_w));
NAMCO_C117(config, m_c117, 0);
diff --git a/src/mame/namco/warpwarp.cpp b/src/mame/namco/warpwarp.cpp
index 9a2748a2834..356ca0ad64a 100644
--- a/src/mame/namco/warpwarp.cpp
+++ b/src/mame/namco/warpwarp.cpp
@@ -932,11 +932,11 @@ ROM_END
ROM_START( navarone )
ROM_REGION( 0x10000, "maincpu", 0 )
- ROM_LOAD( "navalone.p1", 0x0000, 0x0800, CRC(5a32016b) SHA1(d856d069eba470a81341de0bf47eca2a629a69a6) )
- ROM_LOAD( "navalone.p2", 0x0800, 0x0800, CRC(b1c86fe3) SHA1(0293b742806c1517cb126443701115a3427fc60a) )
+ ROM_LOAD( "navarone.p1", 0x0000, 0x0800, CRC(5a32016b) SHA1(d856d069eba470a81341de0bf47eca2a629a69a6) )
+ ROM_LOAD( "navarone.p2", 0x0800, 0x0800, CRC(b1c86fe3) SHA1(0293b742806c1517cb126443701115a3427fc60a) )
ROM_REGION( 0x800, "gfx1", 0 )
- ROM_LOAD( "navalone.chr", 0x0000, 0x0800, CRC(b26c6170) SHA1(ae0aec2b60e1fd3b212e311afb1c588b2b286433) )
+ ROM_LOAD( "navarone.chr", 0x0000, 0x0800, CRC(b26c6170) SHA1(ae0aec2b60e1fd3b212e311afb1c588b2b286433) )
ROM_END
ROM_START( kaitein )
diff --git a/src/mame/pc/calchase.cpp b/src/mame/pc/calchase.cpp
index 8133328c761..b8e0cb5506b 100644
--- a/src/mame/pc/calchase.cpp
+++ b/src/mame/pc/calchase.cpp
@@ -90,15 +90,15 @@ there is a CD-ROM drive.
/*
Grull Osgo - Improvements
--Changes about BIOS memory management so ROM Shadow now works properly.
- The changes are:
- Rom Memory Map remmapped to 128K size map(0xfffe0000, 0xffffffff).rom().region("bios", 0);
+- Changes about BIOS memory management so ROM Shadow now works properly.
+ The changes are:
+ Rom Memory Map remmapped to 128K size map(0xfffe0000, 0xffffffff).rom().region("bios", 0);
--Changes in mtxc write handler and bios_ram write handler. Now The internal register access are
-compatible with chipset VIA.
- (this motherboard has VIA Apollo VXPro chipset. It is not compatible with Intel i430).
- With this changes now BIOS Shadow ram works fine, BIOS can relocate and decompress the full code
- necesary to run the Extended BIOS, POST and Boot). No more BIOS Checksum error.
+- Changes in mtxc write handler and bios_ram write handler. Now The internal register access are
+ compatible with chipset VIA.
+ (this motherboard has VIA Apollo VXPro chipset. It is not compatible with Intel i430).
+ With this changes now BIOS Shadow ram works fine, BIOS can relocate and decompress the full code
+ necessary to run the Extended BIOS, POST and Boot). No more BIOS Checksum error.
- Suppressed all video related items wich will be replaced with VGA driver.
@@ -111,13 +111,13 @@ compatible with chipset VIA.
- Minor changes and NOPS into address maps for debugging purposes.
- Now BIOS is looking for the disk (BIOS Auto detection). It seems all works fine but must be there
-something wrong in the disk geometry reported by calchase.chd (20,255,63) since BIOS does not accept
- 255 heads as parameter. Perhaps a bad dump?
+ something wrong in the disk geometry reported by calchase.chd (20,255,63) since BIOS does not accept
+ 255 heads as parameter. Perhaps a bad dump?
- update by peter ferrie:
- corrected memory map to 64kb blocks
- corrected access to PAM register
- */
+*/
#include "emu.h"
diff --git a/src/mame/shared/xbox_usb.h b/src/mame/shared/xbox_usb.h
index 571ef9f04c5..ca65121243e 100644
--- a/src/mame/shared/xbox_usb.h
+++ b/src/mame/shared/xbox_usb.h
@@ -392,8 +392,6 @@ private:
emu_timer *timer = nullptr;
int state = 0;
uint32_t framenumber = 0;
- uint32_t nextinterupted = 0;
- uint32_t nextbulked = 0;
int interruptbulkratio = 0;
int writebackdonehadcounter = 0;
address_space *space = nullptr;