diff options
author | 2008-06-05 17:21:35 +0000 | |
---|---|---|
committer | 2008-06-05 17:21:35 +0000 | |
commit | cf4b81fba9a8cf43b623e69733986accd388f5a9 (patch) | |
tree | 95dece24e682a03e9ba00d0a8550fe8299c80d1c | |
parent | 1bc774b32b7bc31fa4e0536e2d882c2589819e59 (diff) |
Separated condflags into two individual fields.
-rw-r--r-- | src/emu/cpu/drcbec.c | 12 | ||||
-rw-r--r-- | src/emu/cpu/drcbex64.c | 506 | ||||
-rw-r--r-- | src/emu/cpu/drcbex86.c | 592 | ||||
-rw-r--r-- | src/emu/cpu/drcuml.c | 219 | ||||
-rw-r--r-- | src/emu/cpu/drcuml.h | 13 | ||||
-rw-r--r-- | src/emu/cpu/drcumld.c | 16 | ||||
-rw-r--r-- | src/emu/cpu/drcumlsh.h | 370 |
7 files changed, 950 insertions, 778 deletions
diff --git a/src/emu/cpu/drcbec.c b/src/emu/cpu/drcbec.c index 925b42d2d98..c05cf280121 100644 --- a/src/emu/cpu/drcbec.c +++ b/src/emu/cpu/drcbec.c @@ -114,12 +114,12 @@ enum */ /* build a short opcode from the raw opcode and size */ -#define MAKE_OPCODE_SHORT(op, size, condflags) \ - ((((size) == 8) << 0) | (((condflags) != 0) << 1) | ((op) << 2)) +#define MAKE_OPCODE_SHORT(op, size, conditionorflags) \ + ((((size) == 8) << 0) | (((conditionorflags) != 0) << 1) | ((op) << 2)) /* build a full opcode from the raw opcode, size, condition/flags, and immediate count */ -#define MAKE_OPCODE_FULL(op, size, condflags, pwords) \ - (MAKE_OPCODE_SHORT(op, size, condflags) | ((condflags & 0x80) ? (0x1000 << ((condflags) & 15)) : 0) | ((pwords) << 28)) +#define MAKE_OPCODE_FULL(op, size, condition, flags, pwords) \ + (MAKE_OPCODE_SHORT(op, size, (condition | flags)) | ((condition != DRCUML_COND_ALWAYS) ? (0x1000 << ((condition) & 15)) : 0) | ((pwords) << 28)) /* extract various parts of the opcode */ #define OPCODE_GET_SHORT(op) ((op) & 0xfff) @@ -431,7 +431,7 @@ static void drcbec_generate(drcbe_state *drcbe, drcuml_block *block, const drcum case DRCUML_OP_JMP: assert(inst->numparams == 1); assert(inst->param[0].type == DRCUML_PTYPE_IMMEDIATE); - (dst++)->i = MAKE_OPCODE_FULL(opcode, inst->size, inst->condflags, 1); + (dst++)->i = MAKE_OPCODE_FULL(opcode, inst->size, inst->condition, inst->flags, 1); dst->inst = (drcbec_instruction *)drclabel_get_codeptr(drcbe->labels, inst->param[0].value, fixup_label, dst); dst++; break; @@ -501,7 +501,7 @@ static void drcbec_generate(drcbe_state *drcbe, drcuml_block *block, const drcum immedwords = (immedbytes + sizeof(drcbec_instruction) - 1) / sizeof(drcbec_instruction); /* first item is the opcode, size, condition flags and length */ - (dst++)->i = MAKE_OPCODE_FULL(opcode, inst->size, inst->condflags, inst->numparams + immedwords); + (dst++)->i = MAKE_OPCODE_FULL(opcode, inst->size, inst->condition, inst->flags, inst->numparams + immedwords); /* immediates start after parameters */ immed = dst + inst->numparams; diff --git a/src/emu/cpu/drcbex64.c b/src/emu/cpu/drcbex64.c index 85ba1d12d45..78034ed9683 100644 --- a/src/emu/cpu/drcbex64.c +++ b/src/emu/cpu/drcbex64.c @@ -222,12 +222,17 @@ MACROS ***************************************************************************/ -#define X86_CONDITION(condflags) (condition_map[condflags - DRCUML_COND_Z]) -#define X86_NOT_CONDITION(condflags) (condition_map[condflags - DRCUML_COND_Z] ^ 1) +#define X86_CONDITION(condition) (condition_map[condition - DRCUML_COND_Z]) +#define X86_NOT_CONDITION(condition) (condition_map[condition - DRCUML_COND_Z] ^ 1) #undef MABS #define MABS(drcbe, ptr) MBD(REG_RBP, offset_from_rbp(drcbe, (FPTR)(ptr))) +#define assert_no_condition(inst) assert((inst)->condition == DRCUML_COND_ALWAYS) +#define assert_any_condition(inst) assert((inst)->condition == DRCUML_COND_ALWAYS || ((inst)->condition >= DRCUML_COND_Z && (inst)->condition < DRCUML_COND_MAX)) +#define assert_no_flags(inst) assert((inst)->flags == 0) +#define assert_flags(inst, valid) assert(((inst)->flags & ~(valid)) == 0) + /*************************************************************************** @@ -1281,7 +1286,7 @@ static void emit_add_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_add_r32_imm(dst, reg, param->value); // add reg,param } else if (param->type == DRCUML_PTYPE_MEMORY) @@ -1300,7 +1305,7 @@ static void emit_add_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_add_m32_imm(dst, MEMPARAMS, param->value); // add [dest],param } else @@ -1321,7 +1326,7 @@ static void emit_adc_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_adc_r32_imm(dst, reg, param->value); // adc reg,param } else if (param->type == DRCUML_PTYPE_MEMORY) @@ -1340,7 +1345,7 @@ static void emit_adc_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_adc_m32_imm(dst, MEMPARAMS, param->value); // adc [dest],param } else @@ -1361,7 +1366,7 @@ static void emit_sub_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_sub_r32_imm(dst, reg, param->value); // sub reg,param } else if (param->type == DRCUML_PTYPE_MEMORY) @@ -1380,7 +1385,7 @@ static void emit_sub_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_sub_m32_imm(dst, MEMPARAMS, param->value); // sub [dest],param } else @@ -1401,7 +1406,7 @@ static void emit_sbb_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_sbb_r32_imm(dst, reg, param->value); // sbb reg,param } else if (param->type == DRCUML_PTYPE_MEMORY) @@ -1420,7 +1425,7 @@ static void emit_sbb_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_sbb_m32_imm(dst, MEMPARAMS, param->value); // sbb [dest],param } else @@ -1475,9 +1480,9 @@ static void emit_and_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0xffffffff) + if (inst->flags == 0 && (UINT32)param->value == 0xffffffff) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0) + else if (inst->flags != 0 && (UINT32)param->value == 0) emit_xor_r32_r32(dst, reg, reg); // xor reg,reg else emit_and_r32_imm(dst, reg, param->value); // and reg,param @@ -1498,9 +1503,9 @@ static void emit_and_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0xffffffff) + if (inst->flags == 0 && (UINT32)param->value == 0xffffffff) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0) + else if (inst->flags != 0 && (UINT32)param->value == 0) emit_mov_m32_imm(dst, MEMPARAMS, 0); // mov [dest],0 else emit_and_m32_imm(dst, MEMPARAMS, param->value); // and [dest],param @@ -1558,9 +1563,9 @@ static void emit_or_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags != 0 && (UINT32)param->value == 0xffffffff) emit_mov_r32_imm(dst, reg, -1); // mov reg,-1 else emit_or_r32_imm(dst, reg, param->value); // or reg,param @@ -1581,9 +1586,9 @@ static void emit_or_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags != 0 && (UINT32)param->value == 0xffffffff) emit_mov_m32_imm(dst, MEMPARAMS, -1); // mov [dest],-1 else emit_or_m32_imm(dst, MEMPARAMS, param->value); // or [dest],param @@ -1606,9 +1611,9 @@ static void emit_xor_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags != 0 && (UINT32)param->value == 0xffffffff) emit_not_r32(dst, reg); // not reg else emit_xor_r32_imm(dst, reg, param->value); // xor reg,param @@ -1629,9 +1634,9 @@ static void emit_xor_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags != 0 && (UINT32)param->value == 0xffffffff) emit_not_m32(dst, MEMPARAMS); // not [dest] else emit_xor_m32_imm(dst, MEMPARAMS, param->value); // xor [dest],param @@ -1654,7 +1659,7 @@ static void emit_shl_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_shl_r32_imm(dst, reg, param->value); // shl reg,param @@ -1676,7 +1681,7 @@ static void emit_shl_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_shl_m32_imm(dst, MEMPARAMS, param->value); // shl [dest],param @@ -1698,7 +1703,7 @@ static void emit_shr_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_shr_r32_imm(dst, reg, param->value); // shr reg,param @@ -1720,7 +1725,7 @@ static void emit_shr_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_shr_m32_imm(dst, MEMPARAMS, param->value); // shr [dest],param @@ -1742,7 +1747,7 @@ static void emit_sar_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_sar_r32_imm(dst, reg, param->value); // sar reg,param @@ -1764,7 +1769,7 @@ static void emit_sar_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_sar_m32_imm(dst, MEMPARAMS, param->value); // sar [dest],param @@ -1786,7 +1791,7 @@ static void emit_rol_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rol_r32_imm(dst, reg, param->value); // rol reg,param @@ -1808,7 +1813,7 @@ static void emit_rol_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rol_m32_imm(dst, MEMPARAMS, param->value); // rol [dest],param @@ -1830,7 +1835,7 @@ static void emit_ror_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_ror_r32_imm(dst, reg, param->value); // ror reg,param @@ -1852,7 +1857,7 @@ static void emit_ror_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_ror_m32_imm(dst, MEMPARAMS, param->value); // ror [dest],param @@ -1874,7 +1879,7 @@ static void emit_rcl_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rcl_r32_imm(dst, reg, param->value); // rcl reg,param @@ -1896,7 +1901,7 @@ static void emit_rcl_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rcl_m32_imm(dst, MEMPARAMS, param->value); // rcl [dest],param @@ -1918,7 +1923,7 @@ static void emit_rcr_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rcr_r32_imm(dst, reg, param->value); // rcr reg,param @@ -1940,7 +1945,7 @@ static void emit_rcr_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rcr_m32_imm(dst, MEMPARAMS, param->value); // rcr [dest],param @@ -2009,7 +2014,7 @@ static void emit_add_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) { if (short_immediate(param->value)) emit_add_r64_imm(dst, reg, param->value); // add reg,param @@ -2036,7 +2041,7 @@ static void emit_add_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) { if (short_immediate(param->value)) emit_add_m64_imm(dst, MEMPARAMS, param->value); // add [mem],param @@ -2107,7 +2112,7 @@ static void emit_sub_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) { if (short_immediate(param->value)) emit_sub_r64_imm(dst, reg, param->value); // sub reg,param @@ -2134,7 +2139,7 @@ static void emit_sub_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) { if (short_immediate(param->value)) emit_sub_m64_imm(dst, MEMPARAMS, param->value); // sub [mem],param @@ -2247,7 +2252,7 @@ static void emit_and_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != U64(0xffffffffffffffff)) + if (inst->flags != 0 || param->value != U64(0xffffffffffffffff)) { if (short_immediate(param->value)) emit_and_r64_imm(dst, reg, param->value); // and reg,param @@ -2274,7 +2279,7 @@ static void emit_and_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != U64(0xffffffffffffffff)) + if (inst->flags != 0 || param->value != U64(0xffffffffffffffff)) { if (short_immediate(param->value)) emit_and_m64_imm(dst, MEMPARAMS, param->value); // and [mem],param @@ -2346,7 +2351,7 @@ static void emit_or_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) { if (short_immediate(param->value)) emit_or_r64_imm(dst, reg, param->value); // or reg,param @@ -2373,7 +2378,7 @@ static void emit_or_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) { if (short_immediate(param->value)) emit_or_m64_imm(dst, MEMPARAMS, param->value); // or [mem],param @@ -2402,7 +2407,7 @@ static void emit_xor_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) { if (param->value == U64(0xffffffffffffffff)) emit_not_r64(dst, reg); // not reg @@ -2431,7 +2436,7 @@ static void emit_xor_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) { if (param->value == U64(0xffffffffffffffff)) emit_not_m64(dst, MEMPARAMS); // not [mem] @@ -2462,7 +2467,7 @@ static void emit_shl_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_shl_r64_imm(dst, reg, param->value); // shl reg,param @@ -2484,7 +2489,7 @@ static void emit_shl_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT64)param->value == 0) + if (inst->flags == 0 && (UINT64)param->value == 0) /* skip */; else emit_shl_m64_imm(dst, MEMPARAMS, param->value); // shl [dest],param @@ -2506,7 +2511,7 @@ static void emit_shr_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_shr_r64_imm(dst, reg, param->value); // shr reg,param @@ -2528,7 +2533,7 @@ static void emit_shr_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT64)param->value == 0) + if (inst->flags == 0 && (UINT64)param->value == 0) /* skip */; else emit_shr_m64_imm(dst, MEMPARAMS, param->value); // shr [dest],param @@ -2550,7 +2555,7 @@ static void emit_sar_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_sar_r64_imm(dst, reg, param->value); // sar reg,param @@ -2572,7 +2577,7 @@ static void emit_sar_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT64)param->value == 0) + if (inst->flags == 0 && (UINT64)param->value == 0) /* skip */; else emit_sar_m64_imm(dst, MEMPARAMS, param->value); // sar [dest],param @@ -2594,7 +2599,7 @@ static void emit_rol_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rol_r64_imm(dst, reg, param->value); // rol reg,param @@ -2616,7 +2621,7 @@ static void emit_rol_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT64)param->value == 0) + if (inst->flags == 0 && (UINT64)param->value == 0) /* skip */; else emit_rol_m64_imm(dst, MEMPARAMS, param->value); // rol [dest],param @@ -2638,7 +2643,7 @@ static void emit_ror_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_ror_r64_imm(dst, reg, param->value); // ror reg,param @@ -2660,7 +2665,7 @@ static void emit_ror_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT64)param->value == 0) + if (inst->flags == 0 && (UINT64)param->value == 0) /* skip */; else emit_ror_m64_imm(dst, MEMPARAMS, param->value); // ror [dest],param @@ -2682,7 +2687,7 @@ static void emit_rcl_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rcl_r64_imm(dst, reg, param->value); // rcl reg,param @@ -2704,7 +2709,7 @@ static void emit_rcl_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT64)param->value == 0) + if (inst->flags == 0 && (UINT64)param->value == 0) /* skip */; else emit_rcl_m64_imm(dst, MEMPARAMS, param->value); // rcl [dest],param @@ -2726,7 +2731,7 @@ static void emit_rcr_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rcr_r64_imm(dst, reg, param->value); // rcr reg,param @@ -2748,7 +2753,7 @@ static void emit_rcr_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT64)param->value == 0) + if (inst->flags == 0 && (UINT64)param->value == 0) /* skip */; else emit_rcr_m64_imm(dst, MEMPARAMS, param->value); // rcr [dest],param @@ -2976,6 +2981,8 @@ static void debug_log_hashjmp(int mode, offs_t pc) static x86code *op_handle(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + assert_no_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 1); assert(inst->param[0].type == DRCUML_PTYPE_MEMORY); @@ -2994,6 +3001,8 @@ static x86code *op_handle(drcbe_state *drcbe, x86code *dst, const drcuml_instruc static x86code *op_hash(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + assert_no_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 2); assert(inst->param[0].type == DRCUML_PTYPE_IMMEDIATE); assert(inst->param[1].type == DRCUML_PTYPE_IMMEDIATE); @@ -3010,6 +3019,8 @@ static x86code *op_hash(drcbe_state *drcbe, x86code *dst, const drcuml_instructi static x86code *op_label(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + assert_no_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 1); assert(inst->param[0].type == DRCUML_PTYPE_IMMEDIATE); @@ -3025,6 +3036,8 @@ static x86code *op_label(drcbe_state *drcbe, x86code *dst, const drcuml_instruct static x86code *op_comment(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + assert_no_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 1); assert(inst->param[0].type == DRCUML_PTYPE_MEMORY); @@ -3039,6 +3052,8 @@ static x86code *op_comment(drcbe_state *drcbe, x86code *dst, const drcuml_instru static x86code *op_mapvar(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + assert_no_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 2); assert(inst->param[0].type == DRCUML_PTYPE_MAPVAR); assert(inst->param[1].type == DRCUML_PTYPE_IMMEDIATE); @@ -3060,15 +3075,16 @@ static x86code *op_mapvar(drcbe_state *drcbe, x86code *dst, const drcuml_instruc static x86code *op_debug(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + /* validate instruction */ + assert(inst->size == 4); + assert_no_condition(inst); + assert_no_flags(inst); + #ifdef ENABLE_DEBUGGER if (Machine->debug_mode) { drcuml_parameter pcp; - /* validate instruction */ - assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); - /* normalize parameters */ param_normalize_1(drcbe, inst, &pcp, PTYPE_MRI); @@ -3092,17 +3108,18 @@ static x86code *op_exit(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &retp, PTYPE_MRI); /* load the parameter into EAX */ emit_mov_r32_p32(drcbe, &dst, REG_EAX, &retp); // mov eax,retp - if (inst->condflags == DRCUML_COND_ALWAYS) + if (inst->condition == DRCUML_COND_ALWAYS) emit_jmp(&dst, drcbe->exit); // jmp exit else - emit_jcc(&dst, X86_CONDITION(inst->condflags), drcbe->exit); // jcc exit + emit_jcc(&dst, X86_CONDITION(inst->condition), drcbe->exit); // jcc exit return dst; } @@ -3118,7 +3135,8 @@ static x86code *op_hashjmp(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &modep, PTYPE_MRI, &pcp, PTYPE_MRI, &exp, PTYPE_M); @@ -3205,7 +3223,8 @@ static x86code *op_jmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &labelp, PTYPE_I); @@ -3214,10 +3233,10 @@ static x86code *op_jmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructio jmptarget = (x86code *)drclabel_get_codeptr(drcbe->labels, labelp.value, fixup_label, dst); if (jmptarget == NULL) jmptarget = dst + 0x7ffffff0; - if (inst->condflags == DRCUML_COND_ALWAYS) + if (inst->condition == DRCUML_COND_ALWAYS) emit_jmp(&dst, jmptarget); // jmp target else - emit_jcc(&dst, X86_CONDITION(inst->condflags), jmptarget); // jcc target + emit_jcc(&dst, X86_CONDITION(inst->condition), jmptarget); // jcc target return dst; } @@ -3234,7 +3253,8 @@ static x86code *op_exh(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &handp, PTYPE_M, &exp, PTYPE_MRI); @@ -3243,7 +3263,7 @@ static x86code *op_exh(drcbe_state *drcbe, x86code *dst, const drcuml_instructio targetptr = drcuml_handle_codeptr_addr((drcuml_codehandle *)handp.value); /* perform the exception processing inline if unconditional */ - if (inst->condflags == DRCUML_COND_ALWAYS) + if (inst->condition == DRCUML_COND_ALWAYS) { emit_mov_m32_p32(drcbe, &dst, MABS(drcbe, &drcbe->state.exp), &exp); // mov [exp],exp if (*targetptr != NULL) @@ -3255,7 +3275,7 @@ static x86code *op_exh(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* otherwise, jump to an out-of-band handler */ else { - emit_jcc(&dst, X86_CONDITION(inst->condflags), dst + 0x7ffffff0); // jcc exception + emit_jcc(&dst, X86_CONDITION(inst->condition), dst + 0x7ffffff0); // jcc exception drccache_request_oob_codegen(drcbe->cache, fixup_exception, drcbe, dst, (void *)inst); } return dst; @@ -3274,7 +3294,8 @@ static x86code *op_callh(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &handp, PTYPE_M); @@ -3283,8 +3304,8 @@ static x86code *op_callh(drcbe_state *drcbe, x86code *dst, const drcuml_instruct targetptr = drcuml_handle_codeptr_addr((drcuml_codehandle *)handp.value); /* skip if conditional */ - if (inst->condflags != DRCUML_COND_ALWAYS) - emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip + if (inst->condition != DRCUML_COND_ALWAYS) + emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condition), &skip); // jcc skip /* jump through the handle; directly if a normal jump */ if (*targetptr != NULL) @@ -3293,7 +3314,7 @@ static x86code *op_callh(drcbe_state *drcbe, x86code *dst, const drcuml_instruct emit_call_m64(&dst, MABS(drcbe, targetptr)); // call [targetptr] /* resolve the conditional link */ - if (inst->condflags != DRCUML_COND_ALWAYS) + if (inst->condition != DRCUML_COND_ALWAYS) resolve_link(&dst, &skip); // skip: return dst; } @@ -3309,19 +3330,20 @@ static x86code *op_ret(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 0); /* skip if conditional */ - if (inst->condflags != DRCUML_COND_ALWAYS) - emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip + if (inst->condition != DRCUML_COND_ALWAYS) + emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condition), &skip); // jcc skip /* return */ emit_lea_r64_m64(&dst, REG_RSP, MBD(REG_RSP, 40)); // lea rsp,[rsp+40] emit_ret(&dst); // ret /* resolve the conditional link */ - if (inst->condflags != DRCUML_COND_ALWAYS) + if (inst->condition != DRCUML_COND_ALWAYS) resolve_link(&dst, &skip); // skip: return dst; } @@ -3338,21 +3360,22 @@ static x86code *op_callc(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &funcp, PTYPE_M, ¶mp, PTYPE_M); /* skip if conditional */ - if (inst->condflags != DRCUML_COND_ALWAYS) - emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip + if (inst->condition != DRCUML_COND_ALWAYS) + emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condition), &skip); // jcc skip /* perform the call */ emit_mov_r64_imm(&dst, REG_PARAM1, paramp.value); // mov param1,paramp emit_smart_call_r64(drcbe, &dst, (x86code *)(FPTR)funcp.value, REG_RAX); // call funcp /* resolve the conditional link */ - if (inst->condflags != DRCUML_COND_ALWAYS) + if (inst->condition != DRCUML_COND_ALWAYS) resolve_link(&dst, &skip); // skip: return dst; } @@ -3368,7 +3391,8 @@ static x86code *op_recover(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &mvparam, PTYPE_I); @@ -3401,7 +3425,8 @@ static x86code *op_setfmod(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &srcp, PTYPE_MRI); @@ -3438,7 +3463,8 @@ static x86code *op_getfmod(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_MR); @@ -3466,7 +3492,8 @@ static x86code *op_getexp(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_MR); @@ -3495,7 +3522,8 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags != DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert(inst->flags != 0); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_MR); @@ -3503,7 +3531,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* pick a target register for the general case */ dstreg = param_select_register(REG_EAX, &dstp, NULL); - switch (inst->condflags) + switch (inst->flags) { /* single flags only */ case DRCUML_FLAG_C: @@ -3622,7 +3650,8 @@ static x86code *op_save(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_M); @@ -3683,7 +3712,8 @@ static x86code *op_restore(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_M); @@ -3750,7 +3780,8 @@ static x86code *op_load(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &basep, PTYPE_M, &indp, PTYPE_MRI, &sizep, PTYPE_I); @@ -3811,7 +3842,8 @@ static x86code *op_loads(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &basep, PTYPE_M, &indp, PTYPE_MRI, &sizep, PTYPE_I); @@ -3896,7 +3928,8 @@ static x86code *op_store(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &basep, PTYPE_M, &indp, PTYPE_MRI, &srcp, PTYPE_MRI, &sizep, PTYPE_I); @@ -4010,7 +4043,8 @@ static x86code *op_read(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &addrp, PTYPE_MRI, &spacesizep, PTYPE_I); @@ -4068,7 +4102,8 @@ static x86code *op_readm(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &addrp, PTYPE_MRI, &maskp, PTYPE_MRI, &spacesizep, PTYPE_I); @@ -4123,7 +4158,8 @@ static x86code *op_write(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &addrp, PTYPE_MRI, &srcp, PTYPE_MRI, &spacesizep, PTYPE_I); @@ -4160,7 +4196,8 @@ static x86code *op_writem(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &addrp, PTYPE_MRI, &srcp, PTYPE_MRI, &maskp, PTYPE_MRI, &spacesizep, PTYPE_I); @@ -4200,7 +4237,8 @@ static x86code *op_carry(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &srcp, PTYPE_MRI, &bitp, PTYPE_MRI); @@ -4274,7 +4312,8 @@ static x86code *op_set(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags >= DRCUML_COND_Z && inst->condflags < DRCUML_COND_MAX); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_MR); @@ -4283,7 +4322,7 @@ static x86code *op_set(drcbe_state *drcbe, x86code *dst, const drcuml_instructio dstreg = param_select_register(REG_EAX, &dstp, NULL); /* set to AL */ - emit_setcc_r8(&dst, X86_CONDITION(inst->condflags), REG_AL); // setcc al + emit_setcc_r8(&dst, X86_CONDITION(inst->condition), REG_AL); // setcc al emit_movzx_r32_r8(&dst, dstreg, REG_AL); // movzx dstreg,al /* 32-bit form */ @@ -4311,7 +4350,8 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters, but only if we got here directly */ /* other opcodes call through here with pre-normalized parameters */ @@ -4331,8 +4371,8 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio dstreg = param_select_register(REG_EAX, &dstp, NULL); /* always start with a jmp */ - if (inst->condflags != DRCUML_COND_ALWAYS) - emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip + if (inst->condition != DRCUML_COND_ALWAYS) + emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condition), &skip); // jcc skip /* 32-bit form */ if (inst->size == 4) @@ -4346,20 +4386,20 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio emit_mov_m32_imm(&dst, MABS(drcbe, dstp.value), srcp.value); // mov [dstp],srcp /* conditional memory to register */ - else if (inst->condflags != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_MEMORY) + else if (inst->condition != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_MEMORY) { dst = savedst; skip.target = NULL; - emit_cmovcc_r32_m32(&dst, X86_CONDITION(inst->condflags), dstp.value, MABS(drcbe, srcp.value)); + emit_cmovcc_r32_m32(&dst, X86_CONDITION(inst->condition), dstp.value, MABS(drcbe, srcp.value)); // cmovcc dstp,[srcp] } /* conditional register to register */ - else if (inst->condflags != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_INT_REGISTER) + else if (inst->condition != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_INT_REGISTER) { dst = savedst; skip.target = NULL; - emit_cmovcc_r32_r32(&dst, X86_CONDITION(inst->condflags), dstp.value, srcp.value); + emit_cmovcc_r32_r32(&dst, X86_CONDITION(inst->condition), dstp.value, srcp.value); // cmovcc dstp,srcp } @@ -4383,20 +4423,20 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio emit_mov_m64_imm(&dst, MABS(drcbe, dstp.value), srcp.value); // mov [dstp],srcp /* conditional memory to register */ - else if (inst->condflags != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_MEMORY) + else if (inst->condition != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_MEMORY) { dst = savedst; skip.target = NULL; - emit_cmovcc_r64_m64(&dst, X86_CONDITION(inst->condflags), dstp.value, MABS(drcbe, srcp.value)); + emit_cmovcc_r64_m64(&dst, X86_CONDITION(inst->condition), dstp.value, MABS(drcbe, srcp.value)); // cmovcc dstp,[srcp] } /* conditional register to register */ - else if (inst->condflags != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_INT_REGISTER) + else if (inst->condition != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_INT_REGISTER) { dst = savedst; skip.target = NULL; - emit_cmovcc_r64_r64(&dst, X86_CONDITION(inst->condflags), dstp.value, srcp.value); + emit_cmovcc_r64_r64(&dst, X86_CONDITION(inst->condition), dstp.value, srcp.value); // cmovcc dstp,srcp } @@ -4426,7 +4466,8 @@ static x86code *op_sext(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI, &sizep, PTYPE_I); @@ -4513,7 +4554,8 @@ static x86code *op_roland(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI, &shiftp, PTYPE_MRI, &maskp, PTYPE_MRI); @@ -4578,7 +4620,8 @@ static x86code *op_rolins(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI, &shiftp, PTYPE_MRI, &maskp, PTYPE_MRI); @@ -4636,15 +4679,16 @@ static x86code *op_add(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value + src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -4658,11 +4702,11 @@ static x86code *op_add(drcbe_state *drcbe, x86code *dst, const drcuml_instructio emit_add_m32_p32(drcbe, &dst, MABS(drcbe, dstp.value), &src2p, inst); // add [dstp],src2p /* reg = reg + imm */ - else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) emit_lea_r32_m32(&dst, dstp.value, MBD(src1p.value, src2p.value)); // lea dstp,[src1p+src2p] /* reg = reg + reg */ - else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_INT_REGISTER && inst->condflags == 0) + else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_INT_REGISTER && inst->flags == 0) emit_lea_r32_m32(&dst, dstp.value, MBISD(src1p.value, src2p.value, 1, 0)); // lea dstp,[src1p+src2p] /* general case */ @@ -4682,11 +4726,11 @@ static x86code *op_add(drcbe_state *drcbe, x86code *dst, const drcuml_instructio emit_add_m64_p64(drcbe, &dst, MABS(drcbe, dstp.value), &src2p, inst); // add [dstp],src2p /* reg = reg + imm */ - else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && short_immediate(src2p.value) && inst->condflags == 0) + else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && short_immediate(src2p.value) && inst->flags == 0) emit_lea_r64_m64(&dst, dstp.value, MBD(src1p.value, src2p.value)); // lea dstp,[src1p+src2p] /* reg = reg + reg */ - else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_INT_REGISTER && inst->condflags == 0) + else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_INT_REGISTER && inst->flags == 0) emit_lea_r64_m64(&dst, dstp.value, MBISD(src1p.value, src2p.value, 1, 0)); // lea dstp,[src1p+src2p] /* general case */ @@ -4712,7 +4756,8 @@ static x86code *op_addc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); @@ -4766,15 +4811,16 @@ static x86code *op_sub(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value - src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -4788,7 +4834,7 @@ static x86code *op_sub(drcbe_state *drcbe, x86code *dst, const drcuml_instructio emit_sub_m32_p32(drcbe, &dst, MABS(drcbe, dstp.value), &src2p, inst); // sub [dstp],src2p /* reg = reg - imm */ - else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) emit_lea_r32_m32(&dst, dstp.value, MBD(src1p.value, -src2p.value)); // lea dstp,[src1p-src2p] /* general case */ @@ -4808,7 +4854,7 @@ static x86code *op_sub(drcbe_state *drcbe, x86code *dst, const drcuml_instructio emit_sub_m64_p64(drcbe, &dst, MABS(drcbe, dstp.value), &src2p, inst); // sub [dstp],src2p /* reg = reg - imm */ - else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && short_immediate(src2p.type) && inst->condflags == 0) + else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && short_immediate(src2p.type) && inst->flags == 0) emit_lea_r64_m64(&dst, dstp.value, MBD(src1p.value, -src2p.value)); // lea dstp,[src1p-src2p] /* general case */ @@ -4834,7 +4880,8 @@ static x86code *op_subc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); @@ -4888,7 +4935,8 @@ static x86code *op_cmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_2(drcbe, inst, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); @@ -4949,14 +4997,15 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_V |*/ DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_4_commutative(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); compute_hi = (dstp.type != edstp.type || dstp.value != edstp.value); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) { @@ -4990,13 +5039,13 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx /* compute flags */ - if (inst->condflags != 0) + if (inst->flags != 0) { if (compute_hi) { - if (inst->condflags == DRCUML_FLAG_Z) + if (inst->flags == DRCUML_FLAG_Z) emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax - else if (inst->condflags == DRCUML_FLAG_S) + else if (inst->flags == DRCUML_FLAG_S) emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx else { @@ -5030,13 +5079,13 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi emit_mov_p64_r64(drcbe, &dst, &edstp, REG_RDX); // mov edstp,rdx /* compute flags */ - if (inst->condflags != 0) + if (inst->flags != 0) { if (compute_hi) { - if (inst->condflags == DRCUML_FLAG_Z) + if (inst->flags == DRCUML_FLAG_Z) emit_or_r64_r64(&dst, REG_RDX, REG_RAX); // or rdx,rax - else if (inst->condflags == DRCUML_FLAG_S) + else if (inst->flags == DRCUML_FLAG_S) emit_test_r64_r64(&dst, REG_RDX, REG_RDX); // test rdx,rdx else { @@ -5065,14 +5114,15 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_V |*/ DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_4_commutative(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); compute_hi = (dstp.type != edstp.type || dstp.value != edstp.value); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) { @@ -5129,13 +5179,13 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi } /* compute flags */ - if (inst->condflags != 0) + if (inst->flags != 0) { if (compute_hi) { - if (inst->condflags == DRCUML_FLAG_Z) + if (inst->flags == DRCUML_FLAG_Z) emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax - else if (inst->condflags == DRCUML_FLAG_S) + else if (inst->flags == DRCUML_FLAG_S) emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx else { @@ -5192,13 +5242,13 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi } /* compute flags */ - if (inst->condflags != 0) + if (inst->flags != 0) { if (compute_hi) { - if (inst->condflags == DRCUML_FLAG_Z) + if (inst->flags == DRCUML_FLAG_Z) emit_or_r64_r64(&dst, REG_RDX, REG_RAX); // or rdx,rax - else if (inst->condflags == DRCUML_FLAG_S) + else if (inst->flags == DRCUML_FLAG_S) emit_test_r64_r64(&dst, REG_RDX, REG_RDX); // test rdx,rdx else { @@ -5228,14 +5278,15 @@ static x86code *op_divu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_V |*/ DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); compute_rem = (dstp.type != edstp.type || dstp.value != edstp.value); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) { @@ -5314,14 +5365,15 @@ static x86code *op_divs(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_V |*/ DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); compute_rem = (dstp.type != edstp.type || dstp.value != edstp.value); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) { @@ -5399,15 +5451,16 @@ static x86code *op_and(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value & src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && (src2p.value & size_to_mask[inst->size]) == size_to_mask[inst->size] && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && (src2p.value & size_to_mask[inst->size]) == size_to_mask[inst->size] && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5459,7 +5512,8 @@ static x86code *op_test(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_2_commutative(drcbe, inst, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); @@ -5511,15 +5565,16 @@ static x86code *op_or(drcbe_state *drcbe, x86code *dst, const drcuml_instruction /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value | src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5571,15 +5626,16 @@ static x86code *op_xor(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value & src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5631,13 +5687,14 @@ static x86code *op_lzcnt(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_Z | DRCUML_FLAG_S*/0); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, count_leading_zeros(srcp.value)); /* pick a target register for the general case */ @@ -5677,13 +5734,14 @@ static x86code *op_bswap(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_Z | DRCUML_FLAG_S*/0); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) return convert_to_mov_imm(drcbe, dst, inst, &dstp, FLIPENDIAN_INT32(srcp.value)); @@ -5724,15 +5782,16 @@ static x86code *op_shl(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value << src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5784,15 +5843,16 @@ static x86code *op_shr(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5844,20 +5904,21 @@ static x86code *op_sar(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (INT32)src1p.value >> src2p.value); else if (inst->size == 8) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (INT64)src1p.value >> src2p.value); } - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5909,15 +5970,16 @@ static x86code *op_rol(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5969,15 +6031,16 @@ static x86code *op_ror(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -6029,15 +6092,16 @@ static x86code *op_rolc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -6089,15 +6153,16 @@ static x86code *op_rorc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -6155,7 +6220,8 @@ static x86code *op_fload(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &basep, PTYPE_M, &indp, PTYPE_MRI); @@ -6209,8 +6275,9 @@ static x86code *op_fstore(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); - + assert_no_condition(inst); + assert_no_flags(inst); + /* normalize parameters */ param_normalize_3(drcbe, inst, &basep, PTYPE_M, &indp, PTYPE_MRI, &srcp, PTYPE_MF); @@ -6261,7 +6328,8 @@ static x86code *op_fread(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &addrp, PTYPE_MRI, &spacep, PTYPE_I); @@ -6302,7 +6370,8 @@ static x86code *op_fwrite(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &addrp, PTYPE_MRI, &srcp, PTYPE_MF, &spacep, PTYPE_I); @@ -6346,7 +6415,8 @@ static x86code *op_fmov(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -6355,8 +6425,8 @@ static x86code *op_fmov(drcbe_state *drcbe, x86code *dst, const drcuml_instructi dstreg = param_select_register(REG_XMM0, &dstp, NULL); /* always start with a jmp */ - if (inst->condflags != DRCUML_COND_ALWAYS) - emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip + if (inst->condition != DRCUML_COND_ALWAYS) + emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condition), &skip); // jcc skip /* 32-bit form */ if (inst->size == 4) @@ -6373,7 +6443,7 @@ static x86code *op_fmov(drcbe_state *drcbe, x86code *dst, const drcuml_instructi } /* resolve the jump */ - if (inst->condflags != DRCUML_COND_ALWAYS) + if (inst->condition != DRCUML_COND_ALWAYS) resolve_link(&dst, &skip); // skip: return dst; } @@ -6390,7 +6460,8 @@ static x86code *op_ftoint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MF, &sizep, PTYPE_I, &roundp, PTYPE_I); @@ -6514,7 +6585,8 @@ static x86code *op_ffrint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MRI, &sizep, PTYPE_I); @@ -6598,7 +6670,8 @@ static x86code *op_ffrflt(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF, &sizep, PTYPE_I); @@ -6640,7 +6713,8 @@ static x86code *op_frnds(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -6670,7 +6744,8 @@ static x86code *op_fadd(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MF, &src1p, PTYPE_MF, &src2p, PTYPE_MF); @@ -6714,7 +6789,8 @@ static x86code *op_fsub(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &src1p, PTYPE_MF, &src2p, PTYPE_MF); @@ -6758,7 +6834,8 @@ static x86code *op_fcmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_U)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_U); /* normalize parameters */ param_normalize_2(drcbe, inst, &src1p, PTYPE_MF, &src2p, PTYPE_MF); @@ -6800,7 +6877,8 @@ static x86code *op_fmul(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MF, &src1p, PTYPE_MF, &src2p, PTYPE_MF); @@ -6844,7 +6922,8 @@ static x86code *op_fdiv(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &src1p, PTYPE_MF, &src2p, PTYPE_MF); @@ -6888,7 +6967,8 @@ static x86code *op_fneg(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -6932,7 +7012,8 @@ static x86code *op_fabs(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -6970,7 +7051,8 @@ static x86code *op_fsqrt(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -7012,7 +7094,8 @@ static x86code *op_frecip(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -7056,7 +7139,8 @@ static x86code *op_frsqrt(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); diff --git a/src/emu/cpu/drcbex86.c b/src/emu/cpu/drcbex86.c index 46a5a2489cf..e9cc6f97c13 100644 --- a/src/emu/cpu/drcbex86.c +++ b/src/emu/cpu/drcbex86.c @@ -116,8 +116,13 @@ MACROS ***************************************************************************/ -#define X86_CONDITION(condflags) (condition_map[condflags - DRCUML_COND_Z]) -#define X86_NOT_CONDITION(condflags) (condition_map[condflags - DRCUML_COND_Z] ^ 1) +#define X86_CONDITION(condition) (condition_map[condition - DRCUML_COND_Z]) +#define X86_NOT_CONDITION(condition) (condition_map[condition - DRCUML_COND_Z] ^ 1) + +#define assert_no_condition(inst) assert((inst)->condition == DRCUML_COND_ALWAYS) +#define assert_any_condition(inst) assert((inst)->condition == DRCUML_COND_ALWAYS || ((inst)->condition >= DRCUML_COND_Z && (inst)->condition < DRCUML_COND_MAX)) +#define assert_no_flags(inst) assert((inst)->flags == 0) +#define assert_flags(inst, valid) assert(((inst)->flags & ~(valid)) == 0) @@ -1093,7 +1098,7 @@ static void emit_add_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_add_r32_imm(dst, reg, param->value); // add reg,param } else if (param->type == DRCUML_PTYPE_MEMORY) @@ -1112,7 +1117,7 @@ static void emit_add_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_add_m32_imm(dst, MEMPARAMS, param->value); // add [dest],param } else @@ -1133,7 +1138,7 @@ static void emit_adc_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_adc_r32_imm(dst, reg, param->value); // adc reg,param } else if (param->type == DRCUML_PTYPE_MEMORY) @@ -1152,7 +1157,7 @@ static void emit_adc_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_adc_m32_imm(dst, MEMPARAMS, param->value); // adc [dest],param } else @@ -1173,7 +1178,7 @@ static void emit_sub_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_sub_r32_imm(dst, reg, param->value); // sub reg,param } else if (param->type == DRCUML_PTYPE_MEMORY) @@ -1192,7 +1197,7 @@ static void emit_sub_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_sub_m32_imm(dst, MEMPARAMS, param->value); // sub [dest],param } else @@ -1213,7 +1218,7 @@ static void emit_sbb_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_sbb_r32_imm(dst, reg, param->value); // sbb reg,param } else if (param->type == DRCUML_PTYPE_MEMORY) @@ -1232,7 +1237,7 @@ static void emit_sbb_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags != 0 || param->value != 0) + if (inst->flags != 0 || param->value != 0) emit_sbb_m32_imm(dst, MEMPARAMS, param->value); // sbb [dest],param } else @@ -1325,9 +1330,9 @@ static void emit_and_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0xffffffff) + if (inst->flags == 0 && (UINT32)param->value == 0xffffffff) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0) + else if (inst->flags != 0 && (UINT32)param->value == 0) emit_xor_r32_r32(dst, reg, reg); // xor reg,reg else emit_and_r32_imm(dst, reg, param->value); // and reg,param @@ -1348,9 +1353,9 @@ static void emit_and_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0xffffffff) + if (inst->flags == 0 && (UINT32)param->value == 0xffffffff) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0) + else if (inst->flags != 0 && (UINT32)param->value == 0) emit_mov_m32_imm(dst, MEMPARAMS, 0); // mov [dest],0 else emit_and_m32_imm(dst, MEMPARAMS, param->value); // and [dest],param @@ -1408,9 +1413,9 @@ static void emit_or_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags != 0 && (UINT32)param->value == 0xffffffff) emit_mov_r32_imm(dst, reg, -1); // mov reg,-1 else emit_or_r32_imm(dst, reg, param->value); // or reg,param @@ -1431,9 +1436,9 @@ static void emit_or_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags != 0 && (UINT32)param->value == 0xffffffff) emit_mov_m32_imm(dst, MEMPARAMS, -1); // mov [dest],-1 else emit_or_m32_imm(dst, MEMPARAMS, param->value); // or [dest],param @@ -1456,9 +1461,9 @@ static void emit_xor_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags != 0 && (UINT32)param->value == 0xffffffff) emit_not_r32(dst, reg); // not reg else emit_xor_r32_imm(dst, reg, param->value); // xor reg,param @@ -1479,9 +1484,9 @@ static void emit_xor_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags != 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags != 0 && (UINT32)param->value == 0xffffffff) emit_not_m32(dst, MEMPARAMS); // not [dest] else emit_xor_m32_imm(dst, MEMPARAMS, param->value); // xor [dest],param @@ -1504,7 +1509,7 @@ static void emit_shl_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_shl_r32_imm(dst, reg, param->value); // shl reg,param @@ -1526,7 +1531,7 @@ static void emit_shl_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_shl_m32_imm(dst, MEMPARAMS, param->value); // shl [dest],param @@ -1548,7 +1553,7 @@ static void emit_shr_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_shr_r32_imm(dst, reg, param->value); // shr reg,param @@ -1570,7 +1575,7 @@ static void emit_shr_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_shr_m32_imm(dst, MEMPARAMS, param->value); // shr [dest],param @@ -1592,7 +1597,7 @@ static void emit_sar_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_sar_r32_imm(dst, reg, param->value); // sar reg,param @@ -1614,7 +1619,7 @@ static void emit_sar_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_sar_m32_imm(dst, MEMPARAMS, param->value); // sar [dest],param @@ -1636,7 +1641,7 @@ static void emit_rol_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rol_r32_imm(dst, reg, param->value); // rol reg,param @@ -1658,7 +1663,7 @@ static void emit_rol_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rol_m32_imm(dst, MEMPARAMS, param->value); // rol [dest],param @@ -1680,7 +1685,7 @@ static void emit_ror_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_ror_r32_imm(dst, reg, param->value); // ror reg,param @@ -1702,7 +1707,7 @@ static void emit_ror_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_ror_m32_imm(dst, MEMPARAMS, param->value); // ror [dest],param @@ -1724,7 +1729,7 @@ static void emit_rcl_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rcl_r32_imm(dst, reg, param->value); // rcl reg,param @@ -1746,7 +1751,7 @@ static void emit_rcl_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rcl_m32_imm(dst, MEMPARAMS, param->value); // rcl [dest],param @@ -1768,7 +1773,7 @@ static void emit_rcr_r32_p32(drcbe_state *drcbe, x86code **dst, UINT8 reg, const { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rcr_r32_imm(dst, reg, param->value); // rcr reg,param @@ -1790,7 +1795,7 @@ static void emit_rcr_m32_p32(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM { if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; else emit_rcr_m32_imm(dst, MEMPARAMS, param->value); // rcr [dest],param @@ -1894,7 +1899,7 @@ static void emit_push_p64(drcbe_state *drcbe, x86code **dst, const drcuml_parame static void emit_add_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_MEMORY) { emit_add_r32_m32(dst, reglo, MABS(param->value)); // add reglo,[param] @@ -1925,7 +1930,7 @@ static void emit_add_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_add_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { emit_add_m32_imm(dst, MEMPARAMS, param->value); // add [dest],param @@ -1952,7 +1957,7 @@ static void emit_add_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM static void emit_adc_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_MEMORY) { emit_adc_r32_m32(dst, reglo, MABS(param->value)); // adc reglo,[param] @@ -1983,7 +1988,7 @@ static void emit_adc_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_adc_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { emit_adc_m32_imm(dst, MEMPARAMS, param->value); // adc [dest],param @@ -2010,7 +2015,7 @@ static void emit_adc_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM static void emit_sub_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_MEMORY) { emit_sub_r32_m32(dst, reglo, MABS(param->value)); // sub reglo,[param] @@ -2041,7 +2046,7 @@ static void emit_sub_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_sub_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { emit_sub_m32_imm(dst, MEMPARAMS, param->value); // sub [dest],param @@ -2068,7 +2073,7 @@ static void emit_sub_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM static void emit_sbb_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_MEMORY) { emit_sbb_r32_m32(dst, reglo, MABS(param->value)); // sbb reglo,[param] @@ -2099,7 +2104,7 @@ static void emit_sbb_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_sbb_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { emit_sbb_m32_imm(dst, MEMPARAMS, param->value); // sbb [dest],param @@ -2126,7 +2131,7 @@ static void emit_sbb_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM static void emit_and_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_MEMORY) { emit_and_r32_m32(dst, reglo, MABS(param->value)); // and reglo,[param] @@ -2135,16 +2140,16 @@ static void emit_and_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN } else if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0xffffffff) + if (inst->flags == 0 && (UINT32)param->value == 0xffffffff) /* skip */; - else if (inst->condflags == 0 && (UINT32)param->value == 0) + else if (inst->flags == 0 && (UINT32)param->value == 0) emit_xor_r32_r32(dst, reglo, reglo); // xor reglo,reglo else emit_and_r32_imm(dst, reglo, param->value); // and reglo,param if (saveflags) emit_pushf(dst); // pushf - if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) + if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) /* skip */; - else if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0) + else if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0) emit_xor_r32_r32(dst, reghi, reghi); // xor reghi,reghi else emit_and_r32_imm(dst, reghi, param->value >> 32); // and reghi,param >> 32 @@ -2167,19 +2172,19 @@ static void emit_and_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_and_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0xffffffff) + if (inst->flags == 0 && (UINT32)param->value == 0xffffffff) /* skip */; - else if (inst->condflags == 0 && (UINT32)param->value == 0) + else if (inst->flags == 0 && (UINT32)param->value == 0) emit_mov_m32_imm(dst, MEMPARAMS, 0); // mov [dest],0 else emit_and_m32_imm(dst, MEMPARAMS, param->value); // and [dest],param if (saveflags) emit_pushf(dst); // pushf - if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) + if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) /* skip */; - else if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0) + else if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0) emit_mov_m32_imm(dst, MEMPARAMS + 4, 0); // mov [dest+4],0 else emit_and_m32_imm(dst, MEMPARAMS + 4, param->value >> 32); // and [dest+4],param >> 32 @@ -2204,7 +2209,7 @@ static void emit_and_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM static void emit_test_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_MEMORY) { emit_test_m32_r32(dst, MABS(param->value), reglo); // test [param],reglo @@ -2235,7 +2240,7 @@ static void emit_test_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UI static void emit_test_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { emit_test_m32_imm(dst, MEMPARAMS, param->value); // test [dest],param @@ -2262,7 +2267,7 @@ static void emit_test_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARA static void emit_or_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_MEMORY) { emit_or_r32_m32(dst, reglo, MABS(param->value)); // or reglo,[param] @@ -2271,16 +2276,16 @@ static void emit_or_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT } else if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags == 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags == 0 && (UINT32)param->value == 0xffffffff) emit_mov_r32_imm(dst, reglo, -1); // mov reglo,-1 else emit_or_r32_imm(dst, reglo, param->value); // or reglo,param if (saveflags) emit_pushf(dst); // pushf - if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0) + if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0) /* skip */; - else if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) + else if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) emit_mov_r32_imm(dst, reghi, -1); // mov reghi,-1 else emit_or_r32_imm(dst, reghi, param->value >> 32); // or reghi,param >> 32 @@ -2303,19 +2308,19 @@ static void emit_or_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT static void emit_or_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags == 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags == 0 && (UINT32)param->value == 0xffffffff) emit_mov_m32_imm(dst, MEMPARAMS, -1); // mov [dest],-1 else emit_or_m32_imm(dst, MEMPARAMS, param->value); // or [dest],param if (saveflags) emit_pushf(dst); // pushf - if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0) + if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0) /* skip */; - else if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) + else if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) emit_mov_m32_imm(dst, MEMPARAMS + 4, -1); // mov [dest+4],-1 else emit_or_m32_imm(dst, MEMPARAMS + 4, param->value >> 32); // or [dest+4],param >> 32 @@ -2340,7 +2345,7 @@ static void emit_or_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS static void emit_xor_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_MEMORY) { emit_xor_r32_m32(dst, reglo, MABS(param->value)); // xor reglo,[param] @@ -2349,16 +2354,16 @@ static void emit_xor_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN } else if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags == 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags == 0 && (UINT32)param->value == 0xffffffff) emit_not_r32(dst, reglo); // not reglo else emit_xor_r32_imm(dst, reglo, param->value); // xor reglo,param if (saveflags) emit_pushf(dst); // pushf - if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0) + if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0) /* skip */; - else if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) + else if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) emit_not_r32(dst, reghi); // not reghi else emit_xor_r32_imm(dst, reghi, param->value >> 32); // xor reghi,param >> 32 @@ -2381,19 +2386,19 @@ static void emit_xor_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_xor_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAMS, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { - if (inst->condflags == 0 && (UINT32)param->value == 0) + if (inst->flags == 0 && (UINT32)param->value == 0) /* skip */; - else if (inst->condflags == 0 && (UINT32)param->value == 0xffffffff) + else if (inst->flags == 0 && (UINT32)param->value == 0xffffffff) emit_not_m32(dst, MEMPARAMS); // not [dest] else emit_xor_m32_imm(dst, MEMPARAMS, param->value); // xor [dest],param if (saveflags) emit_pushf(dst); // pushf - if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0) + if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0) /* skip */; - else if (inst->condflags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) + else if (inst->flags == 0 && (UINT32)(param->value >> 32) == 0xffffffff) emit_not_m32(dst, MEMPARAMS + 4); // not [dest+4] else emit_xor_m32_imm(dst, MEMPARAMS + 4, param->value >> 32); // xor [dest+4],param >> 32 @@ -2418,17 +2423,17 @@ static void emit_xor_m64_p64(drcbe_state *drcbe, x86code **dst, DECLARE_MEMPARAM static void emit_shl_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = (inst->condflags != 0); + int saveflags = (inst->flags != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { int count = param->value & 63; - if (inst->condflags == 0 && count == 0) + if (inst->flags == 0 && count == 0) /* skip */; else { while (count >= 32) { - if (inst->condflags != 0) + if (inst->flags != 0) { emit_shld_r32_r32_imm(dst, reghi, reglo, 31); // shld reghi,reglo,31 emit_shl_r32_imm(dst, reglo, 31); // shl reglo,31 @@ -2441,7 +2446,7 @@ static void emit_shl_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN count -= 32; } } - if (inst->condflags != 0 || count > 0) + if (inst->flags != 0 || count > 0) { emit_shld_r32_r32_imm(dst, reghi, reglo, count); // shld reghi,reglo,count if (saveflags) emit_pushf(dst); // pushf @@ -2455,7 +2460,7 @@ static void emit_shl_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20 emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1 - if (inst->condflags != 0) + if (inst->flags != 0) { emit_sub_r32_imm(dst, REG_ECX, 31); // sub ecx,31 emit_shld_r32_r32_imm(dst, reghi, reglo, 31); // shld reghi,reglo,31 @@ -2489,17 +2494,17 @@ static void emit_shl_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_shr_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { int count = param->value & 63; - if (inst->condflags == 0 && count == 0) + if (inst->flags == 0 && count == 0) /* skip */; else { while (count >= 32) { - if (inst->condflags != 0) + if (inst->flags != 0) { emit_shrd_r32_r32_imm(dst, reglo, reghi, 31); // shrd reglo,reghi,31 emit_shr_r32_imm(dst, reghi, 31); // shr reghi,31 @@ -2512,7 +2517,7 @@ static void emit_shr_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN count -= 32; } } - if (inst->condflags != 0 || count > 0) + if (inst->flags != 0 || count > 0) { emit_shrd_r32_r32_imm(dst, reglo, reghi, count); // shrd reglo,reghi,count if (saveflags) emit_pushf(dst); // pushf @@ -2526,7 +2531,7 @@ static void emit_shr_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20 emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1 - if (inst->condflags != 0) + if (inst->flags != 0) { emit_sub_r32_imm(dst, REG_ECX, 31); // sub ecx,31 emit_shrd_r32_r32_imm(dst, reglo, reghi, 31); // shrd reglo,reghi,31 @@ -2560,17 +2565,17 @@ static void emit_shr_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_sar_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { int count = param->value & 63; - if (inst->condflags == 0 && count == 0) + if (inst->flags == 0 && count == 0) /* skip */; else { while (count >= 32) { - if (inst->condflags != 0) + if (inst->flags != 0) { emit_shrd_r32_r32_imm(dst, reglo, reghi, 31); // shrd reglo,reghi,31 emit_sar_r32_imm(dst, reghi, 31); // sar reghi,31 @@ -2583,7 +2588,7 @@ static void emit_sar_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN count -= 32; } } - if (inst->condflags != 0 || count > 0) + if (inst->flags != 0 || count > 0) { emit_shrd_r32_r32_imm(dst, reglo, reghi, count); // shrd reglo,reghi,count if (saveflags) emit_pushf(dst); // pushf @@ -2597,7 +2602,7 @@ static void emit_sar_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20 emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1 - if (inst->condflags != 0) + if (inst->flags != 0) { emit_sub_r32_imm(dst, REG_ECX, 31); // sub ecx,31 emit_shrd_r32_r32_imm(dst, reglo, reghi, 31); // shrd reglo,reghi,31 @@ -2631,17 +2636,17 @@ static void emit_sar_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_rol_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { int count = param->value & 63; - if (inst->condflags == 0 && count == 0) + if (inst->flags == 0 && count == 0) /* skip */; else { while (count >= 32) { - if (inst->condflags != 0) + if (inst->flags != 0) { emit_mov_r32_r32(dst, REG_ECX, reglo); // mov ecx,reglo emit_shld_r32_r32_imm(dst, reglo, reghi, 31); // shld reglo,reghi,31 @@ -2654,7 +2659,7 @@ static void emit_rol_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN count -= 32; } } - if (inst->condflags != 0 || count > 0) + if (inst->flags != 0 || count > 0) { emit_mov_r32_r32(dst, REG_ECX, reglo); // mov ecx,reglo emit_shld_r32_r32_imm(dst, reglo, reghi, count); // shld reglo,reghi,count @@ -2670,7 +2675,7 @@ static void emit_rol_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20 emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1 - if (inst->condflags != 0) + if (inst->flags != 0) { emit_sub_r32_imm(dst, REG_ECX, 31); // sub ecx,31 emit_mov_r32_r32(dst, REG_EBX, reglo); // mov ebx,reglo @@ -2705,17 +2710,17 @@ static void emit_rol_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_ror_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); if (param->type == DRCUML_PTYPE_IMMEDIATE) { int count = param->value & 63; - if (inst->condflags == 0 && count == 0) + if (inst->flags == 0 && count == 0) /* skip */; else { while (count >= 32) { - if (inst->condflags != 0) + if (inst->flags != 0) { emit_mov_r32_r32(dst, REG_ECX, reglo); // mov ecx,reglo emit_shrd_r32_r32_imm(dst, reglo, reghi, 31); // shrd reglo,reghi,31 @@ -2728,7 +2733,7 @@ static void emit_ror_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN count -= 32; } } - if (inst->condflags != 0 || count > 0) + if (inst->flags != 0 || count > 0) { emit_mov_r32_r32(dst, REG_ECX, reglo); // mov ecx,reglo emit_shrd_r32_r32_imm(dst, reglo, reghi, count); // shrd reglo,reghi,count @@ -2744,7 +2749,7 @@ static void emit_ror_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20 emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1 - if (inst->condflags != 0) + if (inst->flags != 0) { emit_sub_r32_imm(dst, REG_ECX, 31); // sub ecx,31 emit_mov_r32_r32(dst, REG_EBX, reglo); // mov ebx,reglo @@ -2779,7 +2784,7 @@ static void emit_ror_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_rcl_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = ((inst->condflags & DRCUML_FLAG_Z) != 0); + int saveflags = ((inst->flags & DRCUML_FLAG_Z) != 0); emit_link skipall, skiploop; x86code *loop; @@ -2821,7 +2826,7 @@ static void emit_rcl_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN static void emit_rcr_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UINT8 reghi, const drcuml_parameter *param, const drcuml_instruction *inst) { - int saveflags = (inst->condflags != 0); + int saveflags = (inst->flags != 0); emit_link skipall, skiploop; x86code *loop; @@ -3030,6 +3035,8 @@ static void debug_log_hashjmp(int mode, offs_t pc) static x86code *op_handle(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + assert_no_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 1); assert(inst->param[0].type == DRCUML_PTYPE_MEMORY); @@ -3045,6 +3052,8 @@ static x86code *op_handle(drcbe_state *drcbe, x86code *dst, const drcuml_instruc static x86code *op_hash(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + assert_no_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 2); assert(inst->param[0].type == DRCUML_PTYPE_IMMEDIATE); assert(inst->param[1].type == DRCUML_PTYPE_IMMEDIATE); @@ -3061,6 +3070,8 @@ static x86code *op_hash(drcbe_state *drcbe, x86code *dst, const drcuml_instructi static x86code *op_label(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + assert_no_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 1); assert(inst->param[0].type == DRCUML_PTYPE_IMMEDIATE); @@ -3076,6 +3087,8 @@ static x86code *op_label(drcbe_state *drcbe, x86code *dst, const drcuml_instruct static x86code *op_comment(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + assert_no_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 1); assert(inst->param[0].type == DRCUML_PTYPE_MEMORY); @@ -3090,6 +3103,8 @@ static x86code *op_comment(drcbe_state *drcbe, x86code *dst, const drcuml_instru static x86code *op_mapvar(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + assert_no_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 2); assert(inst->param[0].type == DRCUML_PTYPE_MAPVAR); assert(inst->param[1].type == DRCUML_PTYPE_IMMEDIATE); @@ -3111,15 +3126,16 @@ static x86code *op_mapvar(drcbe_state *drcbe, x86code *dst, const drcuml_instruc static x86code *op_debug(drcbe_state *drcbe, x86code *dst, const drcuml_instruction *inst) { + /* validate instruction */ + assert(inst->size == 4); + assert_no_condition(inst); + assert_no_flags(inst); + #ifdef ENABLE_DEBUGGER if (Machine->debug_mode) { drcuml_parameter pcp; - /* validate instruction */ - assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); - /* normalize parameters */ param_normalize_1(drcbe, inst, &pcp, PTYPE_MRI); @@ -3144,17 +3160,18 @@ static x86code *op_exit(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= DRCUML_COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &retp, PTYPE_MRI); /* load the parameter into EAX */ emit_mov_r32_p32(drcbe, &dst, REG_EAX, &retp); // mov eax,retp - if (inst->condflags == DRCUML_COND_ALWAYS) + if (inst->condition == DRCUML_COND_ALWAYS) emit_jmp(&dst, drcbe->exit); // jmp exit else - emit_jcc(&dst, X86_CONDITION(inst->condflags), drcbe->exit); // jcc exit + emit_jcc(&dst, X86_CONDITION(inst->condition), drcbe->exit); // jcc exit return dst; } @@ -3170,7 +3187,8 @@ static x86code *op_hashjmp(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &modep, PTYPE_MRI, &pcp, PTYPE_MRI, &exp, PTYPE_M); @@ -3256,17 +3274,18 @@ static x86code *op_jmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= DRCUML_COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &labelp, PTYPE_I); /* look up the jump target and jump there */ jmptarget = (x86code *)drclabel_get_codeptr(drcbe->labels, labelp.value, fixup_label, dst); - if (inst->condflags == DRCUML_COND_ALWAYS) + if (inst->condition == DRCUML_COND_ALWAYS) emit_jmp(&dst, jmptarget); // jmp target else - emit_jcc(&dst, X86_CONDITION(inst->condflags), jmptarget); // jcc target + emit_jcc(&dst, X86_CONDITION(inst->condition), jmptarget); // jcc target return dst; } @@ -3283,7 +3302,8 @@ static x86code *op_exh(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= DRCUML_COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &handp, PTYPE_M, &exp, PTYPE_MRI); @@ -3292,7 +3312,7 @@ static x86code *op_exh(drcbe_state *drcbe, x86code *dst, const drcuml_instructio targetptr = drcuml_handle_codeptr_addr((drcuml_codehandle *)(FPTR)handp.value); /* perform the exception processing inline if unconditional */ - if (inst->condflags == DRCUML_COND_ALWAYS) + if (inst->condition == DRCUML_COND_ALWAYS) { emit_mov_m32_p32(drcbe, &dst, MABS(&drcbe->state.exp), &exp); // mov [exp],exp if (*targetptr != NULL) @@ -3304,7 +3324,7 @@ static x86code *op_exh(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* otherwise, jump to an out-of-band handler */ else { - emit_jcc(&dst, X86_CONDITION(inst->condflags), 0); // jcc exception + emit_jcc(&dst, X86_CONDITION(inst->condition), 0); // jcc exception drccache_request_oob_codegen(drcbe->cache, fixup_exception, drcbe, dst, (void *)inst); } return dst; @@ -3323,7 +3343,8 @@ static x86code *op_callh(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= DRCUML_COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &handp, PTYPE_M); @@ -3332,8 +3353,8 @@ static x86code *op_callh(drcbe_state *drcbe, x86code *dst, const drcuml_instruct targetptr = drcuml_handle_codeptr_addr((drcuml_codehandle *)(FPTR)handp.value); /* skip if conditional */ - if (inst->condflags != DRCUML_COND_ALWAYS) - emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip + if (inst->condition != DRCUML_COND_ALWAYS) + emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condition), &skip); // jcc skip /* jump through the handle; directly if a normal jump */ if (*targetptr != NULL) @@ -3342,7 +3363,7 @@ static x86code *op_callh(drcbe_state *drcbe, x86code *dst, const drcuml_instruct emit_call_m32(&dst, MABS(targetptr)); // call [targetptr] /* resolve the conditional link */ - if (inst->condflags != DRCUML_COND_ALWAYS) + if (inst->condition != DRCUML_COND_ALWAYS) resolve_link(&dst, &skip); // skip: return dst; } @@ -3358,18 +3379,19 @@ static x86code *op_ret(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= DRCUML_COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); assert(inst->numparams == 0); /* skip if conditional */ - if (inst->condflags != DRCUML_COND_ALWAYS) - emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip + if (inst->condition != DRCUML_COND_ALWAYS) + emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condition), &skip); // jcc skip /* return */ emit_ret(&dst); // ret /* resolve the conditional link */ - if (inst->condflags != DRCUML_COND_ALWAYS) + if (inst->condition != DRCUML_COND_ALWAYS) resolve_link(&dst, &skip); // skip: return dst; } @@ -3386,14 +3408,15 @@ static x86code *op_callc(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= DRCUML_COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &funcp, PTYPE_M, ¶mp, PTYPE_M); /* skip if conditional */ - if (inst->condflags != DRCUML_COND_ALWAYS) - emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip + if (inst->condition != DRCUML_COND_ALWAYS) + emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condition), &skip); // jcc skip /* perform the call */ emit_push_imm(&dst, paramp.value); // push paramp @@ -3401,7 +3424,7 @@ static x86code *op_callc(drcbe_state *drcbe, x86code *dst, const drcuml_instruct emit_add_r32_imm(&dst, REG_ESP, 4); // add esp,4 /* resolve the conditional link */ - if (inst->condflags != DRCUML_COND_ALWAYS) + if (inst->condition != DRCUML_COND_ALWAYS) resolve_link(&dst, &skip); // skip: return dst; } @@ -3417,7 +3440,8 @@ static x86code *op_recover(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &mvparam, PTYPE_I); @@ -3452,7 +3476,8 @@ static x86code *op_setfmod(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &srcp, PTYPE_MRI); @@ -3488,7 +3513,8 @@ static x86code *op_getfmod(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_MR); @@ -3516,7 +3542,8 @@ static x86code *op_getexp(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_MR); @@ -3545,7 +3572,8 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags != DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert(inst->flags != 0); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_MR); @@ -3553,7 +3581,7 @@ static x86code *op_getflgs(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* pick a target register for the general case */ dstreg = param_select_register(REG_EAX, &dstp, NULL); - switch (inst->condflags) + switch (inst->flags) { /* single flags only */ case DRCUML_FLAG_C: @@ -3675,7 +3703,8 @@ static x86code *op_save(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_M); @@ -3734,7 +3763,8 @@ static x86code *op_restore(drcbe_state *drcbe, x86code *dst, const drcuml_instru /* validate instruction */ assert(inst->size == 4); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_M); @@ -3798,7 +3828,8 @@ static x86code *op_load(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &basep, PTYPE_M, &indp, PTYPE_MRI, &sizep, PTYPE_I); @@ -3879,7 +3910,8 @@ static x86code *op_loads(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &basep, PTYPE_M, &indp, PTYPE_MRI, &sizep, PTYPE_I); @@ -3948,7 +3980,8 @@ static x86code *op_store(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &basep, PTYPE_M, &indp, PTYPE_MRI, &srcp, PTYPE_MRI, &sizep, PTYPE_I); @@ -4057,7 +4090,8 @@ static x86code *op_read(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &addrp, PTYPE_MRI, &spacesizep, PTYPE_I); @@ -4132,7 +4166,8 @@ static x86code *op_readm(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &addrp, PTYPE_MRI, &maskp, PTYPE_MRI, &spacesizep, PTYPE_I); @@ -4204,7 +4239,8 @@ static x86code *op_write(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &addrp, PTYPE_MRI, &srcp, PTYPE_MRI, &spacesizep, PTYPE_I); @@ -4243,7 +4279,8 @@ static x86code *op_writem(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &addrp, PTYPE_MRI, &srcp, PTYPE_MRI, &maskp, PTYPE_MRI, &spacesizep, PTYPE_I); @@ -4285,7 +4322,8 @@ static x86code *op_carry(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &srcp, PTYPE_MRI, &bitp, PTYPE_MRI); @@ -4364,7 +4402,8 @@ static x86code *op_set(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags >= DRCUML_COND_Z && inst->condflags < DRCUML_COND_MAX); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_1(drcbe, inst, &dstp, PTYPE_MR); @@ -4373,7 +4412,7 @@ static x86code *op_set(drcbe_state *drcbe, x86code *dst, const drcuml_instructio dstreg = param_select_register(REG_EAX, &dstp, NULL); /* set to AL */ - emit_setcc_r8(&dst, X86_CONDITION(inst->condflags), REG_AL); // setcc al + emit_setcc_r8(&dst, X86_CONDITION(inst->condition), REG_AL); // setcc al emit_movzx_r32_r8(&dst, dstreg, REG_AL); // movzx dstreg,al /* store low 32 bits */ @@ -4405,7 +4444,8 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= DRCUML_COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters, but only if we got here directly */ /* other opcodes call through here with pre-normalized parameters */ @@ -4425,8 +4465,8 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio dstreg = param_select_register(REG_EAX, &dstp, NULL); /* always start with a jmp */ - if (inst->condflags != DRCUML_COND_ALWAYS) - emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip + if (inst->condition != DRCUML_COND_ALWAYS) + emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condition), &skip); // jcc skip /* 32-bit form */ if (inst->size == 4) @@ -4440,20 +4480,20 @@ static x86code *op_mov(drcbe_state *drcbe, x86code *dst, const drcuml_instructio emit_mov_m32_imm(&dst, MABS(dstp.value), srcp.value); // mov [dstp],srcp /* conditional memory to register */ - else if (inst->condflags != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_MEMORY) + else if (inst->condition != DRCUML_COND_ALWAYS && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_MEMORY) { dst = savedst; skip.target = NULL; - emit_cmovcc_r32_m32(&dst, X86_CONDITION(inst->condflags), dstp.value, MABS(srcp.value)); + emit_cmovcc_r32_m32(&dst, X86_CONDITION(inst->condition), dstp.value, MABS(srcp.value)); // cmovcc dstp,[srcp] } /* conditional register to register */ - else if (inst->condflags != 0 && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_INT_REGISTER) + else if (inst->condition != DRCUML_COND_ALWAYS && dstp.type == DRCUML_PTYPE_INT_REGISTER && srcp.type == DRCUML_PTYPE_INT_REGISTER) { dst = savedst; skip.target = NULL; - emit_cmovcc_r32_r32(&dst, X86_CONDITION(inst->condflags), dstp.value, srcp.value); + emit_cmovcc_r32_r32(&dst, X86_CONDITION(inst->condition), dstp.value, srcp.value); // cmovcc dstp,srcp } @@ -4509,7 +4549,8 @@ static x86code *op_sext(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI, &sizep, PTYPE_I); @@ -4580,7 +4621,8 @@ static x86code *op_roland(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI, &shiftp, PTYPE_MRI, &maskp, PTYPE_MRI); @@ -4645,7 +4687,8 @@ static x86code *op_rolins(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI, &shiftp, PTYPE_MRI, &maskp, PTYPE_MRI); @@ -4739,15 +4782,16 @@ static x86code *op_add(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value + src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -4761,11 +4805,11 @@ static x86code *op_add(drcbe_state *drcbe, x86code *dst, const drcuml_instructio emit_add_m32_p32(drcbe, &dst, MABS(dstp.value), &src2p, inst); // add [dstp],src2p /* reg = reg + imm */ - else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) emit_lea_r32_m32(&dst, dstp.value, MBD(src1p.value, src2p.value)); // lea dstp,[src1p+src2p] /* reg = reg + reg */ - else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_INT_REGISTER && inst->condflags == 0) + else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_INT_REGISTER && inst->flags == 0) emit_lea_r32_m32(&dst, dstp.value, MBISD(src1p.value, src2p.value, 1, 0)); // lea dstp,[src1p+src2p] /* general case */ @@ -4807,7 +4851,8 @@ static x86code *op_addc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); @@ -4861,15 +4906,16 @@ static x86code *op_sub(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value - src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -4883,7 +4929,7 @@ static x86code *op_sub(drcbe_state *drcbe, x86code *dst, const drcuml_instructio emit_sub_m32_p32(drcbe, &dst, MABS(dstp.value), &src2p, inst); // sub [dstp],src2p /* reg = reg - imm */ - else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) emit_lea_r32_m32(&dst, dstp.value, MBD(src1p.value, -src2p.value)); // lea dstp,[src1p-src2p] /* general case */ @@ -4925,7 +4971,8 @@ static x86code *op_subc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); @@ -4980,7 +5027,8 @@ static x86code *op_cmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_V | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_2(drcbe, inst, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); @@ -5053,14 +5101,15 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_V |*/ DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_4_commutative(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); compute_hi = (dstp.type != edstp.type || dstp.value != edstp.value); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) { @@ -5109,13 +5158,13 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi emit_mov_p32_r32(drcbe, &dst, &edstp, REG_EDX); // mov edstp,edx /* compute flags */ - if (inst->condflags != 0) + if (inst->flags != 0) { if (compute_hi) { - if (inst->condflags == DRCUML_FLAG_Z) + if (inst->flags == DRCUML_FLAG_Z) emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax - else if (inst->condflags == DRCUML_FLAG_S) + else if (inst->flags == DRCUML_FLAG_S) emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx else { @@ -5146,11 +5195,11 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reslo + 0)); // mov eax,reslo.lo emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reslo + 1)); // mov edx,reslo.hi emit_mov_p64_r64(drcbe, &dst, &dstp, REG_EAX, REG_EDX); // mov dstp,edx:eax - if (inst->condflags != 0 && !compute_hi) + if (inst->flags != 0 && !compute_hi) { - if (inst->condflags == DRCUML_FLAG_Z) + if (inst->flags == DRCUML_FLAG_Z) emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax - else if (inst->condflags == DRCUML_FLAG_S) + else if (inst->flags == DRCUML_FLAG_S) emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx else { @@ -5162,19 +5211,19 @@ static x86code *op_mulu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi } if (compute_hi) { - if (inst->condflags & DRCUML_FLAG_Z) + if (inst->flags & DRCUML_FLAG_Z) emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reshi + 0)); // mov eax,reshi.lo emit_mov_r32_m32(&dst, REG_ECX, MABS((UINT32 *)&drcbe->reshi + 1)); // mov ecx,reshi.hi emit_mov_p64_r64(drcbe, &dst, &edstp, REG_EAX, REG_ECX); // mov edstp,ecx:eax - if (inst->condflags != 0) + if (inst->flags != 0) { - if (inst->condflags == DRCUML_FLAG_Z) + if (inst->flags == DRCUML_FLAG_Z) { emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx } - else if (inst->condflags == DRCUML_FLAG_S) + else if (inst->flags == DRCUML_FLAG_S) emit_test_r32_r32(&dst, REG_ECX, REG_ECX); // test ecx,ecx else { @@ -5202,14 +5251,15 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_V |*/ DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_4_commutative(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); compute_hi = (dstp.type != edstp.type || dstp.value != edstp.value); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) { @@ -5281,13 +5331,13 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi } /* compute flags */ - if (inst->condflags != 0) + if (inst->flags != 0) { if (compute_hi) { - if (inst->condflags == DRCUML_FLAG_Z) + if (inst->flags == DRCUML_FLAG_Z) emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax - else if (inst->condflags == DRCUML_FLAG_S) + else if (inst->flags == DRCUML_FLAG_S) emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx else { @@ -5318,11 +5368,11 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reslo + 0)); // mov eax,reslo.lo emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reslo + 1)); // mov edx,reslo.hi emit_mov_p64_r64(drcbe, &dst, &dstp, REG_EAX, REG_EDX); // mov dstp,edx:eax - if (inst->condflags != 0 && !compute_hi) + if (inst->flags != 0 && !compute_hi) { - if (inst->condflags == DRCUML_FLAG_Z) + if (inst->flags == DRCUML_FLAG_Z) emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax - else if (inst->condflags == DRCUML_FLAG_S) + else if (inst->flags == DRCUML_FLAG_S) emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx else { @@ -5337,14 +5387,14 @@ static x86code *op_muls(drcbe_state *drcbe, x86code *dst, const drcuml_instructi emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reshi + 0)); // mov eax,reshi.lo emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reshi + 1)); // mov edx,reshi.hi emit_mov_p64_r64(drcbe, &dst, &edstp, REG_EAX, REG_EDX); // mov edstp,edx:eax - if (inst->condflags != 0) + if (inst->flags != 0) { - if (inst->condflags == DRCUML_FLAG_Z) + if (inst->flags == DRCUML_FLAG_Z) { emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx } - else if (inst->condflags == DRCUML_FLAG_S) + else if (inst->flags == DRCUML_FLAG_S) emit_test_r32_r32(&dst, REG_ECX, REG_ECX); // test ecx,ecx else { @@ -5373,14 +5423,15 @@ static x86code *op_divu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_V |*/ DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); compute_rem = (dstp.type != edstp.type || dstp.value != edstp.value); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) { @@ -5444,7 +5495,7 @@ static x86code *op_divu(drcbe_state *drcbe, x86code *dst, const drcuml_instructi emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reslo + 0)); // mov eax,reslo.lo emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reslo + 1)); // mov edx,reslo.hi emit_mov_p64_r64(drcbe, &dst, &dstp, REG_EAX, REG_EDX); // mov dstp,edx:eax - if (inst->condflags != 0) + if (inst->flags != 0) emit_or_r32_r32(&dst, REG_EAX, REG_EDX); // or eax,edx if (compute_rem) { @@ -5469,14 +5520,15 @@ static x86code *op_divs(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_V |*/ DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); compute_rem = (dstp.type != edstp.type || dstp.value != edstp.value); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) { @@ -5540,7 +5592,7 @@ static x86code *op_divs(drcbe_state *drcbe, x86code *dst, const drcuml_instructi emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reslo + 0)); // mov eax,reslo.lo emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reslo + 1)); // mov edx,reslo.hi emit_mov_p64_r64(drcbe, &dst, &dstp, REG_EAX, REG_EDX); // mov dstp,edx:eax - if (inst->condflags != 0) + if (inst->flags != 0) emit_or_r32_r32(&dst, REG_EAX, REG_EDX); // or eax,edx if (compute_rem) { @@ -5564,15 +5616,16 @@ static x86code *op_and(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value & src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && (src2p.value & size_to_mask[inst->size]) == size_to_mask[inst->size] && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && (src2p.value & size_to_mask[inst->size]) == size_to_mask[inst->size] && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5624,7 +5677,8 @@ static x86code *op_test(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_2_commutative(drcbe, inst, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); @@ -5676,15 +5730,16 @@ static x86code *op_or(drcbe_state *drcbe, x86code *dst, const drcuml_instruction /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value | src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5736,15 +5791,16 @@ static x86code *op_xor(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value & src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5796,13 +5852,14 @@ static x86code *op_lzcnt(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_Z | DRCUML_FLAG_S*/0); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0 && inst->size == 4) + if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0 && inst->size == 4) return convert_to_mov_imm(drcbe, dst, inst, &dstp, count_leading_zeros(srcp.value)); /* pick a target register for the general case */ @@ -5849,13 +5906,14 @@ static x86code *op_bswap(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == 0); + assert_no_condition(inst); + assert_flags(inst, /*DRCUML_FLAG_Z | DRCUML_FLAG_S*/0); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (srcp.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) return convert_to_mov_imm(drcbe, dst, inst, &dstp, FLIPENDIAN_INT32(srcp.value)); @@ -5897,15 +5955,16 @@ static x86code *op_shl(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, src1p.value << src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -5950,15 +6009,16 @@ static x86code *op_shr(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -6003,20 +6063,21 @@ static x86code *op_sar(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) { if (inst->size == 4) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (INT32)src1p.value >> src2p.value); else if (inst->size == 8) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (INT64)src1p.value >> src2p.value); } - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -6061,15 +6122,16 @@ static x86code *op_rol(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -6114,15 +6176,16 @@ static x86code *op_ror(drcbe_state *drcbe, x86code *dst, const drcuml_instructio /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -6167,15 +6230,16 @@ static x86code *op_rolc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -6220,15 +6284,16 @@ static x86code *op_rorc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_Z | DRCUML_FLAG_S)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_S); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI); /* degenerate cases -- convert to a move */ - if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->condflags == 0) + if (src1p.type == DRCUML_PTYPE_IMMEDIATE && src2p.type == DRCUML_PTYPE_IMMEDIATE && inst->flags == 0) return convert_to_mov_imm(drcbe, dst, inst, &dstp, (UINT64)src1p.value >> src2p.value); - if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->condflags == 0) + if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == 0 && inst->flags == 0) return convert_to_mov_src1(drcbe, dst, inst, &dstp, &src1p); /* pick a target register for the general case */ @@ -6277,7 +6342,8 @@ static x86code *op_fload(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &basep, PTYPE_M, &indp, PTYPE_MRI); @@ -6318,7 +6384,8 @@ static x86code *op_fstore(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &basep, PTYPE_M, &indp, PTYPE_MRI, &srcp, PTYPE_MF); @@ -6359,7 +6426,8 @@ static x86code *op_fread(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &addrp, PTYPE_MRI, &spacep, PTYPE_I); @@ -6392,7 +6460,8 @@ static x86code *op_fwrite(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &addrp, PTYPE_MRI, &srcp, PTYPE_MF, &spacep, PTYPE_I); @@ -6424,14 +6493,15 @@ static x86code *op_fmov(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS || (inst->condflags >= DRCUML_COND_Z && inst->condflags < DRCUML_COND_MAX)); + assert_any_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); /* always start with a jmp */ - if (inst->condflags != DRCUML_COND_ALWAYS) - emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condflags), &skip); // jcc skip + if (inst->condition != DRCUML_COND_ALWAYS) + emit_jcc_short_link(&dst, X86_NOT_CONDITION(inst->condition), &skip); // jcc skip /* general case */ emit_mov_r32_m32(&dst, REG_EAX, MABS(srcp.value)); // mov eax,[srcp] @@ -6458,7 +6528,8 @@ static x86code *op_ftoint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MF, &sizep, PTYPE_I, &roundp, PTYPE_I); @@ -6531,7 +6602,8 @@ static x86code *op_ffrint(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MRI, &sizep, PTYPE_I); @@ -6587,7 +6659,8 @@ static x86code *op_ffrflt(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF, &sizep, PTYPE_I); @@ -6613,7 +6686,8 @@ static x86code *op_frnds(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -6637,7 +6711,8 @@ static x86code *op_fadd(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &src1p, PTYPE_MF, &src2p, PTYPE_MF); @@ -6662,7 +6737,8 @@ static x86code *op_fsub(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &src1p, PTYPE_MF, &src2p, PTYPE_MF); @@ -6687,7 +6763,8 @@ static x86code *op_fcmp(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert((inst->condflags & ~(DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_U)) == 0); + assert_no_condition(inst); + assert_flags(inst, DRCUML_FLAG_C | DRCUML_FLAG_Z | DRCUML_FLAG_U); /* normalize parameters */ param_normalize_2(drcbe, inst, &src1p, PTYPE_MF, &src2p, PTYPE_MF); @@ -6713,7 +6790,8 @@ static x86code *op_fmul(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &src1p, PTYPE_MF, &src2p, PTYPE_MF); @@ -6738,7 +6816,8 @@ static x86code *op_fdiv(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_3(drcbe, inst, &dstp, PTYPE_MF, &src1p, PTYPE_MF, &src2p, PTYPE_MF); @@ -6763,7 +6842,8 @@ static x86code *op_fneg(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -6787,7 +6867,8 @@ static x86code *op_fabs(drcbe_state *drcbe, x86code *dst, const drcuml_instructi /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -6811,7 +6892,8 @@ static x86code *op_fsqrt(drcbe_state *drcbe, x86code *dst, const drcuml_instruct /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -6835,7 +6917,8 @@ static x86code *op_frecip(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); @@ -6860,7 +6943,8 @@ static x86code *op_frsqrt(drcbe_state *drcbe, x86code *dst, const drcuml_instruc /* validate instruction */ assert(inst->size == 4 || inst->size == 8); - assert(inst->condflags == DRCUML_COND_ALWAYS); + assert_no_condition(inst); + assert_no_flags(inst); /* normalize parameters */ param_normalize_2(drcbe, inst, &dstp, PTYPE_MF, &srcp, PTYPE_MF); diff --git a/src/emu/cpu/drcuml.c b/src/emu/cpu/drcuml.c index d16d0cbaddd..fa63422ddf3 100644 --- a/src/emu/cpu/drcuml.c +++ b/src/emu/cpu/drcuml.c @@ -61,13 +61,13 @@ ***************************************************************************/ /* opcode validation condition/flag valid bitmasks */ -#define OV_CONDFLAG_NONE 0x00 -#define OV_CONDFLAG_COND 0x80 -#define OV_CONDFLAG_SZ (DRCUML_FLAG_S | DRCUML_FLAG_Z) -#define OV_CONDFLAG_SZC (DRCUML_FLAG_S | DRCUML_FLAG_Z | DRCUML_FLAG_C) -#define OV_CONDFLAG_SZVC (DRCUML_FLAG_S | DRCUML_FLAG_Z | DRCUML_FLAG_V | DRCUML_FLAG_C) -#define OV_CONDFLAG_UZC (DRCUML_FLAG_U | DRCUML_FLAG_Z | DRCUML_FLAG_C) -#define OV_CONDFLAG_FLAGS 0x1f +#define OV_FLAGS_NONE 0x00 +#define OV_FLAGS_SZ (DRCUML_FLAG_S | DRCUML_FLAG_Z) +#define OV_FLAGS_SZC (DRCUML_FLAG_S | DRCUML_FLAG_Z | DRCUML_FLAG_C) +#define OV_FLAGS_SZV (DRCUML_FLAG_S | DRCUML_FLAG_Z | DRCUML_FLAG_V) +#define OV_FLAGS_SZVC (DRCUML_FLAG_S | DRCUML_FLAG_Z | DRCUML_FLAG_V | DRCUML_FLAG_C) +#define OV_FLAGS_UZC (DRCUML_FLAG_U | DRCUML_FLAG_Z | DRCUML_FLAG_C) +#define OV_FLAGS_FLAGS 0x1f /* bitmasks of valid parameter types and flags */ #define OV_PARAM_ALLOWED_NONE (1 << DRCUML_PTYPE_NONE) @@ -109,12 +109,9 @@ struct _drcuml_state { drccache * cache; /* pointer to the codegen cache */ drcuml_block * blocklist; /* list of active blocks */ - const drcbe_interface * beintf; /* backend interface pointer */ drcbe_state * bestate; /* pointer to the back-end state */ - drcuml_codehandle * handlelist; /* head of linked list of handles */ - FILE * umllog; /* handle to the UML logfile */ }; @@ -148,7 +145,8 @@ struct _drcuml_opcode_valid { drcuml_opcode opcode; /* the opcode itself */ UINT8 sizes; /* allowed sizes */ - UINT8 condflags; /* allowed conditions/flags */ + UINT8 condition; /* conditions? */ + UINT8 flags; /* allowed flags */ UINT16 ptypes[4]; /* allowed types for parameters */ }; @@ -172,99 +170,99 @@ struct _bevalidate_test ***************************************************************************/ /* macro to simplify the table */ -#define OPVALID_ENTRY_0(op,sizes,condflag) { DRCUML_OP_##op, sizes, OV_CONDFLAG_##condflag, { OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE } }, -#define OPVALID_ENTRY_1(op,sizes,condflag,p0) { DRCUML_OP_##op, sizes, OV_CONDFLAG_##condflag, { OV_PARAM_ALLOWED_##p0, OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE } }, -#define OPVALID_ENTRY_2(op,sizes,condflag,p0,p1) { DRCUML_OP_##op, sizes, OV_CONDFLAG_##condflag, { OV_PARAM_ALLOWED_##p0, OV_PARAM_ALLOWED_##p1, OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE } }, -#define OPVALID_ENTRY_3(op,sizes,condflag,p0,p1,p2) { DRCUML_OP_##op, sizes, OV_CONDFLAG_##condflag, { OV_PARAM_ALLOWED_##p0, OV_PARAM_ALLOWED_##p1, OV_PARAM_ALLOWED_##p2, OV_PARAM_ALLOWED_NONE } }, -#define OPVALID_ENTRY_4(op,sizes,condflag,p0,p1,p2,p3) { DRCUML_OP_##op, sizes, OV_CONDFLAG_##condflag, { OV_PARAM_ALLOWED_##p0, OV_PARAM_ALLOWED_##p1, OV_PARAM_ALLOWED_##p2, OV_PARAM_ALLOWED_##p3 } }, +#define OPVALID_ENTRY_0(op,sizes,cond,flag) { DRCUML_OP_##op, sizes, cond, OV_FLAGS_##flag, { OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE } }, +#define OPVALID_ENTRY_1(op,sizes,cond,flag,p0) { DRCUML_OP_##op, sizes, cond, OV_FLAGS_##flag, { OV_PARAM_ALLOWED_##p0, OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE } }, +#define OPVALID_ENTRY_2(op,sizes,cond,flag,p0,p1) { DRCUML_OP_##op, sizes, cond, OV_FLAGS_##flag, { OV_PARAM_ALLOWED_##p0, OV_PARAM_ALLOWED_##p1, OV_PARAM_ALLOWED_NONE, OV_PARAM_ALLOWED_NONE } }, +#define OPVALID_ENTRY_3(op,sizes,cond,flag,p0,p1,p2) { DRCUML_OP_##op, sizes, cond, OV_FLAGS_##flag, { OV_PARAM_ALLOWED_##p0, OV_PARAM_ALLOWED_##p1, OV_PARAM_ALLOWED_##p2, OV_PARAM_ALLOWED_NONE } }, +#define OPVALID_ENTRY_4(op,sizes,cond,flag,p0,p1,p2,p3) { DRCUML_OP_##op, sizes, cond, OV_FLAGS_##flag, { OV_PARAM_ALLOWED_##p0, OV_PARAM_ALLOWED_##p1, OV_PARAM_ALLOWED_##p2, OV_PARAM_ALLOWED_##p3 } }, /* opcode validation table */ static const drcuml_opcode_valid opcode_valid_list[] = { /* Compile-time opcodes */ - OPVALID_ENTRY_1(HANDLE, 4, NONE, MEM) - OPVALID_ENTRY_2(HASH, 4, NONE, IMV, IMV) - OPVALID_ENTRY_1(LABEL, 4, NONE, IMV) - OPVALID_ENTRY_1(COMMENT, 4, NONE, ANYMEM) - OPVALID_ENTRY_2(MAPVAR, 4, NONE, MVAR, IMV) + OPVALID_ENTRY_1(HANDLE, 4, FALSE, NONE, MEM) + OPVALID_ENTRY_2(HASH, 4, FALSE, NONE, IMV, IMV) + OPVALID_ENTRY_1(LABEL, 4, FALSE, NONE, IMV) + OPVALID_ENTRY_1(COMMENT, 4, FALSE, NONE, ANYMEM) + OPVALID_ENTRY_2(MAPVAR, 4, FALSE, NONE, MVAR, IMV) /* Control Flow Operations */ - OPVALID_ENTRY_1(DEBUG, 4, NONE, IANY) - OPVALID_ENTRY_1(EXIT, 4, COND, IANY) - OPVALID_ENTRY_3(HASHJMP, 4, NONE, IANY, IANY, MEM) - OPVALID_ENTRY_1(LABEL, 4, NONE, IMV) - OPVALID_ENTRY_1(JMP, 4, COND, IMV) - OPVALID_ENTRY_2(EXH, 4, COND, MEM, IANY) - OPVALID_ENTRY_1(CALLH, 4, COND, MEM) - OPVALID_ENTRY_0(RET, 4, COND) - OPVALID_ENTRY_2(CALLC, 4, COND, ANYMEM,ANYMEM) - OPVALID_ENTRY_2(RECOVER, 4, NONE, IRM, MVAR) + OPVALID_ENTRY_1(DEBUG, 4, FALSE, NONE, IANY) + OPVALID_ENTRY_1(EXIT, 4, TRUE, NONE, IANY) + OPVALID_ENTRY_3(HASHJMP, 4, FALSE, NONE, IANY, IANY, MEM) + OPVALID_ENTRY_1(LABEL, 4, FALSE, NONE, IMV) + OPVALID_ENTRY_1(JMP, 4, TRUE, NONE, IMV) + OPVALID_ENTRY_2(EXH, 4, TRUE, NONE, MEM, IANY) + OPVALID_ENTRY_1(CALLH, 4, TRUE, NONE, MEM) + OPVALID_ENTRY_0(RET, 4, TRUE, NONE) + OPVALID_ENTRY_2(CALLC, 4, TRUE, NONE, ANYMEM,ANYMEM) + OPVALID_ENTRY_2(RECOVER, 4, FALSE, NONE, IRM, MVAR) /* Internal Register Operations */ - OPVALID_ENTRY_1(SETFMOD, 4, NONE, IANY) - OPVALID_ENTRY_1(GETFMOD, 4, NONE, IRM) - OPVALID_ENTRY_1(GETEXP, 4, NONE, IRM) - OPVALID_ENTRY_1(GETFLGS, 4, NONE, IRM) - OPVALID_ENTRY_1(SAVE, 4, NONE, ANYMEM) - OPVALID_ENTRY_1(RESTORE, 4, NONE, ANYMEM) + OPVALID_ENTRY_1(SETFMOD, 4, FALSE, NONE, IANY) + OPVALID_ENTRY_1(GETFMOD, 4, FALSE, NONE, IRM) + OPVALID_ENTRY_1(GETEXP, 4, FALSE, NONE, IRM) + OPVALID_ENTRY_1(GETFLGS, 4, FALSE, NONE, IRM) + OPVALID_ENTRY_1(SAVE, 4, FALSE, NONE, ANYMEM) + OPVALID_ENTRY_1(RESTORE, 4, FALSE, NONE, ANYMEM) /* Integer Operations */ - OPVALID_ENTRY_4(LOAD, 4|8, NONE, IRM, ANYMEM,IANY4, IMV) - OPVALID_ENTRY_4(LOADS, 4|8, NONE, IRM, ANYMEM,IANY4, IMV) - OPVALID_ENTRY_4(STORE, 4|8, NONE, ANYMEM,IANY4, IANY, IMV) - OPVALID_ENTRY_3(READ, 4|8, NONE, IRM, IANY4, IMV) - OPVALID_ENTRY_4(READM, 4|8, NONE, IRM, IANY4, IANY, IMV) - OPVALID_ENTRY_3(WRITE, 4|8, NONE, IANY4, IANY, IMV) - OPVALID_ENTRY_4(WRITEM, 4|8, NONE, IANY4, IANY, IANY, IMV) - OPVALID_ENTRY_2(CARRY, 4|8, NONE, IANY, IANY) - OPVALID_ENTRY_2(MOV, 4|8, COND, IRM, IANY) - OPVALID_ENTRY_1(SET, 4|8, COND, IRM) - OPVALID_ENTRY_3(SEXT, 4|8, NONE, IRM, IANY4, IMV) - OPVALID_ENTRY_4(ROLAND, 4|8, NONE, IRM, IANY, IANY, IANY) - OPVALID_ENTRY_4(ROLINS, 4|8, NONE, IRM, IANY, IANY, IANY) - OPVALID_ENTRY_3(ADD, 4|8, SZVC, IRM, IANY, IANY) - OPVALID_ENTRY_3(ADDC, 4|8, SZVC, IRM, IANY, IANY) - OPVALID_ENTRY_3(SUB, 4|8, SZVC, IRM, IANY, IANY) - OPVALID_ENTRY_3(SUBB, 4|8, SZVC, IRM, IANY, IANY) - OPVALID_ENTRY_2(CMP, 4|8, SZVC, IANY, IANY) - OPVALID_ENTRY_4(MULU, 4|8, SZ, IRM, IRM, IANY, IANY) - OPVALID_ENTRY_4(MULS, 4|8, SZ, IRM, IRM, IANY, IANY) - OPVALID_ENTRY_4(DIVU, 4|8, SZ, IRM, IRM, IANY, IANY) - OPVALID_ENTRY_4(DIVS, 4|8, SZ, IRM, IRM, IANY, IANY) - OPVALID_ENTRY_3(AND, 4|8, SZ, IRM, IANY, IANY) - OPVALID_ENTRY_2(TEST, 4|8, SZ, IANY, IANY) - OPVALID_ENTRY_3(OR, 4|8, SZ, IRM, IANY, IANY) - OPVALID_ENTRY_3(XOR, 4|8, SZ, IRM, IANY, IANY) - OPVALID_ENTRY_2(LZCNT, 4|8, NONE, IRM, IANY) - OPVALID_ENTRY_2(BSWAP, 4|8, NONE, IRM, IANY) - OPVALID_ENTRY_3(SHL, 4|8, SZC, IRM, IANY, IANY) - OPVALID_ENTRY_3(SHR, 4|8, SZC, IRM, IANY, IANY) - OPVALID_ENTRY_3(SAR, 4|8, SZC, IRM, IANY, IANY) - OPVALID_ENTRY_3(ROL, 4|8, SZC, IRM, IANY, IANY) - OPVALID_ENTRY_3(ROLC, 4|8, SZC, IRM, IANY, IANY) - OPVALID_ENTRY_3(ROR, 4|8, SZC, IRM, IANY, IANY) - OPVALID_ENTRY_3(RORC, 4|8, SZC, IRM, IANY, IANY) + OPVALID_ENTRY_4(LOAD, 4|8, FALSE, NONE, IRM, ANYMEM,IANY4, IMV) + OPVALID_ENTRY_4(LOADS, 4|8, FALSE, NONE, IRM, ANYMEM,IANY4, IMV) + OPVALID_ENTRY_4(STORE, 4|8, FALSE, NONE, ANYMEM,IANY4, IANY, IMV) + OPVALID_ENTRY_3(READ, 4|8, FALSE, NONE, IRM, IANY4, IMV) + OPVALID_ENTRY_4(READM, 4|8, FALSE, NONE, IRM, IANY4, IANY, IMV) + OPVALID_ENTRY_3(WRITE, 4|8, FALSE, NONE, IANY4, IANY, IMV) + OPVALID_ENTRY_4(WRITEM, 4|8, FALSE, NONE, IANY4, IANY, IANY, IMV) + OPVALID_ENTRY_2(CARRY, 4|8, FALSE, NONE, IANY, IANY) + OPVALID_ENTRY_2(MOV, 4|8, TRUE, NONE, IRM, IANY) + OPVALID_ENTRY_1(SET, 4|8, TRUE, NONE, IRM) + OPVALID_ENTRY_3(SEXT, 4|8, FALSE, SZ, IRM, IANY4, IMV) + OPVALID_ENTRY_4(ROLAND, 4|8, FALSE, SZ, IRM, IANY, IANY, IANY) + OPVALID_ENTRY_4(ROLINS, 4|8, FALSE, SZ, IRM, IANY, IANY, IANY) + OPVALID_ENTRY_3(ADD, 4|8, FALSE, SZVC, IRM, IANY, IANY) + OPVALID_ENTRY_3(ADDC, 4|8, FALSE, SZVC, IRM, IANY, IANY) + OPVALID_ENTRY_3(SUB, 4|8, FALSE, SZVC, IRM, IANY, IANY) + OPVALID_ENTRY_3(SUBB, 4|8, FALSE, SZVC, IRM, IANY, IANY) + OPVALID_ENTRY_2(CMP, 4|8, FALSE, SZVC, IANY, IANY) + OPVALID_ENTRY_4(MULU, 4|8, FALSE, SZV, IRM, IRM, IANY, IANY) + OPVALID_ENTRY_4(MULS, 4|8, FALSE, SZV, IRM, IRM, IANY, IANY) + OPVALID_ENTRY_4(DIVU, 4|8, FALSE, SZ, IRM, IRM, IANY, IANY) + OPVALID_ENTRY_4(DIVS, 4|8, FALSE, SZ, IRM, IRM, IANY, IANY) + OPVALID_ENTRY_3(AND, 4|8, FALSE, SZ, IRM, IANY, IANY) + OPVALID_ENTRY_2(TEST, 4|8, FALSE, SZ, IANY, IANY) + OPVALID_ENTRY_3(OR, 4|8, FALSE, SZ, IRM, IANY, IANY) + OPVALID_ENTRY_3(XOR, 4|8, FALSE, SZ, IRM, IANY, IANY) + OPVALID_ENTRY_2(LZCNT, 4|8, FALSE, SZ, IRM, IANY) + OPVALID_ENTRY_2(BSWAP, 4|8, FALSE, SZ, IRM, IANY) + OPVALID_ENTRY_3(SHL, 4|8, FALSE, SZC, IRM, IANY, IANY) + OPVALID_ENTRY_3(SHR, 4|8, FALSE, SZC, IRM, IANY, IANY) + OPVALID_ENTRY_3(SAR, 4|8, FALSE, SZC, IRM, IANY, IANY) + OPVALID_ENTRY_3(ROL, 4|8, FALSE, SZC, IRM, IANY, IANY) + OPVALID_ENTRY_3(ROLC, 4|8, FALSE, SZC, IRM, IANY, IANY) + OPVALID_ENTRY_3(ROR, 4|8, FALSE, SZC, IRM, IANY, IANY) + OPVALID_ENTRY_3(RORC, 4|8, FALSE, SZC, IRM, IANY, IANY) /* Floating Point Operations */ - OPVALID_ENTRY_3(FLOAD, 4|8, NONE, FRM, ANYMEM,IANY4) - OPVALID_ENTRY_3(FSTORE, 4|8, NONE, ANYMEM,IANY4, FANY) - OPVALID_ENTRY_3(FREAD, 4|8, NONE, FRM, IANY4, IMV4) - OPVALID_ENTRY_3(FWRITE, 4|8, NONE, IANY4, FANY, IMV4) - OPVALID_ENTRY_2(FMOV, 4|8, COND, FRM, FANY) - OPVALID_ENTRY_4(FTOINT, 4|8, NONE, IRM, FANY, IMM, IMM) - OPVALID_ENTRY_3(FFRINT, 4|8, NONE, FRM, IANY, IMM) - OPVALID_ENTRY_3(FFRFLT, 4|8, NONE, FRM, FANY, IMM) - OPVALID_ENTRY_2(FRNDS, 8, NONE, FRM, FANY) - OPVALID_ENTRY_3(FADD, 4|8, NONE, FRM, FANY, FANY) - OPVALID_ENTRY_3(FSUB, 4|8, NONE, FRM, FANY, FANY) - OPVALID_ENTRY_2(FCMP, 4|8, UZC, FANY, FANY) - OPVALID_ENTRY_3(FMUL, 4|8, NONE, FRM, FANY, FANY) - OPVALID_ENTRY_3(FDIV, 4|8, NONE, FRM, FANY, FANY) - OPVALID_ENTRY_2(FNEG, 4|8, NONE, FRM, FANY) - OPVALID_ENTRY_2(FABS, 4|8, NONE, FRM, FANY) - OPVALID_ENTRY_2(FSQRT, 4|8, NONE, FRM, FANY) - OPVALID_ENTRY_2(FRECIP, 4|8, NONE, FRM, FANY) - OPVALID_ENTRY_2(FRSQRT, 4|8, NONE, FRM, FANY) + OPVALID_ENTRY_3(FLOAD, 4|8, FALSE, NONE, FRM, ANYMEM,IANY4) + OPVALID_ENTRY_3(FSTORE, 4|8, FALSE, NONE, ANYMEM,IANY4, FANY) + OPVALID_ENTRY_3(FREAD, 4|8, FALSE, NONE, FRM, IANY4, IMV4) + OPVALID_ENTRY_3(FWRITE, 4|8, FALSE, NONE, IANY4, FANY, IMV4) + OPVALID_ENTRY_2(FMOV, 4|8, TRUE, NONE, FRM, FANY) + OPVALID_ENTRY_4(FTOINT, 4|8, FALSE, NONE, IRM, FANY, IMM, IMM) + OPVALID_ENTRY_3(FFRINT, 4|8, FALSE, NONE, FRM, IANY, IMM) + OPVALID_ENTRY_3(FFRFLT, 4|8, FALSE, NONE, FRM, FANY, IMM) + OPVALID_ENTRY_2(FRNDS, 8, FALSE, NONE, FRM, FANY) + OPVALID_ENTRY_3(FADD, 4|8, FALSE, NONE, FRM, FANY, FANY) + OPVALID_ENTRY_3(FSUB, 4|8, FALSE, NONE, FRM, FANY, FANY) + OPVALID_ENTRY_2(FCMP, 4|8, FALSE, UZC, FANY, FANY) + OPVALID_ENTRY_3(FMUL, 4|8, FALSE, NONE, FRM, FANY, FANY) + OPVALID_ENTRY_3(FDIV, 4|8, FALSE, NONE, FRM, FANY, FANY) + OPVALID_ENTRY_2(FNEG, 4|8, FALSE, NONE, FRM, FANY) + OPVALID_ENTRY_2(FABS, 4|8, FALSE, NONE, FRM, FANY) + OPVALID_ENTRY_2(FSQRT, 4|8, FALSE, NONE, FRM, FANY) + OPVALID_ENTRY_2(FRECIP, 4|8, FALSE, NONE, FRM, FANY) + OPVALID_ENTRY_2(FRSQRT, 4|8, FALSE, NONE, FRM, FANY) }; @@ -519,7 +517,7 @@ drcuml_block *drcuml_block_begin(drcuml_state *drcuml, UINT32 maxinst, jmp_buf * 0 parameters to the block -------------------------------------------------*/ -void drcuml_block_append_0(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condflags) +void drcuml_block_append_0(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condition, UINT8 flags) { drcuml_instruction *inst = &block->inst[block->nextinst++]; @@ -532,7 +530,8 @@ void drcuml_block_append_0(drcuml_block *block, drcuml_opcode op, UINT8 size, UI /* fill in the instruction */ inst->opcode = (UINT8)op; inst->size = size; - inst->condflags = condflags; + inst->condition = condition; + inst->flags = flags; inst->numparams = 0; /* validation */ @@ -545,7 +544,7 @@ void drcuml_block_append_0(drcuml_block *block, drcuml_opcode op, UINT8 size, UI 1 parameter to the block -------------------------------------------------*/ -void drcuml_block_append_1(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condflags, drcuml_ptype p0type, drcuml_pvalue p0value) +void drcuml_block_append_1(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condition, UINT8 flags, drcuml_ptype p0type, drcuml_pvalue p0value) { drcuml_instruction *inst = &block->inst[block->nextinst++]; @@ -558,7 +557,8 @@ void drcuml_block_append_1(drcuml_block *block, drcuml_opcode op, UINT8 size, UI /* fill in the instruction */ inst->opcode = (UINT8)op; inst->size = size; - inst->condflags = condflags; + inst->condition = condition; + inst->flags = flags; inst->numparams = 1; inst->param[0].type = p0type; inst->param[0].value = p0value; @@ -573,7 +573,7 @@ void drcuml_block_append_1(drcuml_block *block, drcuml_opcode op, UINT8 size, UI 2 parameters to the block -------------------------------------------------*/ -void drcuml_block_append_2(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condflags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value) +void drcuml_block_append_2(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condition, UINT8 flags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value) { drcuml_instruction *inst = &block->inst[block->nextinst++]; @@ -586,7 +586,8 @@ void drcuml_block_append_2(drcuml_block *block, drcuml_opcode op, UINT8 size, UI /* fill in the instruction */ inst->opcode = (UINT8)op; inst->size = size; - inst->condflags = condflags; + inst->condition = condition; + inst->flags = flags; inst->numparams = 2; inst->param[0].type = p0type; inst->param[0].value = p0value; @@ -603,7 +604,7 @@ void drcuml_block_append_2(drcuml_block *block, drcuml_opcode op, UINT8 size, UI 3 parameters to the block -------------------------------------------------*/ -void drcuml_block_append_3(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condflags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value, drcuml_ptype p2type, drcuml_pvalue p2value) +void drcuml_block_append_3(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condition, UINT8 flags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value, drcuml_ptype p2type, drcuml_pvalue p2value) { drcuml_instruction *inst = &block->inst[block->nextinst++]; @@ -616,7 +617,8 @@ void drcuml_block_append_3(drcuml_block *block, drcuml_opcode op, UINT8 size, UI /* fill in the instruction */ inst->opcode = (UINT8)op; inst->size = size; - inst->condflags = condflags; + inst->condition = condition; + inst->flags = flags; inst->numparams = 3; inst->param[0].type = p0type; inst->param[0].value = p0value; @@ -635,7 +637,7 @@ void drcuml_block_append_3(drcuml_block *block, drcuml_opcode op, UINT8 size, UI 4 parameters to the block -------------------------------------------------*/ -void drcuml_block_append_4(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condflags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value, drcuml_ptype p2type, drcuml_pvalue p2value, drcuml_ptype p3type, drcuml_pvalue p3value) +void drcuml_block_append_4(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condition, UINT8 flags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value, drcuml_ptype p2type, drcuml_pvalue p2value, drcuml_ptype p3type, drcuml_pvalue p3value) { drcuml_instruction *inst = &block->inst[block->nextinst++]; @@ -648,7 +650,8 @@ void drcuml_block_append_4(drcuml_block *block, drcuml_opcode op, UINT8 size, UI /* fill in the instruction */ inst->opcode = (UINT8)op; inst->size = size; - inst->condflags = condflags; + inst->condition = condition; + inst->flags = flags; inst->numparams = 4; inst->param[0].type = p0type; inst->param[0].value = p0value; @@ -877,7 +880,7 @@ void drcuml_add_comment(drcuml_block *block, const char *format, ...) strcpy(comment, buffer); /* add an instruction with a pointer */ - drcuml_block_append_1(block, DRCUML_OP_COMMENT, 4, DRCUML_COND_ALWAYS, MEM(comment)); + drcuml_block_append_1(block, DRCUML_OP_COMMENT, 4, DRCUML_COND_ALWAYS, 0, MEM(comment)); } @@ -1078,7 +1081,7 @@ static void bevalidate_iterate_over_params(drcuml_state *drcuml, drcuml_codehand static void bevalidate_iterate_over_flags(drcuml_state *drcuml, drcuml_codehandle **handles, const bevalidate_test *test, drcuml_parameter *paramlist) { const drcuml_opcode_valid *opvalid = &opcode_valid_table[test->opcode]; - UINT8 flagmask = opvalid->condflags & 0x1f; + UINT8 flagmask = opvalid->flags & 0x1f; UINT8 curmask; /* iterate over all possible flag combinations */ @@ -1125,23 +1128,23 @@ static void bevalidate_execute(drcuml_state *drcuml, drcuml_codehandle **handles switch (numparams) { case 0: - drcuml_block_append_0(block, test->opcode, test->size, flagmask); + drcuml_block_append_0(block, test->opcode, test->size, DRCUML_COND_ALWAYS, flagmask); break; case 1: - drcuml_block_append_1(block, test->opcode, test->size, flagmask, params[0].type, params[0].value); + drcuml_block_append_1(block, test->opcode, test->size, DRCUML_COND_ALWAYS, flagmask, params[0].type, params[0].value); break; case 2: - drcuml_block_append_2(block, test->opcode, test->size, flagmask, params[0].type, params[0].value, params[1].type, params[1].value); + drcuml_block_append_2(block, test->opcode, test->size, DRCUML_COND_ALWAYS, flagmask, params[0].type, params[0].value, params[1].type, params[1].value); break; case 3: - drcuml_block_append_3(block, test->opcode, test->size, flagmask, params[0].type, params[0].value, params[1].type, params[1].value, params[2].type, params[2].value); + drcuml_block_append_3(block, test->opcode, test->size, DRCUML_COND_ALWAYS, flagmask, params[0].type, params[0].value, params[1].type, params[1].value, params[2].type, params[2].value); break; case 4: - drcuml_block_append_4(block, test->opcode, test->size, flagmask, params[0].type, params[0].value, params[1].type, params[1].value, params[2].type, params[2].value, params[3].type, params[3].value); + drcuml_block_append_4(block, test->opcode, test->size, DRCUML_COND_ALWAYS, flagmask, params[0].type, params[0].value, params[1].type, params[1].value, params[2].type, params[2].value, params[3].type, params[3].value); break; } testinst = block->inst[block->nextinst - 1]; diff --git a/src/emu/cpu/drcuml.h b/src/emu/cpu/drcuml.h index a902165b8ba..36c1a71451a 100644 --- a/src/emu/cpu/drcuml.h +++ b/src/emu/cpu/drcuml.h @@ -313,7 +313,8 @@ typedef struct _drcuml_instruction drcuml_instruction; struct _drcuml_instruction { drcuml_opcode opcode; /* opcode */ - UINT8 condflags; /* condition or flags */ + UINT8 condition; /* condition */ + UINT8 flags; /* flags */ UINT8 size; /* operation size */ UINT8 numparams; /* number of parameters */ drcuml_parameter param[4]; /* up to 4 parameters */ @@ -418,11 +419,11 @@ void drcuml_free(drcuml_state *drcuml); drcuml_block *drcuml_block_begin(drcuml_state *drcuml, UINT32 maxinst, jmp_buf *errorbuf); /* append an opcode to the block, with 0-4 parameters */ -void drcuml_block_append_0(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condflags); -void drcuml_block_append_1(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condflags, drcuml_ptype p0type, drcuml_pvalue p0value); -void drcuml_block_append_2(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condflags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value); -void drcuml_block_append_3(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condflags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value, drcuml_ptype p2type, drcuml_pvalue p2value); -void drcuml_block_append_4(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condflags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value, drcuml_ptype p2type, drcuml_pvalue p2value, drcuml_ptype p3type, drcuml_pvalue p3value); +void drcuml_block_append_0(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condition, UINT8 flags); +void drcuml_block_append_1(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condition, UINT8 flags, drcuml_ptype p0type, drcuml_pvalue p0value); +void drcuml_block_append_2(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condition, UINT8 flags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value); +void drcuml_block_append_3(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condition, UINT8 flags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value, drcuml_ptype p2type, drcuml_pvalue p2value); +void drcuml_block_append_4(drcuml_block *block, drcuml_opcode op, UINT8 size, UINT8 condition, UINT8 flags, drcuml_ptype p0type, drcuml_pvalue p0value, drcuml_ptype p1type, drcuml_pvalue p1value, drcuml_ptype p2type, drcuml_pvalue p2value, drcuml_ptype p3type, drcuml_pvalue p3value); /* complete a code block and commit it to the cache via the back-end */ void drcuml_block_end(drcuml_block *block); diff --git a/src/emu/cpu/drcumld.c b/src/emu/cpu/drcumld.c index 5f034b761a3..88a2d38b5ac 100644 --- a/src/emu/cpu/drcumld.c +++ b/src/emu/cpu/drcumld.c @@ -245,29 +245,29 @@ void drcuml_disasm(const drcuml_instruction *inst, char *buffer) /* if we are outputting a condition but it's "always", skip it */ if (func == output_cond) { - if (inst->condflags == DRCUML_COND_ALWAYS) + if (inst->condition == DRCUML_COND_ALWAYS) continue; - param.value = inst->condflags; + param.value = inst->condition; } /* if we are outputting flags but they are "none", skip it */ else if (func == output_flags) { - if (inst->condflags == FLAGS_NONE) + if (inst->flags == FLAGS_NONE) continue; - param.value = inst->condflags; + param.value = inst->flags; } /* if we are outputting test/cmp flags but they are "all", skip it */ else if (func == output_flags_cmptest) { - if (inst->opcode == DRCUML_OP_CMP && inst->condflags == FLAGS_ALLI) + if (inst->opcode == DRCUML_OP_CMP && inst->flags == FLAGS_ALLI) continue; - if (inst->opcode == DRCUML_OP_FCMP && inst->condflags == FLAGS_ALLF) + if (inst->opcode == DRCUML_OP_FCMP && inst->flags == FLAGS_ALLF) continue; - if (inst->opcode == DRCUML_OP_TEST && inst->condflags == (FLAGS_S|FLAGS_Z)) + if (inst->opcode == DRCUML_OP_TEST && inst->flags == (FLAGS_S|FLAGS_Z)) continue; - param.value = inst->condflags; + param.value = inst->flags; } /* otherwise, we are fetching an actual parameter */ diff --git a/src/emu/cpu/drcumlsh.h b/src/emu/cpu/drcumlsh.h index 452b55ce319..87cc29cd040 100644 --- a/src/emu/cpu/drcumlsh.h +++ b/src/emu/cpu/drcumlsh.h @@ -95,257 +95,257 @@ ***************************************************************************/ /* ----- Compile-time Opcodes ----- */ -#define UML_HANDLE(block, handle) do { drcuml_block_append_1(block, DRCUML_OP_HANDLE, 4, IF_ALWAYS, MEM(handle)); } while (0) -#define UML_HASH(block, mode, pc) do { drcuml_block_append_2(block, DRCUML_OP_HASH, 4, IF_ALWAYS, IMM(mode), IMM(pc)); } while (0) -#define UML_LABEL(block, label) do { drcuml_block_append_1(block, DRCUML_OP_LABEL, 4, IF_ALWAYS, IMM(label)); } while (0) +#define UML_HANDLE(block, handle) do { drcuml_block_append_1(block, DRCUML_OP_HANDLE, 4, IF_ALWAYS, FLAGS_NONE, MEM(handle)); } while (0) +#define UML_HASH(block, mode, pc) do { drcuml_block_append_2(block, DRCUML_OP_HASH, 4, IF_ALWAYS, FLAGS_NONE, IMM(mode), IMM(pc)); } while (0) +#define UML_LABEL(block, label) do { drcuml_block_append_1(block, DRCUML_OP_LABEL, 4, IF_ALWAYS, FLAGS_NONE, IMM(label)); } while (0) #define UML_COMMENT/*(block, format, ...)*/ drcuml_add_comment -#define UML_MAPVAR(block, mapvar, value) do { drcuml_block_append_2(block, DRCUML_OP_MAPVAR, 4, IF_ALWAYS, mapvar, IMM(value)); } while (0) +#define UML_MAPVAR(block, mapvar, value) do { drcuml_block_append_2(block, DRCUML_OP_MAPVAR, 4, IF_ALWAYS, FLAGS_NONE, mapvar, IMM(value)); } while (0) /* ----- Control Flow Operations ----- */ -#define UML_DEBUG(block, pc) do { drcuml_block_append_1(block, DRCUML_OP_DEBUG, 4, IF_ALWAYS, pc); } while (0) +#define UML_DEBUG(block, pc) do { drcuml_block_append_1(block, DRCUML_OP_DEBUG, 4, IF_ALWAYS, FLAGS_NONE, pc); } while (0) -#define UML_EXIT(block, param) do { drcuml_block_append_1(block, DRCUML_OP_EXIT, 4, IF_ALWAYS, param); } while (0) -#define UML_EXITc(block, cond, param) do { drcuml_block_append_1(block, DRCUML_OP_EXIT, 4, cond, param); } while (0) +#define UML_EXIT(block, param) do { drcuml_block_append_1(block, DRCUML_OP_EXIT, 4, IF_ALWAYS, FLAGS_NONE, param); } while (0) +#define UML_EXITc(block, cond, param) do { drcuml_block_append_1(block, DRCUML_OP_EXIT, 4, cond, FLAGS_NONE, param); } while (0) -#define UML_HASHJMP(block, mode, pc, handle) do { drcuml_block_append_3(block, DRCUML_OP_HASHJMP, 4, IF_ALWAYS, mode, pc, MEM(handle)); } while (0) +#define UML_HASHJMP(block, mode, pc, handle) do { drcuml_block_append_3(block, DRCUML_OP_HASHJMP, 4, IF_ALWAYS, FLAGS_NONE, mode, pc, MEM(handle)); } while (0) -#define UML_JMP(block, label) do { drcuml_block_append_1(block, DRCUML_OP_JMP, 4, IF_ALWAYS, IMM(label)); } while (0) -#define UML_JMPc(block, cond, label) do { drcuml_block_append_1(block, DRCUML_OP_JMP, 4, cond, IMM(label)); } while (0) +#define UML_JMP(block, label) do { drcuml_block_append_1(block, DRCUML_OP_JMP, 4, IF_ALWAYS, FLAGS_NONE, IMM(label)); } while (0) +#define UML_JMPc(block, cond, label) do { drcuml_block_append_1(block, DRCUML_OP_JMP, 4, cond, FLAGS_NONE, IMM(label)); } while (0) -#define UML_JMPH(block, handle) do { drcuml_block_append_1(block, DRCUML_OP_JMPH, 4, IF_ALWAYS, MEM(handle)); } while (0) -#define UML_JMPHc(block, cond, handle) do { drcuml_block_append_1(block, DRCUML_OP_JMPH, 4, cond, MEM(handle)); } while (0) -#define UML_EXH(block, handle, param) do { drcuml_block_append_2(block, DRCUML_OP_EXH, 4, IF_ALWAYS, MEM(handle), param); } while (0) -#define UML_EXHc(block, cond, handle, param) do { drcuml_block_append_2(block, DRCUML_OP_EXH, 4, cond, MEM(handle), param); } while (0) -#define UML_CALLH(block, handle) do { drcuml_block_append_1(block, DRCUML_OP_CALLH, 4, IF_ALWAYS, MEM(handle)); } while (0) -#define UML_CALLHc(block, cond, handle) do { drcuml_block_append_1(block, DRCUML_OP_CALLH, 4, cond, MEM(handle)); } while (0) -#define UML_RET(block) do { drcuml_block_append_0(block, DRCUML_OP_RET, 4, IF_ALWAYS); } while (0) -#define UML_RETc(block, cond) do { drcuml_block_append_0(block, DRCUML_OP_RET, 4, cond); } while (0) +#define UML_JMPH(block, handle) do { drcuml_block_append_1(block, DRCUML_OP_JMPH, 4, IF_ALWAYS, FLAGS_NONE, MEM(handle)); } while (0) +#define UML_JMPHc(block, cond, handle) do { drcuml_block_append_1(block, DRCUML_OP_JMPH, 4, cond, FLAGS_NONE, MEM(handle)); } while (0) +#define UML_EXH(block, handle, param) do { drcuml_block_append_2(block, DRCUML_OP_EXH, 4, IF_ALWAYS, FLAGS_NONE, MEM(handle), param); } while (0) +#define UML_EXHc(block, cond, handle, param) do { drcuml_block_append_2(block, DRCUML_OP_EXH, 4, cond, FLAGS_NONE, MEM(handle), param); } while (0) +#define UML_CALLH(block, handle) do { drcuml_block_append_1(block, DRCUML_OP_CALLH, 4, IF_ALWAYS, FLAGS_NONE, MEM(handle)); } while (0) +#define UML_CALLHc(block, cond, handle) do { drcuml_block_append_1(block, DRCUML_OP_CALLH, 4, cond, FLAGS_NONE, MEM(handle)); } while (0) +#define UML_RET(block) do { drcuml_block_append_0(block, DRCUML_OP_RET, 4, IF_ALWAYS, FLAGS_NONE); } while (0) +#define UML_RETc(block, cond) do { drcuml_block_append_0(block, DRCUML_OP_RET, 4, cond, FLAGS_NONE); } while (0) -#define UML_CALLC(block, func, ptr) do { drcuml_block_append_2(block, DRCUML_OP_CALLC, 4, IF_ALWAYS, MEM(func), MEM(ptr)); } while (0) -#define UML_CALLCc(block, cond, func, ptr) do { drcuml_block_append_2(block, DRCUML_OP_CALLC, 4, cond, MEM(func), MEM(ptr)); } while (0) +#define UML_CALLC(block, func, ptr) do { drcuml_block_append_2(block, DRCUML_OP_CALLC, 4, IF_ALWAYS, FLAGS_NONE, MEM(func), MEM(ptr)); } while (0) +#define UML_CALLCc(block, cond, func, ptr) do { drcuml_block_append_2(block, DRCUML_OP_CALLC, 4, cond, FLAGS_NONE, MEM(func), MEM(ptr)); } while (0) -#define UML_RECOVER(block, dst, mapvar) do { drcuml_block_append_2(block, DRCUML_OP_RECOVER, 4, IF_ALWAYS, dst, mapvar); } while (0) +#define UML_RECOVER(block, dst, mapvar) do { drcuml_block_append_2(block, DRCUML_OP_RECOVER, 4, IF_ALWAYS, FLAGS_NONE, dst, mapvar); } while (0) /* ----- Internal Register Operations ----- */ -#define UML_SETFMOD(block, mode) do { drcuml_block_append_1(block, DRCUML_OP_SETFMOD, 4, IF_ALWAYS, mode); } while (0) -#define UML_GETFMOD(block, dst) do { drcuml_block_append_1(block, DRCUML_OP_GETFMOD, 4, IF_ALWAYS, dst); } while (0) -#define UML_GETEXP(block, dst) do { drcuml_block_append_1(block, DRCUML_OP_GETEXP, 4, IF_ALWAYS, dst); } while (0) -#define UML_GETFLGS(block, dst, flags) do { drcuml_block_append_1(block, DRCUML_OP_GETFLGS, 4, flags, dst); } while (0) -#define UML_SAVE(block, dst) do { drcuml_block_append_1(block, DRCUML_OP_SAVE, 4, IF_ALWAYS, MEM(dst)); } while (0) -#define UML_RESTORE(block, src) do { drcuml_block_append_1(block, DRCUML_OP_RESTORE, 4, IF_ALWAYS, MEM(src)); } while (0) +#define UML_SETFMOD(block, mode) do { drcuml_block_append_1(block, DRCUML_OP_SETFMOD, 4, IF_ALWAYS, FLAGS_NONE, mode); } while (0) +#define UML_GETFMOD(block, dst) do { drcuml_block_append_1(block, DRCUML_OP_GETFMOD, 4, IF_ALWAYS, FLAGS_NONE, dst); } while (0) +#define UML_GETEXP(block, dst) do { drcuml_block_append_1(block, DRCUML_OP_GETEXP, 4, IF_ALWAYS, FLAGS_NONE, dst); } while (0) +#define UML_GETFLGS(block, dst, flags) do { drcuml_block_append_1(block, DRCUML_OP_GETFLGS, 4, IF_ALWAYS, flags, dst); } while (0) +#define UML_SAVE(block, dst) do { drcuml_block_append_1(block, DRCUML_OP_SAVE, 4, IF_ALWAYS, FLAGS_NONE, MEM(dst)); } while (0) +#define UML_RESTORE(block, src) do { drcuml_block_append_1(block, DRCUML_OP_RESTORE, 4, IF_ALWAYS, FLAGS_NONE, MEM(src)); } while (0) /* ----- 32-Bit Integer Operations ----- */ -#define UML_LOAD(block, dst, base, index, size) do { drcuml_block_append_4(block, DRCUML_OP_LOAD, 4, IF_ALWAYS, dst, MEM(base), index, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_LOADS(block, dst, base, index, size) do { drcuml_block_append_4(block, DRCUML_OP_LOADS, 4, IF_ALWAYS, dst, MEM(base), index, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_STORE(block, base, index, src1, size) do { drcuml_block_append_4(block, DRCUML_OP_STORE, 4, IF_ALWAYS, MEM(base), index, src1, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_READ(block, dst, src1, spsize) do { drcuml_block_append_3(block, DRCUML_OP_READ, 4, IF_ALWAYS, dst, src1, IMM(DRCUML_SPSIZE_##spsize)); } while (0) -#define UML_READM(block, dst, src1, mask, spsize) do { drcuml_block_append_4(block, DRCUML_OP_READM, 4, IF_ALWAYS, dst, src1, mask, IMM(DRCUML_SPSIZE_##spsize)); } while (0) -#define UML_WRITE(block, dst, src1, spsize) do { drcuml_block_append_3(block, DRCUML_OP_WRITE, 4, IF_ALWAYS, dst, src1, IMM(DRCUML_SPSIZE_##spsize)); } while (0) -#define UML_WRITEM(block, dst, src1, mask, spsize) do { drcuml_block_append_4(block, DRCUML_OP_WRITEM, 4, IF_ALWAYS, dst, src1, mask, IMM(DRCUML_SPSIZE_##spsize)); } while (0) +#define UML_LOAD(block, dst, base, index, size) do { drcuml_block_append_4(block, DRCUML_OP_LOAD, 4, IF_ALWAYS, FLAGS_NONE, dst, MEM(base), index, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_LOADS(block, dst, base, index, size) do { drcuml_block_append_4(block, DRCUML_OP_LOADS, 4, IF_ALWAYS, FLAGS_NONE, dst, MEM(base), index, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_STORE(block, base, index, src1, size) do { drcuml_block_append_4(block, DRCUML_OP_STORE, 4, IF_ALWAYS, FLAGS_NONE, MEM(base), index, src1, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_READ(block, dst, src1, spsize) do { drcuml_block_append_3(block, DRCUML_OP_READ, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SPSIZE_##spsize)); } while (0) +#define UML_READM(block, dst, src1, mask, spsize) do { drcuml_block_append_4(block, DRCUML_OP_READM, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, mask, IMM(DRCUML_SPSIZE_##spsize)); } while (0) +#define UML_WRITE(block, dst, src1, spsize) do { drcuml_block_append_3(block, DRCUML_OP_WRITE, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SPSIZE_##spsize)); } while (0) +#define UML_WRITEM(block, dst, src1, mask, spsize) do { drcuml_block_append_4(block, DRCUML_OP_WRITEM, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, mask, IMM(DRCUML_SPSIZE_##spsize)); } while (0) -#define UML_CARRY(block, src, bitnum) do { drcuml_block_append_2(block, DRCUML_OP_CARRY, 4, IF_ALWAYS, src, bitnum); } while (0) -#define UML_SETc(block, cond, dst) do { drcuml_block_append_1(block, DRCUML_OP_SET, 4, cond, dst); } while (0) +#define UML_CARRY(block, src, bitnum) do { drcuml_block_append_2(block, DRCUML_OP_CARRY, 4, IF_ALWAYS, FLAGS_NONE, src, bitnum); } while (0) +#define UML_SETc(block, cond, dst) do { drcuml_block_append_1(block, DRCUML_OP_SET, 4, cond, FLAGS_NONE, dst); } while (0) -#define UML_MOV(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_MOV, 4, IF_ALWAYS, dst, src1); } while (0) -#define UML_MOVc(block, cond, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_MOV, 4, cond, dst, src1); } while (0) -#define UML_SEXT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_SEXT, 4, IF_ALWAYS, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_MOV(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_MOV, 4, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_MOVc(block, cond, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_MOV, 4, cond, FLAGS_NONE, dst, src1); } while (0) +#define UML_SEXT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_SEXT, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_ROLAND(block, dst, src, shift, mask) do { drcuml_block_append_4(block, DRCUML_OP_ROLAND, 4, IF_ALWAYS, dst, src, shift, mask); } while (0) -#define UML_ROLINS(block, dst, src, shift, mask) do { drcuml_block_append_4(block, DRCUML_OP_ROLINS, 4, IF_ALWAYS, dst, src, shift, mask); } while (0) +#define UML_ROLAND(block, dst, src, shift, mask) do { drcuml_block_append_4(block, DRCUML_OP_ROLAND, 4, IF_ALWAYS, FLAGS_NONE, dst, src, shift, mask); } while (0) +#define UML_ROLINS(block, dst, src, shift, mask) do { drcuml_block_append_4(block, DRCUML_OP_ROLINS, 4, IF_ALWAYS, FLAGS_NONE, dst, src, shift, mask); } while (0) -#define UML_NEG(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_NEG, 4, FLAGS_NONE, dst, src1); } while (0) -#define UML_NEGf(block, dst, src1, flags) do { drcuml_block_append_2(block, DRCUML_OP_NEG, 4, flags, dst, src1); } while (0) +#define UML_NEG(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_NEG, 4, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_NEGf(block, dst, src1, flags) do { drcuml_block_append_2(block, DRCUML_OP_NEG, 4, IF_ALWAYS, flags, dst, src1); } while (0) -#define UML_ADD(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_ADD, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_ADDf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_ADD, 4, flags, dst, src1, src2); } while (0) -#define UML_ADDC(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_ADDC, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_ADDCf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_ADDC, 4, flags, dst, src1, src2); } while (0) +#define UML_ADD(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_ADD, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_ADDf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_ADD, 4, IF_ALWAYS, flags, dst, src1, src2); } while (0) +#define UML_ADDC(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_ADDC, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_ADDCf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_ADDC, 4, IF_ALWAYS, flags, dst, src1, src2); } while (0) -#define UML_SUB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_SUB, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_SUBf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_SUB, 4, flags, dst, src1, src2); } while (0) -#define UML_SUBB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_SUBB, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_SUBBf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_SUBB, 4, flags, dst, src1, src2); } while (0) +#define UML_SUB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_SUB, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_SUBf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_SUB, 4, IF_ALWAYS, flags, dst, src1, src2); } while (0) +#define UML_SUBB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_SUBB, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_SUBBf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_SUBB, 4, IF_ALWAYS, flags, dst, src1, src2); } while (0) -#define UML_CMP(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_CMP, 4, FLAGS_ALLI, src1, src2); } while (0) -#define UML_CMPf(block, src1, src2, flags) do { drcuml_block_append_2(block, DRCUML_OP_CMP, 4, flags, src1, src2); } while (0) +#define UML_CMP(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_CMP, 4, IF_ALWAYS, FLAGS_ALLI, src1, src2); } while (0) +#define UML_CMPf(block, src1, src2, flags) do { drcuml_block_append_2(block, DRCUML_OP_CMP, 4, IF_ALWAYS, flags, src1, src2); } while (0) -#define UML_MULU(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_MULU, 4, FLAGS_NONE, dst, edst, src1, src2); } while (0) -#define UML_MULUf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_MULU, 4, flags, dst, edst, src1, src2); } while (0) -#define UML_MULS(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_MULS, 4, FLAGS_NONE, dst, edst, src1, src2); } while (0) -#define UML_MULSf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_MULS, 4, flags, dst, edst, src1, src2); } while (0) +#define UML_MULU(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_MULU, 4, IF_ALWAYS, FLAGS_NONE, dst, edst, src1, src2); } while (0) +#define UML_MULUf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_MULU, 4, IF_ALWAYS, flags, dst, edst, src1, src2); } while (0) +#define UML_MULS(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_MULS, 4, IF_ALWAYS, FLAGS_NONE, dst, edst, src1, src2); } while (0) +#define UML_MULSf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_MULS, 4, IF_ALWAYS, flags, dst, edst, src1, src2); } while (0) -#define UML_DIVU(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_DIVU, 4, FLAGS_NONE, dst, edst, src1, src2); } while (0) -#define UML_DIVUf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_DIVU, 4, flags, dst, edst, src1, src2); } while (0) -#define UML_DIVS(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_DIVS, 4, FLAGS_NONE, dst, edst, src1, src2); } while (0) -#define UML_DIVSf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_DIVS, 4, flags, dst, edst, src1, src2); } while (0) +#define UML_DIVU(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_DIVU, 4, IF_ALWAYS, FLAGS_NONE, dst, edst, src1, src2); } while (0) +#define UML_DIVUf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_DIVU, 4, IF_ALWAYS, flags, dst, edst, src1, src2); } while (0) +#define UML_DIVS(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_DIVS, 4, IF_ALWAYS, FLAGS_NONE, dst, edst, src1, src2); } while (0) +#define UML_DIVSf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_DIVS, 4, IF_ALWAYS, flags, dst, edst, src1, src2); } while (0) -#define UML_AND(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_AND, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_ANDf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_AND, 4, flags, dst, src1, src2); } while (0) +#define UML_AND(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_AND, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_ANDf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_AND, 4, IF_ALWAYS, flags, dst, src1, src2); } while (0) -#define UML_TEST(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_TEST, 4, FLAGS_S|FLAGS_Z,src1, src2); } while (0) -#define UML_TESTf(block, src1, src2, flags) do { drcuml_block_append_2(block, DRCUML_OP_TEST, 4, flags, src1, src2); } while (0) +#define UML_TEST(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_TEST, 4, IF_ALWAYS, FLAGS_S|FLAGS_Z,src1, src2); } while (0) +#define UML_TESTf(block, src1, src2, flags) do { drcuml_block_append_2(block, DRCUML_OP_TEST, 4, IF_ALWAYS, flags, src1, src2); } while (0) -#define UML_OR(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_OR, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_ORf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_OR, 4, flags, dst, src1, src2); } while (0) +#define UML_OR(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_OR, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_ORf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_OR, 4, IF_ALWAYS, flags, dst, src1, src2); } while (0) -#define UML_XOR(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_XOR, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_XORf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_XOR, 4, flags, dst, src1, src2); } while (0) +#define UML_XOR(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_XOR, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_XORf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_XOR, 4, IF_ALWAYS, flags, dst, src1, src2); } while (0) -#define UML_LZCNT(block, dst, src) do { drcuml_block_append_2(block, DRCUML_OP_LZCNT, 4, FLAGS_NONE, dst, src); } while (0) -#define UML_BSWAP(block, dst, src) do { drcuml_block_append_2(block, DRCUML_OP_BSWAP, 4, FLAGS_NONE, dst, src); } while (0) +#define UML_LZCNT(block, dst, src) do { drcuml_block_append_2(block, DRCUML_OP_LZCNT, 4, IF_ALWAYS, FLAGS_NONE, dst, src); } while (0) +#define UML_BSWAP(block, dst, src) do { drcuml_block_append_2(block, DRCUML_OP_BSWAP, 4, IF_ALWAYS, FLAGS_NONE, dst, src); } while (0) -#define UML_SHL(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SHL, 4, FLAGS_NONE, dst, src, count); } while (0) -#define UML_SHLf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SHL, 4, flags, dst, src, count); } while (0) +#define UML_SHL(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SHL, 4, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_SHLf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SHL, 4, IF_ALWAYS, flags, dst, src, count); } while (0) -#define UML_SHR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SHR, 4, FLAGS_NONE, dst, src, count); } while (0) -#define UML_SHRf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SHR, 4, flags, dst, src, count); } while (0) +#define UML_SHR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SHR, 4, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_SHRf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SHR, 4, IF_ALWAYS, flags, dst, src, count); } while (0) -#define UML_SAR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SAR, 4, FLAGS_NONE, dst, src, count); } while (0) -#define UML_SARf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SAR, 4, flags, dst, src, count); } while (0) +#define UML_SAR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SAR, 4, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_SARf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SAR, 4, IF_ALWAYS, flags, dst, src, count); } while (0) -#define UML_ROL(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROL, 4, FLAGS_NONE, dst, src, count); } while (0) -#define UML_ROLf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROL, 4, flags, dst, src, count); } while (0) -#define UML_ROLC(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROLC, 4, FLAGS_NONE, dst, src, count); } while (0) -#define UML_ROLCf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROLC, 4, flags, dst, src, count); } while (0) +#define UML_ROL(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROL, 4, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_ROLf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROL, 4, IF_ALWAYS, flags, dst, src, count); } while (0) +#define UML_ROLC(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROLC, 4, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_ROLCf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROLC, 4, IF_ALWAYS, flags, dst, src, count); } while (0) -#define UML_ROR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROR, 4, FLAGS_NONE, dst, src, count); } while (0) -#define UML_RORf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROR, 4, flags, dst, src, count); } while (0) -#define UML_RORC(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_RORC, 4, FLAGS_NONE, dst, src, count); } while (0) -#define UML_RORCf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_RORC, 4, flags, dst, src, count); } while (0) +#define UML_ROR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROR, 4, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_RORf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROR, 4, IF_ALWAYS, flags, dst, src, count); } while (0) +#define UML_RORC(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_RORC, 4, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_RORCf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_RORC, 4, IF_ALWAYS, flags, dst, src, count); } while (0) /* ----- 64-Bit Integer Operations ----- */ -#define UML_DLOAD(block, dst, base, index, size) do { drcuml_block_append_4(block, DRCUML_OP_LOAD, 8, IF_ALWAYS, dst, MEM(base), index, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_DLOADS(block, dst, base, index, size) do { drcuml_block_append_4(block, DRCUML_OP_LOADS, 8, IF_ALWAYS, dst, MEM(base), index, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_DSTORE(block, base, index, src1, size) do { drcuml_block_append_4(block, DRCUML_OP_STORE, 8, IF_ALWAYS, MEM(base), index, src1, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_DREAD(block, dst, src1, spsize) do { drcuml_block_append_3(block, DRCUML_OP_READ, 8, IF_ALWAYS, dst, src1, IMM(DRCUML_SPSIZE_##spsize)); } while (0) -#define UML_DREADM(block, dst, src1, mask, spsize) do { drcuml_block_append_4(block, DRCUML_OP_READM, 8, IF_ALWAYS, dst, src1, mask, IMM(DRCUML_SPSIZE_##spsize)); } while (0) -#define UML_DWRITE(block, dst, src1, spsize) do { drcuml_block_append_3(block, DRCUML_OP_WRITE, 8, IF_ALWAYS, dst, src1, IMM(DRCUML_SPSIZE_##spsize)); } while (0) -#define UML_DWRITEM(block, dst, src1, mask, spsize) do { drcuml_block_append_4(block, DRCUML_OP_WRITEM, 8, IF_ALWAYS, dst, src1, mask, IMM(DRCUML_SPSIZE_##spsize)); } while (0) +#define UML_DLOAD(block, dst, base, index, size) do { drcuml_block_append_4(block, DRCUML_OP_LOAD, 8, IF_ALWAYS, FLAGS_NONE, dst, MEM(base), index, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_DLOADS(block, dst, base, index, size) do { drcuml_block_append_4(block, DRCUML_OP_LOADS, 8, IF_ALWAYS, FLAGS_NONE, dst, MEM(base), index, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_DSTORE(block, base, index, src1, size) do { drcuml_block_append_4(block, DRCUML_OP_STORE, 8, IF_ALWAYS, FLAGS_NONE, MEM(base), index, src1, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_DREAD(block, dst, src1, spsize) do { drcuml_block_append_3(block, DRCUML_OP_READ, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SPSIZE_##spsize)); } while (0) +#define UML_DREADM(block, dst, src1, mask, spsize) do { drcuml_block_append_4(block, DRCUML_OP_READM, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, mask, IMM(DRCUML_SPSIZE_##spsize)); } while (0) +#define UML_DWRITE(block, dst, src1, spsize) do { drcuml_block_append_3(block, DRCUML_OP_WRITE, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SPSIZE_##spsize)); } while (0) +#define UML_DWRITEM(block, dst, src1, mask, spsize) do { drcuml_block_append_4(block, DRCUML_OP_WRITEM, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, mask, IMM(DRCUML_SPSIZE_##spsize)); } while (0) -#define UML_DCARRY(block, src, bitnum) do { drcuml_block_append_2(block, DRCUML_OP_CARRY, 8, IF_ALWAYS, src, bitnum); } while (0) -#define UML_DSETc(block, cond, dst) do { drcuml_block_append_1(block, DRCUML_OP_SET, 8, cond, dst); } while (0) +#define UML_DCARRY(block, src, bitnum) do { drcuml_block_append_2(block, DRCUML_OP_CARRY, 8, IF_ALWAYS, FLAGS_NONE, src, bitnum); } while (0) +#define UML_DSETc(block, cond, dst) do { drcuml_block_append_1(block, DRCUML_OP_SET, 8, cond, FLAGS_NONE, dst); } while (0) -#define UML_DMOV(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_MOV, 8, IF_ALWAYS, dst, src1); } while (0) -#define UML_DMOVc(block, cond, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_MOV, 8, cond, dst, src1); } while (0) -#define UML_DSEXT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_SEXT, 8, IF_ALWAYS, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_DMOV(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_MOV, 8, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_DMOVc(block, cond, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_MOV, 8, cond, FLAGS_NONE, dst, src1); } while (0) +#define UML_DSEXT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_SEXT, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_DROLAND(block, dst, src, shift, mask) do { drcuml_block_append_4(block, DRCUML_OP_ROLAND, 8, IF_ALWAYS, dst, src, shift, mask); } while (0) -#define UML_DROLINS(block, dst, src, shift, mask) do { drcuml_block_append_4(block, DRCUML_OP_ROLINS, 8, IF_ALWAYS, dst, src, shift, mask); } while (0) +#define UML_DROLAND(block, dst, src, shift, mask) do { drcuml_block_append_4(block, DRCUML_OP_ROLAND, 8, IF_ALWAYS, FLAGS_NONE, dst, src, shift, mask); } while (0) +#define UML_DROLINS(block, dst, src, shift, mask) do { drcuml_block_append_4(block, DRCUML_OP_ROLINS, 8, IF_ALWAYS, FLAGS_NONE, dst, src, shift, mask); } while (0) -#define UML_DNEG(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_NEG, 8, FLAGS_NONE, dst, src1); } while (0) -#define UML_DNEGf(block, dst, src1, flags) do { drcuml_block_append_2(block, DRCUML_OP_NEG, 8, flags, dst, src1); } while (0) +#define UML_DNEG(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_NEG, 8, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_DNEGf(block, dst, src1, flags) do { drcuml_block_append_2(block, DRCUML_OP_NEG, 8, IF_ALWAYS, flags, dst, src1); } while (0) -#define UML_DADD(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_ADD, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_DADDf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_ADD, 8, flags, dst, src1, src2); } while (0) -#define UML_DADDC(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_ADDC, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_DADDCf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_ADDC, 8, flags, dst, src1, src2); } while (0) +#define UML_DADD(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_ADD, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_DADDf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_ADD, 8, IF_ALWAYS, flags, dst, src1, src2); } while (0) +#define UML_DADDC(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_ADDC, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_DADDCf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_ADDC, 8, IF_ALWAYS, flags, dst, src1, src2); } while (0) -#define UML_DSUB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_SUB, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_DSUBf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_SUB, 8, flags, dst, src1, src2); } while (0) -#define UML_DSUBB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_SUBB, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_DSUBBf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_SUBB, 8, flags, dst, src1, src2); } while (0) +#define UML_DSUB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_SUB, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_DSUBf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_SUB, 8, IF_ALWAYS, flags, dst, src1, src2); } while (0) +#define UML_DSUBB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_SUBB, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_DSUBBf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_SUBB, 8, IF_ALWAYS, flags, dst, src1, src2); } while (0) -#define UML_DCMP(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_CMP, 8, FLAGS_ALLI, src1, src2); } while (0) -#define UML_DCMPf(block, src1, src2, flags) do { drcuml_block_append_2(block, DRCUML_OP_CMP, 8, flags, src1, src2); } while (0) +#define UML_DCMP(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_CMP, 8, IF_ALWAYS, FLAGS_ALLI, src1, src2); } while (0) +#define UML_DCMPf(block, src1, src2, flags) do { drcuml_block_append_2(block, DRCUML_OP_CMP, 8, IF_ALWAYS, flags, src1, src2); } while (0) -#define UML_DMULU(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_MULU, 8, FLAGS_NONE, dst, edst, src1, src2); } while (0) -#define UML_DMULUf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_MULU, 8, flags, dst, edst, src1, src2); } while (0) -#define UML_DMULS(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_MULS, 8, FLAGS_NONE, dst, edst, src1, src2); } while (0) -#define UML_DMULSf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_MULS, 8, flags, dst, edst, src1, src2); } while (0) +#define UML_DMULU(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_MULU, 8, IF_ALWAYS, FLAGS_NONE, dst, edst, src1, src2); } while (0) +#define UML_DMULUf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_MULU, 8, IF_ALWAYS, flags, dst, edst, src1, src2); } while (0) +#define UML_DMULS(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_MULS, 8, IF_ALWAYS, FLAGS_NONE, dst, edst, src1, src2); } while (0) +#define UML_DMULSf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_MULS, 8, IF_ALWAYS, flags, dst, edst, src1, src2); } while (0) -#define UML_DDIVU(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_DIVU, 8, FLAGS_NONE, dst, edst, src1, src2); } while (0) -#define UML_DDIVUf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_DIVU, 8, flags, dst, edst, src1, src2); } while (0) -#define UML_DDIVS(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_DIVS, 8, FLAGS_NONE, dst, edst, src1, src2); } while (0) -#define UML_DDIVSf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_DIVS, 8, flags, dst, edst, src1, src2); } while (0) +#define UML_DDIVU(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_DIVU, 8, IF_ALWAYS, FLAGS_NONE, dst, edst, src1, src2); } while (0) +#define UML_DDIVUf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_DIVU, 8, IF_ALWAYS, flags, dst, edst, src1, src2); } while (0) +#define UML_DDIVS(block, dst, edst, src1, src2) do { drcuml_block_append_4(block, DRCUML_OP_DIVS, 8, IF_ALWAYS, FLAGS_NONE, dst, edst, src1, src2); } while (0) +#define UML_DDIVSf(block, dst, edst, src1, src2, flags) do { drcuml_block_append_4(block, DRCUML_OP_DIVS, 8, IF_ALWAYS, flags, dst, edst, src1, src2); } while (0) -#define UML_DAND(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_AND, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_DANDf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_AND, 8, flags, dst, src1, src2); } while (0) +#define UML_DAND(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_AND, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_DANDf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_AND, 8, IF_ALWAYS, flags, dst, src1, src2); } while (0) -#define UML_DTEST(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_TEST, 8, FLAGS_S|FLAGS_Z,src1, src2); } while (0) -#define UML_DTESTf(block, src1, src2, flags) do { drcuml_block_append_2(block, DRCUML_OP_TEST, 8, flags, src1, src2); } while (0) +#define UML_DTEST(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_TEST, 8, IF_ALWAYS, FLAGS_S|FLAGS_Z,src1, src2); } while (0) +#define UML_DTESTf(block, src1, src2, flags) do { drcuml_block_append_2(block, DRCUML_OP_TEST, 8, IF_ALWAYS, flags, src1, src2); } while (0) -#define UML_DOR(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_OR, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_DORf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_OR, 8, flags, dst, src1, src2); } while (0) +#define UML_DOR(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_OR, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_DORf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_OR, 8, IF_ALWAYS, flags, dst, src1, src2); } while (0) -#define UML_DXOR(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_XOR, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_DXORf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_XOR, 8, flags, dst, src1, src2); } while (0) +#define UML_DXOR(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_XOR, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_DXORf(block, dst, src1, src2, flags) do { drcuml_block_append_3(block, DRCUML_OP_XOR, 8, IF_ALWAYS, flags, dst, src1, src2); } while (0) -#define UML_DSHL(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SHL, 8, FLAGS_NONE, dst, src, count); } while (0) -#define UML_DSHLf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SHL, 8, flags, dst, src, count); } while (0) +#define UML_DSHL(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SHL, 8, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_DSHLf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SHL, 8, IF_ALWAYS, flags, dst, src, count); } while (0) -#define UML_DSHR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SHR, 8, FLAGS_NONE, dst, src, count); } while (0) -#define UML_DSHRf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SHR, 8, flags, dst, src, count); } while (0) +#define UML_DSHR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SHR, 8, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_DSHRf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SHR, 8, IF_ALWAYS, flags, dst, src, count); } while (0) -#define UML_DSAR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SAR, 8, FLAGS_NONE, dst, src, count); } while (0) -#define UML_DSARf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SAR, 8, flags, dst, src, count); } while (0) +#define UML_DSAR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_SAR, 8, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_DSARf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_SAR, 8, IF_ALWAYS, flags, dst, src, count); } while (0) -#define UML_DROL(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROL, 8, FLAGS_NONE, dst, src, count); } while (0) -#define UML_DROLf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROL, 8, flags, dst, src, count); } while (0) -#define UML_DROLC(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROLC, 8, FLAGS_NONE, dst, src, count); } while (0) -#define UML_DROLCf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROLC, 8, flags, dst, src, count); } while (0) +#define UML_DROL(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROL, 8, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_DROLf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROL, 8, IF_ALWAYS, flags, dst, src, count); } while (0) +#define UML_DROLC(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROLC, 8, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_DROLCf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROLC, 8, IF_ALWAYS, flags, dst, src, count); } while (0) -#define UML_DROR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROR, 8, FLAGS_NONE, dst, src, count); } while (0) -#define UML_DRORf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROR, 8, flags, dst, src, count); } while (0) -#define UML_DRORC(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_RORC, 8, FLAGS_NONE, dst, src, count); } while (0) -#define UML_DRORCf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_RORC, 8, flags, dst, src, count); } while (0) +#define UML_DROR(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_ROR, 8, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_DRORf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_ROR, 8, IF_ALWAYS, flags, dst, src, count); } while (0) +#define UML_DRORC(block, dst, src, count) do { drcuml_block_append_3(block, DRCUML_OP_RORC, 8, IF_ALWAYS, FLAGS_NONE, dst, src, count); } while (0) +#define UML_DRORCf(block, dst, src, count, flags) do { drcuml_block_append_3(block, DRCUML_OP_RORC, 8, IF_ALWAYS, flags, dst, src, count); } while (0) /* ----- 32-bit Floating Point Arithmetic Operations ----- */ -#define UML_FSLOAD(block, dst, base, index) do { drcuml_block_append_3(block, DRCUML_OP_FLOAD, 4, IF_ALWAYS, dst, MEM(base), index); } while (0) -#define UML_FSSTORE(block, base, index, src1) do { drcuml_block_append_3(block, DRCUML_OP_FSTORE, 4, IF_ALWAYS, MEM(base), index, src1); } while (0) +#define UML_FSLOAD(block, dst, base, index) do { drcuml_block_append_3(block, DRCUML_OP_FLOAD, 4, IF_ALWAYS, FLAGS_NONE, dst, MEM(base), index); } while (0) +#define UML_FSSTORE(block, base, index, src1) do { drcuml_block_append_3(block, DRCUML_OP_FSTORE, 4, IF_ALWAYS, FLAGS_NONE, MEM(base), index, src1); } while (0) -#define UML_FSREAD(block, dst, src1, space) do { drcuml_block_append_3(block, DRCUML_OP_FREAD, 4, IF_ALWAYS, dst, src1, IMM(ADDRESS_SPACE_##space)); } while (0) -#define UML_FSWRITE(block, dst, src1, space) do { drcuml_block_append_3(block, DRCUML_OP_FWRITE, 4, IF_ALWAYS, dst, src1, IMM(ADDRESS_SPACE_##space)); } while (0) +#define UML_FSREAD(block, dst, src1, space) do { drcuml_block_append_3(block, DRCUML_OP_FREAD, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(ADDRESS_SPACE_##space)); } while (0) +#define UML_FSWRITE(block, dst, src1, space) do { drcuml_block_append_3(block, DRCUML_OP_FWRITE, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(ADDRESS_SPACE_##space)); } while (0) -#define UML_FSMOV(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FMOV, 4, IF_ALWAYS, dst, src1); } while (0) -#define UML_FSMOVc(block, cond, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FMOV, 4, cond, dst, src1); } while (0) +#define UML_FSMOV(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FMOV, 4, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_FSMOVc(block, cond, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FMOV, 4, cond, FLAGS_NONE, dst, src1); } while (0) -#define UML_FSTOINT(block, dst, src1, size, round) do { drcuml_block_append_4(block, DRCUML_OP_FTOINT, 4, IF_ALWAYS, dst, src1, IMM(DRCUML_SIZE_##size), IMM(DRCUML_FMOD_##round)); } while (0) -#define UML_FSFRINT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_FFRINT, 4, IF_ALWAYS, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_FSFRFLT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_FFRFLT, 4, IF_ALWAYS, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_FSTOINT(block, dst, src1, size, round) do { drcuml_block_append_4(block, DRCUML_OP_FTOINT, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SIZE_##size), IMM(DRCUML_FMOD_##round)); } while (0) +#define UML_FSFRINT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_FFRINT, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_FSFRFLT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_FFRFLT, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_FSADD(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FADD, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_FSSUB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FSUB, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_FSCMP(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_FCMP, 4, FLAGS_ALLF, src1, src2); } while (0) -#define UML_FSMUL(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FMUL, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_FSDIV(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FDIV, 4, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_FSNEG(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FNEG, 4, FLAGS_NONE, dst, src1); } while (0) -#define UML_FSABS(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FABS, 4, FLAGS_NONE, dst, src1); } while (0) -#define UML_FSSQRT(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FSQRT, 4, FLAGS_NONE, dst, src1); } while (0) -#define UML_FSRECIP(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FRECIP, 4, FLAGS_NONE, dst, src1); } while (0) -#define UML_FSRSQRT(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FRSQRT, 4, FLAGS_NONE, dst, src1); } while (0) +#define UML_FSADD(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FADD, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_FSSUB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FSUB, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_FSCMP(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_FCMP, 4, IF_ALWAYS, FLAGS_ALLF, src1, src2); } while (0) +#define UML_FSMUL(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FMUL, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_FSDIV(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FDIV, 4, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_FSNEG(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FNEG, 4, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_FSABS(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FABS, 4, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_FSSQRT(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FSQRT, 4, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_FSRECIP(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FRECIP, 4, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_FSRSQRT(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FRSQRT, 4, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) /* ----- 64-bit Floating Point Arithmetic Operations ----- */ -#define UML_FDLOAD(block, dst, base, index) do { drcuml_block_append_3(block, DRCUML_OP_FLOAD, 8, IF_ALWAYS, dst, MEM(base), index); } while (0) -#define UML_FDSTORE(block, base, index, src1) do { drcuml_block_append_3(block, DRCUML_OP_FSTORE, 8, IF_ALWAYS, MEM(base), index, src1); } while (0) - -#define UML_FDREAD(block, dst, src1, space) do { drcuml_block_append_3(block, DRCUML_OP_FREAD, 8, IF_ALWAYS, dst, src1, IMM(ADDRESS_SPACE_##space)); } while (0) -#define UML_FDWRITE(block, dst, src1, space) do { drcuml_block_append_3(block, DRCUML_OP_FWRITE, 8, IF_ALWAYS, dst, src1, IMM(ADDRESS_SPACE_##space)); } while (0) - -#define UML_FDMOV(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FMOV, 8, IF_ALWAYS, dst, src1); } while (0) -#define UML_FDMOVc(block, cond, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FMOV, 8, cond, dst, src1); } while (0) - -#define UML_FDTOINT(block, dst, src1, size, round) do { drcuml_block_append_4(block, DRCUML_OP_FTOINT, 8, IF_ALWAYS, dst, src1, IMM(DRCUML_SIZE_##size), IMM(DRCUML_FMOD_##round)); } while (0) -#define UML_FDFRINT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_FFRINT, 8, IF_ALWAYS, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) -#define UML_FDFRFLT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_FFRFLT, 8, IF_ALWAYS, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) - -#define UML_FDRNDS(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FRNDS, 8, FLAGS_NONE, dst, src1); } while (0) - -#define UML_FDADD(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FADD, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_FDSUB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FSUB, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_FDCMP(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_FCMP, 8, FLAGS_ALLF, src1, src2); } while (0) -#define UML_FDMUL(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FMUL, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_FDDIV(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FDIV, 8, FLAGS_NONE, dst, src1, src2); } while (0) -#define UML_FDNEG(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FNEG, 8, FLAGS_NONE, dst, src1); } while (0) -#define UML_FDABS(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FABS, 8, FLAGS_NONE, dst, src1); } while (0) -#define UML_FDSQRT(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FSQRT, 8, FLAGS_NONE, dst, src1); } while (0) -#define UML_FDRECIP(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FRECIP, 8, FLAGS_NONE, dst, src1); } while (0) -#define UML_FDRSQRT(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FRSQRT, 8, FLAGS_NONE, dst, src1); } while (0) +#define UML_FDLOAD(block, dst, base, index) do { drcuml_block_append_3(block, DRCUML_OP_FLOAD, 8, IF_ALWAYS, FLAGS_NONE, dst, MEM(base), index); } while (0) +#define UML_FDSTORE(block, base, index, src1) do { drcuml_block_append_3(block, DRCUML_OP_FSTORE, 8, IF_ALWAYS, FLAGS_NONE, MEM(base), index, src1); } while (0) + +#define UML_FDREAD(block, dst, src1, space) do { drcuml_block_append_3(block, DRCUML_OP_FREAD, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(ADDRESS_SPACE_##space)); } while (0) +#define UML_FDWRITE(block, dst, src1, space) do { drcuml_block_append_3(block, DRCUML_OP_FWRITE, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(ADDRESS_SPACE_##space)); } while (0) + +#define UML_FDMOV(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FMOV, 8, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_FDMOVc(block, cond, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FMOV, 8, cond, FLAGS_NONE, dst, src1); } while (0) + +#define UML_FDTOINT(block, dst, src1, size, round) do { drcuml_block_append_4(block, DRCUML_OP_FTOINT, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SIZE_##size), IMM(DRCUML_FMOD_##round)); } while (0) +#define UML_FDFRINT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_FFRINT, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) +#define UML_FDFRFLT(block, dst, src1, size) do { drcuml_block_append_3(block, DRCUML_OP_FFRFLT, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, IMM(DRCUML_SIZE_##size)); } while (0) + +#define UML_FDRNDS(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FRNDS, 8, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) + +#define UML_FDADD(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FADD, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_FDSUB(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FSUB, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_FDCMP(block, src1, src2) do { drcuml_block_append_2(block, DRCUML_OP_FCMP, 8, IF_ALWAYS, FLAGS_ALLF, src1, src2); } while (0) +#define UML_FDMUL(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FMUL, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_FDDIV(block, dst, src1, src2) do { drcuml_block_append_3(block, DRCUML_OP_FDIV, 8, IF_ALWAYS, FLAGS_NONE, dst, src1, src2); } while (0) +#define UML_FDNEG(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FNEG, 8, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_FDABS(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FABS, 8, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_FDSQRT(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FSQRT, 8, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_FDRECIP(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FRECIP, 8, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) +#define UML_FDRSQRT(block, dst, src1) do { drcuml_block_append_2(block, DRCUML_OP_FRSQRT, 8, IF_ALWAYS, FLAGS_NONE, dst, src1); } while (0) #endif |