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author Joakim Larsson Edström <joakimlarsson42@gmail.com>2017-01-20 01:37:11 +0100
committer GitHub <noreply@github.com>2017-01-20 01:37:11 +0100
commitd125a1c0a841d25a511275e091103eb1b29687c0 (patch)
tree5c2ac09029be3defe15b202383b6c36217aa0278
parent43ece2178b4bd1f55c40dbf5d0c919b7c4cb01a8 (diff)
parente0b8d253dc4f21dc23fad86466899fea8be57b05 (diff)
Merge pull request #2004 from JoakimLarsson/fccpu20
New working board: Fccpu20
-rw-r--r--src/devices/machine/68561mpcc.cpp157
-rw-r--r--src/devices/machine/68561mpcc.h20
-rw-r--r--src/mame/drivers/fccpu20.cpp249
3 files changed, 357 insertions, 69 deletions
diff --git a/src/devices/machine/68561mpcc.cpp b/src/devices/machine/68561mpcc.cpp
index fa0f9b6ce0b..c07216fd640 100644
--- a/src/devices/machine/68561mpcc.cpp
+++ b/src/devices/machine/68561mpcc.cpp
@@ -55,6 +55,7 @@ FEATURES
#define LOG_DCD 0x200
#define LOG_SYNC 0x400
#define LOG_CHAR 0x800
+#define LOG_RX 0x1000
#define VERBOSE 0 // (LOG_PRINTF | LOG_SETUP | LOG_GENERAL)
@@ -72,6 +73,7 @@ FEATURES
#define LOGDCD(...) LOGMASK(LOG_DCD, __VA_ARGS__)
#define LOGSYNC(...) LOGMASK(LOG_SYNC, __VA_ARGS__)
#define LOGCHAR(...) LOGMASK(LOG_CHAR, __VA_ARGS__)
+#define LOGRX(...) LOGMASK(LOG_RX, __VA_ARGS__)
#if VERBOSE & LOG_PRINTF
#define logerror printf
@@ -274,6 +276,10 @@ void mpcc_device::device_reset()
m_ccr = 0x00;
m_ecr = 0x04;
+ // Clear fifos
+ m_tx_data_fifo.clear();
+ m_rx_data_fifo.clear();
+
// Init out callbacks to known inactive state
m_out_txd_cb(1);
m_out_dtr_cb(1);
@@ -292,6 +298,76 @@ void mpcc_device::device_timer(emu_timer &timer, device_timer_id id, int param,
device_serial_interface::device_timer(timer, id, param, ptr);
}
+WRITE_LINE_MEMBER(mpcc_device::cts_w)
+{
+ if (state == CLEAR_LINE)
+ {
+ uint8_t old_sisr = m_sisr;
+
+ m_sisr &= ~REG_SISR_CTSLVL;
+ if ( (old_sisr & REG_SISR_CTSLVL) &&
+ (m_sicr & REG_SICR_RTSLVL) &&
+ (m_tcr & REG_TCR_TEN))
+ {
+ m_sisr |= REG_SISR_CTST;
+ if (m_sier & REG_SIER_CTS)
+ {
+ // TODO: make sure interrupt is issued with the next negative transition of TxC
+ trigger_interrupt(INT_SR_CTS);
+ // TODO: Make sure TxC has negative transition after CTS goes inactive before INT can be reset in SISR7
+ }
+ }
+ }
+ else
+ m_sisr |= REG_SISR_CTSLVL;
+}
+
+WRITE_LINE_MEMBER(mpcc_device::dsr_w)
+{
+ if (state == ASSERT_LINE)
+ {
+ uint8_t old_sisr = m_sisr;
+
+ m_sisr |= REG_SISR_DSRLVL;
+ if ( !(old_sisr & REG_SISR_DSRLVL) &&
+ !(m_rcr & REG_RCR_RRES))
+ {
+ m_sisr |= REG_SISR_DSRT;
+ if (m_sier & REG_SIER_DSR)
+ {
+ // TODO: make sure interrupt is issued with the next negative transition of RxC
+ trigger_interrupt(INT_SR_DSR);
+ // TODO: Make sure RxC has negative transition after DSR goes inactive before INT can be reset in SISR6
+ }
+ }
+ }
+ else
+ m_sisr &= ~REG_SISR_DSRLVL;
+}
+
+WRITE_LINE_MEMBER(mpcc_device::dcd_w)
+{
+ if (state == CLEAR_LINE)
+ {
+ uint8_t old_sisr = m_sisr;
+
+ m_sisr &= ~REG_SISR_DCDLVL;
+ if ( (old_sisr & REG_SISR_DCDLVL) &&
+ !(m_rcr & REG_RCR_RRES))
+ {
+ m_sisr |= REG_SISR_DCDT;
+ if (m_sier & REG_SIER_DCD)
+ {
+ // TODO: make sure interrupt is issued with the next negative transition of RxC
+ trigger_interrupt(INT_SR_DCD);
+ // TODO: Make sure RxC has negative transition before INT can be reset in SISR5
+ }
+ }
+ }
+ else
+ m_sisr |= REG_SISR_DCDLVL;
+}
+
//-------------------------------------------------
// get_brg_rate - helper function
//-------------------------------------------------
@@ -430,7 +506,7 @@ void mpcc_device::update_serial()
parity_t parity = get_parity();
LOGSETUP(" %s() %s Setting data frame %d+%d%c%s\n", FUNCNAME, m_owner->tag(), 1,
- data_bits, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O',
+ data_bits, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O',
stop_bits == STOP_BITS_1 ? "1" : (stop_bits == STOP_BITS_2 ? "2" : "1.5"));
set_data_frame(1, data_bits, parity, stop_bits);
@@ -439,16 +515,16 @@ void mpcc_device::update_serial()
// check if the receiver is in reset mode
if (m_rcr & REG_RCR_RRES)
{
- LOG("- Rx in reset\n");
+ LOGSETUP("- Rx in reset\n");
set_rcv_rate(0);
}
// Rx is running
else
{
- LOG("- Rx enabled\n");
+ LOGSETUP("- Rx enabled\n");
m_brg_rate = get_rx_rate();
- LOG("- BRG rate %d\n", m_brg_rate);
+ LOGSETUP("- BRG rate %d\n", m_brg_rate);
set_rcv_rate(m_brg_rate);
}
@@ -456,7 +532,7 @@ void mpcc_device::update_serial()
// check if Rx is in reset
if (m_tcr & REG_TCR_TRES)
{
- LOG("- Tx in reset\n");
+ LOGSETUP("- Tx in reset\n");
set_tra_rate(0);
}
// Tx is running
@@ -465,15 +541,15 @@ void mpcc_device::update_serial()
// Check that Tx is enabled
if (m_tcr & REG_TCR_TEN)
{
- LOG("- Tx enabled\n");
+ LOGSETUP("- Tx enabled\n");
m_brg_rate = get_tx_rate();
- LOG("- BRG rate %d\n", m_brg_rate);
+ LOGSETUP("- BRG rate %d\n", m_brg_rate);
set_tra_rate(m_brg_rate);
}
else
{
- LOG("- Tx disabled\n");
+ LOGSETUP("- Tx disabled\n");
set_tra_rate(0);
}
}
@@ -532,6 +608,7 @@ void mpcc_device::tra_complete()
else
{
m_out_rts_cb(CLEAR_LINE); // TODO: respect the RTSLV bit
+ m_sicr &= ~REG_SICR_RTSLVL;
}
// Check if Tx interrupts are enabled
@@ -574,6 +651,7 @@ void mpcc_device::rcv_complete()
receive_register_extract();
data = get_received_char();
+ LOGRX("%s %02x [%c]\n", FUNCNAME, isascii(data) ? data : ' ', data);
// receive_data(data);
if (m_rx_data_fifo.full())
@@ -706,7 +784,7 @@ READ8_MEMBER( mpcc_device::read )
{
case 0x00: data = do_rsr(); break;
case 0x01: data = do_rcr(); break;
- case 0x02: data = m_rdr; logerror("MPCC: Reg RDR not implemented\n"); break;
+ case 0x02: data = do_rdr(); break;
case 0x04: data = m_rivnr; logerror("MPCC: Reg RIVNR not implemented\n"); break;
case 0x05: data = do_rier(); break;
case 0x08: data = m_tsr; break; logerror("MPCC: Reg TSR not implemented\n"); break;
@@ -714,7 +792,7 @@ READ8_MEMBER( mpcc_device::read )
//case 0x0a: data = m_tdr; break; // TDR is a write only register
case 0x0c: data = do_tivnr(); break;
case 0x0d: data = do_tier(); break;
- case 0x10: data = m_sisr; logerror("MPCC: Reg SISR not implemented\n"); break;
+ case 0x10: data = do_sisr(); break;
case 0x11: data = do_sicr(); break;
case 0x14: data = m_sivnr; logerror("MPCC: Reg SIVNR not implemented\n"); break;
case 0x15: data = do_sier(); break;
@@ -750,7 +828,7 @@ WRITE8_MEMBER( mpcc_device::write )
case 0x0a: m_tdr = data; LOGCHAR("*%c", data); do_tdr(data); break;
case 0x0c: do_tivnr(data); break;
case 0x0d: do_tier(data); break;
- case 0x10: m_sisr = data; logerror("MPCC: Reg SISR not implemented\n"); break;
+ case 0x10: do_sisr(data); break;
case 0x11: do_sicr(data); break;
case 0x14: m_sivnr = data; logerror("MPCC: Reg SIVNR not implemented\n"); break;
case 0x15: do_sier(data); break;
@@ -800,6 +878,26 @@ uint8_t mpcc_device::do_rcr()
return data;
}
+uint8_t mpcc_device::do_rdr()
+{
+ uint8_t data = 0;
+
+ if (!m_rx_data_fifo.empty())
+ {
+ // load data from the FIFO
+ data = m_rx_data_fifo.dequeue();
+ }
+ else
+ {
+ LOGRX("data_read: Attempt to read out character from empty FIFO\n");
+ logerror("data_read: Attempt to read out character from empty FIFO\n");
+ }
+
+ LOGRX("%s <- %02x [%c]\n", FUNCNAME, isascii(data) ? data : ' ', data);
+ return data;
+}
+
+
void mpcc_device::do_rier(uint8_t data)
{
LOG("%s -> %02x\n", FUNCNAME, data);
@@ -908,10 +1006,47 @@ uint8_t mpcc_device::do_tier()
return data;
}
+void mpcc_device::do_sisr(uint8_t data)
+{
+ LOG("%s -> %02x\n", FUNCNAME, data);
+ if (data & REG_SISR_CTST) m_sisr &= ~REG_SISR_CTST;
+ if (data & REG_SISR_DSRT) m_sisr &= ~REG_SISR_DSRT;
+ if (data & REG_SISR_DCDT) m_sisr &= ~REG_SISR_DCDT;
+
+ LOGSETUP(" - CTS %d transitioned: %d\n", (m_sisr & REG_SISR_CTSLVL) ? 1 :0, (m_sisr & REG_SISR_CTST) ? 1 : 0);
+ LOGSETUP(" - DSR %d transitioned: %d\n", (m_sisr & REG_SISR_DSRLVL) ? 1 :0, (m_sisr & REG_SISR_DSRT) ? 1 : 0);
+ LOGSETUP(" - DCD %d transitioned: %d\n", (m_sisr & REG_SISR_DCDLVL) ? 1 :0, (m_sisr & REG_SISR_DCDT) ? 1 : 0);
+}
+
+uint8_t mpcc_device::do_sisr()
+{
+ uint8_t data = m_sisr;
+ LOG("%s <- %02x\n", FUNCNAME, data);
+ return data;
+}
+
void mpcc_device::do_sicr(uint8_t data)
{
LOG("%s -> %02x\n", FUNCNAME, data);
+
+ // If RTS is activated the RTS output latch can only be reset by an empty FIFO.
+ if ( !(m_sicr & REG_SICR_RTSLVL) &&
+ (data & REG_SICR_RTSLVL))
+ {
+ m_out_rts_cb(ASSERT_LINE); // TODO: respect the RTSLV bit
+ }
+
m_sicr = data;
+
+ if (m_sicr & REG_SICR_DTRLVL)
+ {
+ m_out_dtr_cb(ASSERT_LINE);
+ }
+ else
+ {
+ m_out_dtr_cb(CLEAR_LINE);
+ }
+
LOGSETUP(" - RTS level : %s\n", (m_sicr & REG_SICR_RTSLVL) ? "high" : "low");
LOGSETUP(" - DTR level : %s\n", (m_sicr & REG_SICR_DTRLVL) ? "high" : "low");
LOGSETUP(" - Echo Mode : %s\n", (m_sicr & REG_SICR_ECHO) ? "enabled" : "disabled");
diff --git a/src/devices/machine/68561mpcc.h b/src/devices/machine/68561mpcc.h
index 6263be045fb..a2c06dbaaf5 100644
--- a/src/devices/machine/68561mpcc.h
+++ b/src/devices/machine/68561mpcc.h
@@ -120,9 +120,10 @@ public:
DECLARE_READ8_MEMBER( iack );
/* Callbacks to be called by others for signals driven by connected devices */
- DECLARE_WRITE_LINE_MEMBER( write_rx ); // bit transitions from serial device
- DECLARE_WRITE_LINE_MEMBER( cts_w ) {} // { m_chanA->cts_w(state); }
- DECLARE_WRITE_LINE_MEMBER( dcd_w ) {} // { m_chanA->dcd_w(state); }
+ DECLARE_WRITE_LINE_MEMBER( write_rx );
+ DECLARE_WRITE_LINE_MEMBER( cts_w );
+ DECLARE_WRITE_LINE_MEMBER( dsr_w );
+ DECLARE_WRITE_LINE_MEMBER( dcd_w );
DECLARE_WRITE_LINE_MEMBER( rxc_w ) {} // { m_chanA->rxc_w(state); }
DECLARE_WRITE_LINE_MEMBER( txc_w ) {} // { m_chanA->txc_w(state); }
@@ -249,6 +250,7 @@ protected:
};
uint8_t m_rdr;
+ uint8_t do_rdr();
// TODO: investigate if 4 x 16 bit wide FIFO is needed for 16 bit mode
util::fifo<uint8_t, 8> m_rx_data_fifo;
@@ -318,7 +320,19 @@ protected:
REG_TIER_TFERR = 0x02, // TX Frame error interrupt
};
+ // SISR - Serial Interface Status Register
uint8_t m_sisr;
+ uint8_t do_sisr();
+ void do_sisr(uint8_t data);
+ enum
+ {
+ REG_SISR_CTST = 0x80, // Clear To Send Transition Status
+ REG_SISR_DSRT = 0x40, // Data Set Ready Transition Status
+ REG_SISR_DCDT = 0x20, // Data Carrier Detect Transition Status
+ REG_SISR_CTSLVL = 0x10, // Clear To Send Level
+ REG_SISR_DSRLVL = 0x08, // Data Set Ready Level
+ REG_SISR_DCDLVL = 0x04, // Data Carrier Detect Level
+ };
// SICR - Serial Interface Control Register
uint8_t m_sicr;
diff --git a/src/mame/drivers/fccpu20.cpp b/src/mame/drivers/fccpu20.cpp
index 2aedc8c181b..c8017ba0e82 100644
--- a/src/mame/drivers/fccpu20.cpp
+++ b/src/mame/drivers/fccpu20.cpp
@@ -11,57 +11,112 @@
*
*
* ||
- * || || CPU-20
+ * || || CPU-21 - main board
* ||||--||_____________________________________________________________
* ||||--|| |
* || || _ |__
* || | | |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || | |VME|
- * || | | |
- * || | |P1 |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || |_| |
- * || |___|
- * || |
- * || |
- * || |
- * || |
- * || |
- * || |
+ * RST o-[| | | |
+ * || +-------+ | | |
+ * ABT o-[| | XTAL | | | |
+ * || | 50MHz | +-----------------------+ | | |
+ * RUN C| +-------+ | MPCC | | | |
+ * HALT C| +-------+ | R68561P | | |VME|
+ * BM C| | XTAL | +-----------------------+ | | |
+ * || | 40MHz | +-----------------------+ | |P1 |
+ * || +-------+ | PIT | | | |
+ * FLMA C| +-------+ | MC68230P8 | | | |
+ * EPROM C| | XTAL | +-----------------------+ | | |
+ * 2WST C| | 32MHz | | | |
+ * 4WST C| +-------+ | | |
+ * 6WST C| | | |
+ * 8WST C| |_| |
+ * 12WST C| +--------------------+ |___|
+ * 14WST C| | BIM | |
+ * || | MC68153L | |
+ * || +--------------------+ |
+ * CSH o-[| |
* || |
+ * R/H o-[| |
* || |
+ * DIP0 - +----------------+ |
+ * . - | | |___
+ * . - | | +---+ _| |
+ * . - | CPU | | |+------------+ | | |
+ * . - | M68020 | | || 27128 | | | |
+ * . - | | | || EPROM | | | |
+ * . - | | | |+------------+ | | |
+ * DIP7 - | | | F | | |VME|
+ * || +----------------+ | L |+------------+ | | |
+ * || | M || 27128 | | |P2 |
+ * [|||O +------------+ | E || EPROM | | | |
+ * +-|||| | | | |+------------+ | | |
+ * | |||| | FPU | | m | | | |
+ * | |||| | 68881 | | e |+------------+ | | |
+ * | |||| | | | m || 27128 | | | |
+ * | |||| | | | || EPROM | | | |
+ * P4 | |||| +------------+ | b |+------------+ | | |
+ * | |||| | u | | | |
+ * +-|||| | s |+------------+ |_| |
+ * [|||O | || 27128 | |___|
+ * || || | || EPROM | |
+ * ||||--|| +---++------------+ |
+ * ||||--||-------------------------------------------------------------+
+ * ||
+ *
+ *
+ * ||
+ * || || CPU-21 - slave board (SRAM-22 - connected via FLME mem bus)
+ * ||||--||_____________________________________________________________
+ * ||||--|| |
+ * || || 64 x 64Kbit SRAM = 512KB __|__
+ * || +-----------+ +-----------+ +-----------+ +-----------+| | |
+ * || |IMS1600 | | | | | | || | |
+ * || +-----------+ +-----------+ +-----------+ +-----------+| | |
+ * RUN C| | | | | | | | || | |
+ * || +-----------+ +-----------+ +-----------+ +-----------+| | |
+ * || | | | | | | | || | |
+ * || +-----------+ +-----------+ +-----------+ +-----------+| |VME|
+ * SEL0 C| | | | | | | | || | |
+ * SEL1 C| +-----------+ +-----------+ +-----------+ +-----------+| |P1 |
+ * || | | | | | | | || | |
+ * || +-----------+ +-----------+ +-----------+ +-----------+| | |
+ * || | | | | | | | || | |
+ * || +-----------+ +-----------+ +-----------+ +-----------+| | |
+ * || | | | | | | | || | |
+ * || +-----------+ +-----------+ +-----------+ +-----------+| | |
+ * || | | | | | | | ||_| |
+ * || +-----------+ +-----------+ +-----------+ +-----------+ |___|
+ * || | | | | | | | | |
+ * || +-----------+ +-----------+ +-----------+ +-----------+ |
+ * || | | | | | | | | |
+ * || +-----------+ +-----------+ +-----------+ +-----------+ |
+ * || | | | | |
+ * || +-----------+ +-----------+ +-----------+ +-----------+ |
+ * || | | | | | | | | |
+ * || +-----------+ +-----------+ +-----------+ +-----------+ |
* || |___
- * || _| |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || | |VME|
- * || | | |
- * || | |P2 |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || | | |
- * || |_| |
- * || |___|
- * || || +
- * ||||--|| |
- * ||||--||--------------------------------------------------------------+
+ * || +---++-----------+ +-----------+ _| |
+ * || | || | | || | |
+ * || | |+-----------+ +-----------+| | |
+ * || | || | | || | |
+ * || | |+-----------+ +-----------+| | |
+ * || | F || | | || |VME|
+ * || | L |+-----------+ +-----------+| | |
+ * || | M | | |P2 |
+ * [|||O | E | | | |
+ * +-|||| | | | | |
+ * | |||| | m | | | |
+ * | |||| | e | | | |
+ * | |||| | m | | | |
+ * | |||| | | | | |
+ * P8? | |||| | b | | | |
+ * | |||| | u | +-----------------------+ | | |
+ * +-|||| | s | | MPCC | |_| |
+ * [|||O | | | R68561P | |___|
+ * || || | | +-----------------------+ |
+ * ||||--|| +---+ (XTAL) |
+ * ||||--||------------------------------------------------------------+
* ||
*
* History of Force Computers
@@ -103,9 +158,11 @@ Basadressen av I / O-enheter:
* FBFF0000-FBFFFFFF VME A16 D8-D32
* FC000000-FCFEFFFF VME A24 D8-D16
* FCFF0000-FCFFFFFF VME A16 D8-D16
+ * FF800000 MPCC
+ * FF800200 MPCC1 - on daughter board
+ * FF800600 MPCC2 - on daughter board
* FF800800 BIM
* FF800C00 PIT
- * FF800000 MPCC
* FF800A00 RTC
* --------------------------------------------------------------------------
*
@@ -194,6 +251,8 @@ cpu20_state(const machine_config &mconfig, device_type type, const char *tag)
, m_pit (*this, "pit")
, m_bim (*this, "bim")
, m_mpcc (*this, "mpcc")
+ , m_mpcc2 (*this, "mpcc2")
+ , m_mpcc3 (*this, "mpcc3")
{
}
DECLARE_READ32_MEMBER (bootvect_r);
@@ -206,11 +265,18 @@ cpu20_state(const machine_config &mconfig, device_type type, const char *tag)
virtual void machine_start () override;
virtual void machine_reset () override;
+ /* PIT callbacks */
+ DECLARE_READ8_MEMBER (pita_r);
+ DECLARE_READ8_MEMBER (pitb_r);
+ DECLARE_READ8_MEMBER (pitc_r);
+
private:
required_device<m68000_base_device> m_maincpu;
required_device<pit68230_device> m_pit;
required_device<bim68153_device> m_bim;
required_device<mpcc68561_device> m_mpcc;
+ required_device<mpcc68561_device> m_mpcc2;
+ required_device<mpcc68561_device> m_mpcc3;
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
uint32_t *m_sysrom;
@@ -228,7 +294,9 @@ static ADDRESS_MAP_START (cpu20_mem, AS_PROGRAM, 32, cpu20_state)
AM_RANGE (0xff040000, 0xff04ffff) AM_RAM /* RAM installed in machine start */
AM_RANGE (0xff000000, 0xff00ffff) AM_ROM AM_REGION("roms", 0x0000)
AM_RANGE (0xff800000, 0xff80001f) AM_DEVREADWRITE8("mpcc", mpcc68561_device, read, write, 0xffffffff)
-// AM_RANGE (0xff800200, 0xff80020f) AM_DEVREADWRITE8("pit2", pit68230_device, read, write, 0xff00ff00)
+ AM_RANGE (0xff800200, 0xff80021f) AM_DEVREADWRITE8("mpcc2", mpcc68561_device, read, write, 0xffffffff)
+// AM_RANGE (0xff800200, 0xff8003ff) AM_DEVREADWRITE8("pit2", pit68230_device, read, write, 0xff00ff00)
+ AM_RANGE (0xff800600, 0xff80061f) AM_DEVREADWRITE8("mpcc3", mpcc68561_device, read, write, 0xffffffff)
AM_RANGE (0xff800800, 0xff80080f) AM_DEVREADWRITE8("bim", bim68153_device, read, write, 0xff00ff00)
// AM_RANGE (0xff800a00, 0xff800a0f) AM_DEVREADWRITE8("rtc", rtc_device, read, write, 0x00ff00ff)
AM_RANGE (0xff800c00, 0xff800dff) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0xffffffff)
@@ -315,6 +383,48 @@ void cpu20_state::update_irq_to_maincpu()
}
}
+/* 8 configuration DIP switches
+
+ Baud B3 B2 B1 B0
+ 9600 0 0 0 1
+ 28800 0 0 1 0
+ 38400 1 0 1 0
+ 57600 0 0 1 1
+
+ B3: 8 bit 38400 baud
+
+ B4:
+
+ B5:
+
+ B6: Auto execute FF00C0000
+
+ B7: memory size?
+*/
+#define BR7N9600 0x01
+#define BR7N28800 0x02
+#define BR7N38400 0x06
+#define BR7N57600 0x03
+#define BR8N38400 0x08
+#define FORCEBUG 0x30
+READ8_MEMBER (cpu20_state::pita_r){
+ LOG("%s\n", FUNCNAME);
+
+ return FORCEBUG | BR7N9600;
+}
+
+/* Enabling/Disabling of VME IRQ 1-7 */
+READ8_MEMBER (cpu20_state::pitb_r){
+ LOG("%s\n", FUNCNAME);
+ return 0xff;
+}
+
+/* VME bus release software settings (output) (ROR, RAT, RATAR, RATBCLR, RORAT, RORRAT */
+READ8_MEMBER (cpu20_state::pitc_r){
+ LOG("%s\n", FUNCNAME);
+ return 0xff;
+}
+
static SLOT_INTERFACE_START(fccpu20_vme_cards)
SLOT_INTERFACE("fcisio", VME_FCISIO1)
SLOT_INTERFACE("fcscsi", VME_FCSCSI1)
@@ -330,15 +440,17 @@ static MACHINE_CONFIG_START (cpu20, cpu20_state)
MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("bim", bim68153_device, iack)
MCFG_VME_DEVICE_ADD("vme")
- MCFG_VME_SLOT_ADD ("vme", "slot1", fccpu20_vme_cards, nullptr)
+ MCFG_VME_SLOT_ADD ("vme", "vme1", fccpu20_vme_cards, nullptr)
/* PIT Parallel Interface and Timer device, assumed strapped for on board clock */
- MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_8_664MHz)
+ MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_32MHz / 4) /* Crystal not verified */
+ MCFG_PIT68230_PA_INPUT_CB(READ8(cpu20_state, pita_r))
+ MCFG_PIT68230_PB_INPUT_CB(READ8(cpu20_state, pitb_r))
+ MCFG_PIT68230_PC_INPUT_CB(READ8(cpu20_state, pitc_r))
MCFG_PIT68230_TIMER_IRQ_CB(DEVWRITELINE("bim", bim68153_device, int2_w))
-// MCFG_DEVICE_ADD ("pit2", PIT68230, XTAL_8_664MHz)
-
- MCFG_MC68153_ADD("bim", XTAL_16MHz / 2)
+ /* BIM */
+ MCFG_MC68153_ADD("bim", XTAL_32MHz / 8)
MCFG_BIM68153_OUT_INT_CB(WRITELINE(cpu20_state, bim_irq_callback))
/*INT0 - Abort switch */
/*INT1 - MPCC@8.064 MHz aswell */
@@ -347,16 +459,43 @@ static MACHINE_CONFIG_START (cpu20, cpu20_state)
/* MPCC */
#define RS232P1_TAG "rs232p1"
- MCFG_MPCC68561_ADD ("mpcc", XTAL_16MHz, 0, 0)
+#define RS232P2_TAG "rs232p2"
+#define RS232P3_TAG "rs232p3"
+ // MPCC
+ MCFG_MPCC68561_ADD ("mpcc", XTAL_32MHz / 4, 0, 0)
MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_txd))
MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_dtr))
MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_rts))
- // RS232
+ MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int1_w))
+ /* Additional MPCC sits on slave boards like SRAM-22 */
+ // MPCC2
+ MCFG_MPCC68561_ADD ("mpcc2", XTAL_32MHz / 4, 0, 0)
+ MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_txd))
+ MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_dtr))
+ MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_rts))
+ MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int3_w))
+ // MPCC3
+ MCFG_MPCC68561_ADD ("mpcc3", XTAL_32MHz / 4, 0, 0)
+ MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_txd))
+ MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_dtr))
+ MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_rts))
+ MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int3_w))
+
+ // MPCC - RS232
MCFG_RS232_PORT_ADD (RS232P1_TAG, default_rs232_devices, "terminal")
- MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("mpcc", mpcc68561_device, rx_w))
+ MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("mpcc", mpcc68561_device, write_rx))
MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("mpcc", mpcc68561_device, cts_w))
-// MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int1_w))
+ // MPCC2 - RS232
+ MCFG_RS232_PORT_ADD (RS232P2_TAG, default_rs232_devices, nullptr)
+ MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("mpcc2", mpcc68561_device, write_rx))
+ MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("mpcc2", mpcc68561_device, cts_w))
+
+ // MPCC3 - RS232
+ MCFG_RS232_PORT_ADD (RS232P3_TAG, default_rs232_devices, nullptr)
+ MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("mpcc3", mpcc68561_device, write_rx))
+ MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("mpcc3", mpcc68561_device, cts_w))
+
MACHINE_CONFIG_END
/* ROM definitions */