diff options
author | 2019-04-26 12:57:56 +0200 | |
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committer | 2019-04-26 13:05:23 +0200 | |
commit | ca07dc3cc53b809954db77d8248c5642d0c0d12d (patch) | |
tree | 87662884f777feb6825fb3214c8eeaf85a03195b | |
parent | 8320a30ff332401bde7a268e4e147d9068537086 (diff) |
xbox_pci.cpp: start supporting smm and let nforcepc use it (nw)
-rw-r--r-- | src/mame/drivers/nforcepc.cpp | 2 | ||||
-rw-r--r-- | src/mame/includes/xbox_pci.h | 5 | ||||
-rw-r--r-- | src/mame/machine/xbox_pci.cpp | 29 |
3 files changed, 34 insertions, 2 deletions
diff --git a/src/mame/drivers/nforcepc.cpp b/src/mame/drivers/nforcepc.cpp index c3d62b9145a..0d0482939d5 100644 --- a/src/mame/drivers/nforcepc.cpp +++ b/src/mame/drivers/nforcepc.cpp @@ -698,6 +698,7 @@ void nforcepc_state::nforcepc(machine_config &config) maincpu.set_addrmap(AS_PROGRAM, &nforcepc_state::nforce_map); maincpu.set_addrmap(AS_IO, &nforcepc_state::nforce_map_io); maincpu.set_irq_acknowledge_callback(FUNC(nforcepc_state::irq_callback)); + //maincpu.smiact().set("pci:01.0", FUNC(i82439hx_host_device::smi_act_w)); PCI_ROOT(config, ":pci", 0); CRUSH11(config, ":pci:00.0", 0, "maincpu"); // 10de:01a4 NVIDIA Corporation nForce CPU bridge @@ -705,6 +706,7 @@ void nforcepc_state::nforcepc(machine_config &config) 10de:01ad NVIDIA Corporation nForce 220/420 Memory Controller 10de:01ab NVIDIA Corporation nForce 420 Memory Controller (DDR)*/ mcpx_isalpc_device &isa(MCPX_ISALPC(config, ":pci:01.0", 0, 0x10430c11)); // 10de:01b2 NVIDIA Corporation nForce ISA Bridge (LPC bus) + isa.smi().set_inputline(":maincpu", INPUT_LINE_SMI); isa.boot_state_hook().set(FUNC(nforcepc_state::boot_state_award_w)); isa.interrupt_output().set(FUNC(nforcepc_state::maincpu_interrupt)); it8703f_device &ite(IT8703F(config, ":pci:01.0:0", 0)); diff --git a/src/mame/includes/xbox_pci.h b/src/mame/includes/xbox_pci.h index 16606d1fcb5..bea51152fad 100644 --- a/src/mame/includes/xbox_pci.h +++ b/src/mame/includes/xbox_pci.h @@ -74,6 +74,7 @@ public: mcpx_isalpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t subsystem_id); mcpx_isalpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + auto smi() { return m_smi_callback.bind(); } auto interrupt_output() { return m_interrupt_output.bind(); } auto boot_state_hook() { return m_boot_state_hook.bind(); } @@ -107,13 +108,17 @@ protected: private: void internal_io_map(address_map &map); void lpc_io(address_map &map); + void update_smi_line(); + devcb_write_line m_smi_callback; devcb_write_line m_interrupt_output; devcb_write8 m_boot_state_hook; required_device<pic8259_device> pic8259_1; required_device<pic8259_device> pic8259_2; required_device<pit8254_device> pit8254; + uint16_t m_global_smi_control; + uint8_t m_smi_command_port; lpcbus_device_interface *lpcdevices[16]; }; diff --git a/src/mame/machine/xbox_pci.cpp b/src/mame/machine/xbox_pci.cpp index c45b3fe53ff..88a4ea9a546 100644 --- a/src/mame/machine/xbox_pci.cpp +++ b/src/mame/machine/xbox_pci.cpp @@ -115,17 +115,21 @@ mcpx_isalpc_device::mcpx_isalpc_device(const machine_config &mconfig, const char mcpx_isalpc_device::mcpx_isalpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : pci_device(mconfig, MCPX_ISALPC, tag, owner, clock), + m_smi_callback(*this), m_interrupt_output(*this), m_boot_state_hook(*this), pic8259_1(*this, "pic8259_1"), pic8259_2(*this, "pic8259_2"), - pit8254(*this, "pit8254") + pit8254(*this, "pit8254"), + m_global_smi_control(0), + m_smi_command_port(0) { } void mcpx_isalpc_device::device_start() { pci_device::device_start(); + m_smi_callback.resolve_safe(); m_interrupt_output.resolve_safe(); m_boot_state_hook.resolve_safe(); add_map(0x00000100, M_IO, FUNC(mcpx_isalpc_device::lpc_io)); @@ -189,9 +193,21 @@ void mcpx_isalpc_device::device_add_mconfig(machine_config &config) */ } +void mcpx_isalpc_device::update_smi_line() +{ + if (m_global_smi_control) + m_smi_callback(1); + else + m_smi_callback(0); +} + READ32_MEMBER(mcpx_isalpc_device::acpi_r) { logerror("Acpi read from %04X mask %08X\n", bank_infos[0].adr + offset * 4, mem_mask); + if ((offset == 0xa) && ACCESSING_BITS_0_15) + return m_global_smi_control; + if ((offset == 0xb) && ACCESSING_BITS_16_23) + return m_smi_command_port << 16; return 0; } @@ -199,11 +215,20 @@ WRITE32_MEMBER(mcpx_isalpc_device::acpi_w) { // Seen using word registers at the following offsets // 0x00 0x02 0x04 0x08 0x20 0x22 0x28 0xa0 0xa2 0xc0-0xd8 + if ((offset == 0xa) && ACCESSING_BITS_0_15) + { + // Global SMI Control + m_global_smi_control = m_global_smi_control & (~data & 0xffff); + update_smi_line(); + } if ((offset == 0xb) && ACCESSING_BITS_16_23) { // SMI Command Port // write to byte 0x2e must generate a SMI interrupt - logerror("Generate software SMI with value %02X\n", (data >> 16) & 0xff); + m_smi_command_port = (data >> 16) & 0xff; + m_global_smi_control |= 0x200; + update_smi_line(); + logerror("Generate software SMI with value %02X\n", m_smi_command_port); } logerror("Acpi write %08X to %04X mask %08X\n", data, bank_infos[0].adr + offset * 4, mem_mask); } |