diff options
author | 2014-10-18 20:44:47 +0000 | |
---|---|---|
committer | 2014-10-18 20:44:47 +0000 | |
commit | 932b305d754b9c39036a38f418530d7276d936c7 (patch) | |
tree | 82cd83a44ddfd6859464d0ebcc71cfca03cd7f9a | |
parent | 0a61c69a7712a1d59000d91b2d6e17e0d338fd65 (diff) |
calchase.c: [Peter Ferrie]
* Implemented missing DIP switch for Eggs Playing Chicken, promote to working. Press "S" to skip the CMOS error, "S" or wait to skip the emm386.exe error (not an emulation issue), use "Coin 2" to
coin-up and start the game, and "1 Player Start" to brake.
calchase.c, gamecstl.c, midqslvr.c, queen.c, savquest.c, taitowlf.c,
voyager.c, xtom3d.c: [Peter Ferrie]
* Intel component is not MXTC, it's MTXC.
-rw-r--r-- | src/mame/drivers/calchase.c | 54 | ||||
-rw-r--r-- | src/mame/drivers/gamecstl.c | 46 | ||||
-rw-r--r-- | src/mame/drivers/midqslvr.c | 58 | ||||
-rw-r--r-- | src/mame/drivers/queen.c | 48 | ||||
-rw-r--r-- | src/mame/drivers/savquest.c | 68 | ||||
-rw-r--r-- | src/mame/drivers/taitowlf.c | 46 | ||||
-rw-r--r-- | src/mame/drivers/voyager.c | 50 | ||||
-rw-r--r-- | src/mame/drivers/xtom3d.c | 58 |
8 files changed, 213 insertions, 215 deletions
diff --git a/src/mame/drivers/calchase.c b/src/mame/drivers/calchase.c index 3491026395e..dc7915afd07 100644 --- a/src/mame/drivers/calchase.c +++ b/src/mame/drivers/calchase.c @@ -142,7 +142,7 @@ public: UINT32 *m_bios_ram; UINT32 *m_bios_ext_ram; - UINT8 m_mxtc_config_reg[256]; + UINT8 m_mtxc_config_reg[256]; UINT8 m_piix4_config_reg[4][256]; UINT32 m_idle_skip_ram; @@ -166,21 +166,21 @@ public: required_device<dac_device> m_dac_r; }; -// Intel 82439TX System Controller (MXTC) +// Intel 82439TX System Controller (MTXC) // TODO: change with a VIA82C585VPX (North Bridge - APOLLO Chipset) -static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg) +static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg) { calchase_state *state = busdevice->machine().driver_data<calchase_state>(); -// osd_printf_debug("MXTC: read %d, %02X\n", function, reg); +// osd_printf_debug("MTXC: read %d, %02X\n", function, reg); - return state->m_mxtc_config_reg[reg]; + return state->m_mtxc_config_reg[reg]; } -static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) +static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) { calchase_state *state = busdevice->machine().driver_data<calchase_state>(); -// osd_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data); +// osd_printf_debug("%s:MTXC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data); /* memory banking with North Bridge: @@ -204,17 +204,17 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i state->membank("bios_ext")->set_base(state->memregion("bios")->base() + 0); } - state->m_mxtc_config_reg[reg] = data; + state->m_mtxc_config_reg[reg] = data; } void calchase_state::intel82439tx_init() { - m_mxtc_config_reg[0x60] = 0x02; - m_mxtc_config_reg[0x61] = 0x02; - m_mxtc_config_reg[0x62] = 0x02; - m_mxtc_config_reg[0x63] = 0x02; - m_mxtc_config_reg[0x64] = 0x02; - m_mxtc_config_reg[0x65] = 0x02; + m_mtxc_config_reg[0x60] = 0x02; + m_mtxc_config_reg[0x61] = 0x02; + m_mtxc_config_reg[0x62] = 0x02; + m_mtxc_config_reg[0x63] = 0x02; + m_mtxc_config_reg[0x64] = 0x02; + m_mtxc_config_reg[0x65] = 0x02; } static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask) @@ -226,19 +226,19 @@ static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int func if (ACCESSING_BITS_24_31) { - r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24; + r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24; } if (ACCESSING_BITS_16_23) { - r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16; + r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16; } if (ACCESSING_BITS_8_15) { - r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8; + r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8; } if (ACCESSING_BITS_0_7) { - r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0; + r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0; } return r; } @@ -247,19 +247,19 @@ static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int functi { if (ACCESSING_BITS_24_31) { - mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); } if (ACCESSING_BITS_16_23) { - mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); } if (ACCESSING_BITS_8_15) { - mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); } if (ACCESSING_BITS_0_7) { - mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); } } @@ -328,7 +328,7 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi WRITE32_MEMBER(calchase_state::bios_ram_w) { - if (m_mxtc_config_reg[0x63] & 0x10) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x63] & 0x10) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ram + offset); } @@ -336,7 +336,7 @@ WRITE32_MEMBER(calchase_state::bios_ram_w) WRITE32_MEMBER(calchase_state::bios_ext_ram_w) { - if (m_mxtc_config_reg[0x63] & 0x40) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x63] & 0x40) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ext_ram + offset); } @@ -571,9 +571,7 @@ static INPUT_PORTS_START( calchase ) PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) ) PORT_DIPSETTING( 0x1000, DEF_STR( Off ) ) PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) - PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x2000, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen") //eggsplc PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) ) PORT_DIPSETTING( 0x4000, DEF_STR( Off ) ) PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) @@ -774,4 +772,4 @@ ROM_END GAME( 1998, hostinv, 0, hostinv, calchase, calchase_state, hostinv, ROT0, "The Game Room", "Host Invaders", GAME_NOT_WORKING|GAME_IMPERFECT_GRAPHICS ) GAME( 1999, calchase, 0, calchase, calchase, calchase_state, calchase, ROT0, "The Game Room", "California Chase", GAME_NOT_WORKING|GAME_IMPERFECT_GRAPHICS ) -GAME( 2002, eggsplc, 0, calchase, calchase, calchase_state, hostinv, ROT0, "The Game Room", "Eggs Playing Chicken", GAME_NOT_WORKING|GAME_IMPERFECT_GRAPHICS ) +GAME( 2002, eggsplc, 0, calchase, calchase, calchase_state, hostinv, ROT0, "The Game Room", "Eggs Playing Chicken", 0 ) diff --git a/src/mame/drivers/gamecstl.c b/src/mame/drivers/gamecstl.c index d288f7a7acf..362fcd82f89 100644 --- a/src/mame/drivers/gamecstl.c +++ b/src/mame/drivers/gamecstl.c @@ -83,7 +83,7 @@ public: required_device<gfxdecode_device> m_gfxdecode; required_device<palette_device> m_palette; UINT32 *m_bios_ram; - UINT8 m_mxtc_config_reg[256]; + UINT8 m_mtxc_config_reg[256]; UINT8 m_piix4_config_reg[4][256]; DECLARE_WRITE32_MEMBER(pnp_config_w); @@ -162,19 +162,19 @@ UINT32 gamecstl_state::screen_update_gamecstl(screen_device &screen, bitmap_ind1 return 0; } -// Intel 82439TX System Controller (MXTC) +// Intel 82439TX System Controller (MTXC) -static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg) +static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg) { gamecstl_state *state = busdevice->machine().driver_data<gamecstl_state>(); - printf("MXTC: read %d, %02X\n", function, reg); - return state->m_mxtc_config_reg[reg]; + printf("MTXC: read %d, %02X\n", function, reg); + return state->m_mtxc_config_reg[reg]; } -static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) +static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) { gamecstl_state *state = busdevice->machine().driver_data<gamecstl_state>(); - printf("%s:MXTC: write %d, %02X, %02X\n", busdevice->machine().describe_context(), function, reg, data); + printf("%s:MTXC: write %d, %02X, %02X\n", busdevice->machine().describe_context(), function, reg, data); switch(reg) { @@ -192,17 +192,17 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i } } - state->m_mxtc_config_reg[reg] = data; + state->m_mtxc_config_reg[reg] = data; } void gamecstl_state::intel82439tx_init() { - m_mxtc_config_reg[0x60] = 0x02; - m_mxtc_config_reg[0x61] = 0x02; - m_mxtc_config_reg[0x62] = 0x02; - m_mxtc_config_reg[0x63] = 0x02; - m_mxtc_config_reg[0x64] = 0x02; - m_mxtc_config_reg[0x65] = 0x02; + m_mtxc_config_reg[0x60] = 0x02; + m_mtxc_config_reg[0x61] = 0x02; + m_mtxc_config_reg[0x62] = 0x02; + m_mtxc_config_reg[0x63] = 0x02; + m_mtxc_config_reg[0x64] = 0x02; + m_mtxc_config_reg[0x65] = 0x02; } static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask) @@ -210,19 +210,19 @@ static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int func UINT32 r = 0; if (ACCESSING_BITS_24_31) { - r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24; + r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24; } if (ACCESSING_BITS_16_23) { - r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16; + r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16; } if (ACCESSING_BITS_8_15) { - r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8; + r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8; } if (ACCESSING_BITS_0_7) { - r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0; + r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0; } return r; } @@ -231,19 +231,19 @@ static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int functi { if (ACCESSING_BITS_24_31) { - mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); } if (ACCESSING_BITS_16_23) { - mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); } if (ACCESSING_BITS_8_15) { - mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); } if (ACCESSING_BITS_0_7) { - mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); } } @@ -326,7 +326,7 @@ WRITE32_MEMBER(gamecstl_state::pnp_data_w) WRITE32_MEMBER(gamecstl_state::bios_ram_w) { - if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ram + offset); } diff --git a/src/mame/drivers/midqslvr.c b/src/mame/drivers/midqslvr.c index a56a0c192fc..af631ee7206 100644 --- a/src/mame/drivers/midqslvr.c +++ b/src/mame/drivers/midqslvr.c @@ -45,7 +45,7 @@ public: UINT32 *m_bios_ext4_ram; UINT32 *m_isa_ram1; UINT32 *m_isa_ram2; - UINT8 m_mxtc_config_reg[256]; + UINT8 m_mtxc_config_reg[256]; UINT8 m_piix4_config_reg[4][256]; DECLARE_WRITE32_MEMBER( isa_ram1_w ); @@ -63,23 +63,23 @@ public: }; -// Intel 82439TX System Controller (MXTC) +// Intel 82439TX System Controller (MTXC) -static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg) +static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg) { midqslvr_state *state = busdevice->machine().driver_data<midqslvr_state>(); -// osd_printf_debug("MXTC: read %d, %02X\n", function, reg); +// osd_printf_debug("MTXC: read %d, %02X\n", function, reg); if((reg & 0xfc) == 0 && function == 0) // return vendor ID return (0x71008086 >> (reg & 3)*8) & 0xff; - return state->m_mxtc_config_reg[reg]; + return state->m_mtxc_config_reg[reg]; } -static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) +static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) { midqslvr_state *state = busdevice->machine().driver_data<midqslvr_state>(); - printf("MXTC: write %d, %02X, %02X\n", function, reg, data); + printf("MTXC: write %d, %02X, %02X\n", function, reg, data); /* memory banking with North Bridge: @@ -155,17 +155,17 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i } } - state->m_mxtc_config_reg[reg] = data; + state->m_mtxc_config_reg[reg] = data; } void midqslvr_state::intel82439tx_init() { - m_mxtc_config_reg[0x60] = 0x02; - m_mxtc_config_reg[0x61] = 0x02; - m_mxtc_config_reg[0x62] = 0x02; - m_mxtc_config_reg[0x63] = 0x02; - m_mxtc_config_reg[0x64] = 0x02; - m_mxtc_config_reg[0x65] = 0x02; + m_mtxc_config_reg[0x60] = 0x02; + m_mtxc_config_reg[0x61] = 0x02; + m_mtxc_config_reg[0x62] = 0x02; + m_mtxc_config_reg[0x63] = 0x02; + m_mtxc_config_reg[0x64] = 0x02; + m_mtxc_config_reg[0x65] = 0x02; } static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask) @@ -173,19 +173,19 @@ static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int func UINT32 r = 0; if (ACCESSING_BITS_24_31) { - r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24; + r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24; } if (ACCESSING_BITS_16_23) { - r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16; + r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16; } if (ACCESSING_BITS_8_15) { - r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8; + r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8; } if (ACCESSING_BITS_0_7) { - r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0; + r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0; } return r; } @@ -194,19 +194,19 @@ static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int functi { if (ACCESSING_BITS_24_31) { - mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); } if (ACCESSING_BITS_16_23) { - mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); } if (ACCESSING_BITS_8_15) { - mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); } if (ACCESSING_BITS_0_7) { - mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); } } @@ -296,7 +296,7 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi WRITE32_MEMBER(midqslvr_state::isa_ram1_w) { - if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled { COMBINE_DATA(m_isa_ram1 + offset); } @@ -304,7 +304,7 @@ WRITE32_MEMBER(midqslvr_state::isa_ram1_w) WRITE32_MEMBER(midqslvr_state::isa_ram2_w) { - if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled { COMBINE_DATA(m_isa_ram2 + offset); } @@ -312,7 +312,7 @@ WRITE32_MEMBER(midqslvr_state::isa_ram2_w) WRITE32_MEMBER(midqslvr_state::bios_ext1_ram_w) { - if (m_mxtc_config_reg[0x5e] & 0x2) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5e] & 0x2) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ext1_ram + offset); } @@ -321,7 +321,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext1_ram_w) WRITE32_MEMBER(midqslvr_state::bios_ext2_ram_w) { - if (m_mxtc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ext2_ram + offset); } @@ -330,7 +330,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext2_ram_w) WRITE32_MEMBER(midqslvr_state::bios_ext3_ram_w) { - if (m_mxtc_config_reg[0x5f] & 0x2) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5f] & 0x2) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ext3_ram + offset); } @@ -339,7 +339,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext3_ram_w) WRITE32_MEMBER(midqslvr_state::bios_ext4_ram_w) { - if (m_mxtc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ext4_ram + offset); } @@ -348,7 +348,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext4_ram_w) WRITE32_MEMBER(midqslvr_state::bios_ram_w) { - if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ram + offset); } diff --git a/src/mame/drivers/queen.c b/src/mame/drivers/queen.c index 4767c7b2760..7d82b8e8a64 100644 --- a/src/mame/drivers/queen.c +++ b/src/mame/drivers/queen.c @@ -43,7 +43,7 @@ public: UINT32 *m_bios_ram; UINT32 *m_bios_ext_ram; - UINT8 m_mxtc_config_reg[256]; + UINT8 m_mtxc_config_reg[256]; UINT8 m_piix4_config_reg[4][256]; DECLARE_WRITE32_MEMBER( bios_ext_ram_w ); @@ -55,20 +55,20 @@ public: }; -// Intel 82439TX System Controller (MXTC) +// Intel 82439TX System Controller (MTXC) -static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg) +static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg) { queen_state *state = busdevice->machine().driver_data<queen_state>(); -// osd_printf_debug("MXTC: read %d, %02X\n", function, reg); +// osd_printf_debug("MTXC: read %d, %02X\n", function, reg); - return state->m_mxtc_config_reg[reg]; + return state->m_mtxc_config_reg[reg]; } -static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) +static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) { queen_state *state = busdevice->machine().driver_data<queen_state>(); - printf("MXTC: write %d, %02X, %02X\n", function, reg, data); + printf("MTXC: write %d, %02X, %02X\n", function, reg, data); /* memory banking with North Bridge: @@ -92,17 +92,17 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i state->membank("bios_ext")->set_base(state->memregion("bios")->base() + 0x20000); } - state->m_mxtc_config_reg[reg] = data; + state->m_mtxc_config_reg[reg] = data; } void queen_state::intel82439tx_init() { - m_mxtc_config_reg[0x60] = 0x02; - m_mxtc_config_reg[0x61] = 0x02; - m_mxtc_config_reg[0x62] = 0x02; - m_mxtc_config_reg[0x63] = 0x02; - m_mxtc_config_reg[0x64] = 0x02; - m_mxtc_config_reg[0x65] = 0x02; + m_mtxc_config_reg[0x60] = 0x02; + m_mtxc_config_reg[0x61] = 0x02; + m_mtxc_config_reg[0x62] = 0x02; + m_mtxc_config_reg[0x63] = 0x02; + m_mtxc_config_reg[0x64] = 0x02; + m_mtxc_config_reg[0x65] = 0x02; } static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask) @@ -110,19 +110,19 @@ static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int func UINT32 r = 0; if (ACCESSING_BITS_24_31) { - r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24; + r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24; } if (ACCESSING_BITS_16_23) { - r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16; + r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16; } if (ACCESSING_BITS_8_15) { - r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8; + r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8; } if (ACCESSING_BITS_0_7) { - r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0; + r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0; } return r; } @@ -131,19 +131,19 @@ static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int functi { if (ACCESSING_BITS_24_31) { - mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); } if (ACCESSING_BITS_16_23) { - mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); } if (ACCESSING_BITS_8_15) { - mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); } if (ACCESSING_BITS_0_7) { - mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); } } @@ -209,7 +209,7 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi WRITE32_MEMBER(queen_state::bios_ext_ram_w) { - if (m_mxtc_config_reg[0x63] & 0x40) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x63] & 0x40) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ext_ram + offset); } @@ -218,7 +218,7 @@ WRITE32_MEMBER(queen_state::bios_ext_ram_w) WRITE32_MEMBER(queen_state::bios_ram_w) { - if (m_mxtc_config_reg[0x63] & 0x10) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x63] & 0x10) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ram + offset); } diff --git a/src/mame/drivers/savquest.c b/src/mame/drivers/savquest.c index ff32b04da71..18901d3b6bf 100644 --- a/src/mame/drivers/savquest.c +++ b/src/mame/drivers/savquest.c @@ -87,7 +87,7 @@ public: UINT8 m_port379; int m_hasp_passmode; - UINT8 m_mxtc_config_reg[256]; + UINT8 m_mtxc_config_reg[256]; UINT8 m_piix4_config_reg[8][256]; DECLARE_WRITE32_MEMBER( bios_f0000_ram_w ); @@ -115,23 +115,23 @@ public: void intel82439tx_init(); }; -// Intel 82439TX System Controller (MXTC) +// Intel 82439TX System Controller (MTXC) -static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg) +static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg) { savquest_state *state = busdevice->machine().driver_data<savquest_state>(); -// osd_printf_debug("MXTC: read %d, %02X\n", function, reg); +// osd_printf_debug("MTXC: read %d, %02X\n", function, reg); if((reg & 0xfe) == 0) return (reg & 1) ? 0x80 : 0x86; // Vendor ID, Intel if((reg & 0xfe) == 2) - return (reg & 1) ? 0x70 : 0x00; // Device ID, MXTC + return (reg & 1) ? 0x70 : 0x00; // Device ID, MTXC - return state->m_mxtc_config_reg[reg]; + return state->m_mtxc_config_reg[reg]; } -static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) +static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) { savquest_state *state = busdevice->machine().driver_data<savquest_state>(); // osd_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data); @@ -198,17 +198,17 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i } #endif - state->m_mxtc_config_reg[reg] = data; + state->m_mtxc_config_reg[reg] = data; } void savquest_state::intel82439tx_init() { - m_mxtc_config_reg[0x60] = 0x02; - m_mxtc_config_reg[0x61] = 0x02; - m_mxtc_config_reg[0x62] = 0x02; - m_mxtc_config_reg[0x63] = 0x02; - m_mxtc_config_reg[0x64] = 0x02; - m_mxtc_config_reg[0x65] = 0x02; + m_mtxc_config_reg[0x60] = 0x02; + m_mtxc_config_reg[0x61] = 0x02; + m_mtxc_config_reg[0x62] = 0x02; + m_mtxc_config_reg[0x63] = 0x02; + m_mtxc_config_reg[0x64] = 0x02; + m_mtxc_config_reg[0x65] = 0x02; m_smram = auto_alloc_array(machine(), UINT8, 0x20000); } @@ -217,19 +217,19 @@ static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int func UINT32 r = 0; if (ACCESSING_BITS_24_31) { - r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24; + r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24; } if (ACCESSING_BITS_16_23) { - r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16; + r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16; } if (ACCESSING_BITS_8_15) { - r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8; + r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8; } if (ACCESSING_BITS_0_7) { - r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0; + r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0; } return r; } @@ -238,19 +238,19 @@ static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int functi { if (ACCESSING_BITS_24_31) { - mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); } if (ACCESSING_BITS_16_23) { - mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); } if (ACCESSING_BITS_8_15) { - mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); } if (ACCESSING_BITS_0_7) { - mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); } } @@ -327,9 +327,9 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi WRITE32_MEMBER(savquest_state::bios_f0000_ram_w) { - //if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled + //if (m_mtxc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled #if 1 - if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_f0000_ram + offset); } @@ -338,9 +338,9 @@ WRITE32_MEMBER(savquest_state::bios_f0000_ram_w) WRITE32_MEMBER(savquest_state::bios_e0000_ram_w) { - //if (m_mxtc_config_reg[0x5e] & 2) // write to RAM if this region is write-enabled + //if (m_mtxc_config_reg[0x5e] & 2) // write to RAM if this region is write-enabled #if 1 - if (m_mxtc_config_reg[0x5e] & 2) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5e] & 2) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_e0000_ram + offset); } @@ -349,9 +349,9 @@ WRITE32_MEMBER(savquest_state::bios_e0000_ram_w) WRITE32_MEMBER(savquest_state::bios_e4000_ram_w) { - //if (m_mxtc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled + //if (m_mtxc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled #if 1 - if (m_mxtc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_e4000_ram + offset); } @@ -360,9 +360,9 @@ WRITE32_MEMBER(savquest_state::bios_e4000_ram_w) WRITE32_MEMBER(savquest_state::bios_e8000_ram_w) { - //if (m_mxtc_config_reg[0x5f] & 2) // write to RAM if this region is write-enabled + //if (m_mtxc_config_reg[0x5f] & 2) // write to RAM if this region is write-enabled #if 1 - if (m_mxtc_config_reg[0x5f] & 2) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5f] & 2) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_e8000_ram + offset); } @@ -371,9 +371,9 @@ WRITE32_MEMBER(savquest_state::bios_e8000_ram_w) WRITE32_MEMBER(savquest_state::bios_ec000_ram_w) { - //if (m_mxtc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled + //if (m_mtxc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled #if 1 - if (m_mxtc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ec000_ram + offset); } @@ -579,7 +579,7 @@ WRITE32_MEMBER(savquest_state::parallel_port_w) READ8_MEMBER(savquest_state::smram_r) { /* TODO: way more complex than this */ - if(m_mxtc_config_reg[0x72] & 0x40) + if(m_mtxc_config_reg[0x72] & 0x40) return m_smram[offset]; else return m_vga->mem_r(space,offset,0xff); @@ -588,7 +588,7 @@ READ8_MEMBER(savquest_state::smram_r) WRITE8_MEMBER(savquest_state::smram_w) { /* TODO: way more complex than this */ - if(m_mxtc_config_reg[0x72] & 0x40) + if(m_mtxc_config_reg[0x72] & 0x40) m_smram[offset] = data; else m_vga->mem_w(space,offset,data,0xff); diff --git a/src/mame/drivers/taitowlf.c b/src/mame/drivers/taitowlf.c index 8c2ae02b10e..3cdbbde6b68 100644 --- a/src/mame/drivers/taitowlf.c +++ b/src/mame/drivers/taitowlf.c @@ -44,7 +44,7 @@ public: m_palette(*this, "palette") { } UINT32 *m_bios_ram; - UINT8 m_mxtc_config_reg[256]; + UINT8 m_mtxc_config_reg[256]; UINT8 m_piix4_config_reg[4][256]; required_region_ptr<UINT8> m_bootscreen_rom; @@ -92,20 +92,20 @@ UINT32 taitowlf_state::screen_update_taitowlf(screen_device &screen, bitmap_rgb3 #endif -// Intel 82439TX System Controller (MXTC) +// Intel 82439TX System Controller (MTXC) -static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg) +static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg) { taitowlf_state *state = busdevice->machine().driver_data<taitowlf_state>(); -// osd_printf_debug("MXTC: read %d, %02X\n", function, reg); +// osd_printf_debug("MTXC: read %d, %02X\n", function, reg); - return state->m_mxtc_config_reg[reg]; + return state->m_mtxc_config_reg[reg]; } -static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) +static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) { taitowlf_state *state = busdevice->machine().driver_data<taitowlf_state>(); -// osd_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data); +// osd_printf_debug("%s:MTXC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data); switch(reg) { @@ -123,17 +123,17 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i } } - state->m_mxtc_config_reg[reg] = data; + state->m_mtxc_config_reg[reg] = data; } void taitowlf_state::intel82439tx_init() { - m_mxtc_config_reg[0x60] = 0x02; - m_mxtc_config_reg[0x61] = 0x02; - m_mxtc_config_reg[0x62] = 0x02; - m_mxtc_config_reg[0x63] = 0x02; - m_mxtc_config_reg[0x64] = 0x02; - m_mxtc_config_reg[0x65] = 0x02; + m_mtxc_config_reg[0x60] = 0x02; + m_mtxc_config_reg[0x61] = 0x02; + m_mtxc_config_reg[0x62] = 0x02; + m_mtxc_config_reg[0x63] = 0x02; + m_mtxc_config_reg[0x64] = 0x02; + m_mtxc_config_reg[0x65] = 0x02; } static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask) @@ -141,19 +141,19 @@ static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int func UINT32 r = 0; if (ACCESSING_BITS_24_31) { - r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24; + r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24; } if (ACCESSING_BITS_16_23) { - r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16; + r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16; } if (ACCESSING_BITS_8_15) { - r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8; + r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8; } if (ACCESSING_BITS_0_7) { - r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0; + r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0; } return r; } @@ -162,19 +162,19 @@ static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int functi { if (ACCESSING_BITS_24_31) { - mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); } if (ACCESSING_BITS_16_23) { - mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); } if (ACCESSING_BITS_8_15) { - mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); } if (ACCESSING_BITS_0_7) { - mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); } } @@ -257,7 +257,7 @@ WRITE32_MEMBER(taitowlf_state::pnp_data_w) WRITE32_MEMBER(taitowlf_state::bios_ram_w) { - if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ram + offset); } diff --git a/src/mame/drivers/voyager.c b/src/mame/drivers/voyager.c index f18e2e45592..542b225f255 100644 --- a/src/mame/drivers/voyager.c +++ b/src/mame/drivers/voyager.c @@ -30,7 +30,7 @@ public: } UINT32 *m_bios_ram; - UINT8 m_mxtc_config_reg[256]; + UINT8 m_mtxc_config_reg[256]; UINT8 m_piix4_config_reg[4][256]; UINT32 m_idle_skip_ram; @@ -42,20 +42,20 @@ public: }; -// Intel 82439TX System Controller (MXTC) +// Intel 82439TX System Controller (MTXC) -static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg) +static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg) { voyager_state *state = busdevice->machine().driver_data<voyager_state>(); -// osd_printf_debug("MXTC: read %d, %02X\n", function, reg); +// osd_printf_debug("MTXC: read %d, %02X\n", function, reg); - return state->m_mxtc_config_reg[reg]; + return state->m_mtxc_config_reg[reg]; } -static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) +static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) { voyager_state *state = busdevice->machine().driver_data<voyager_state>(); -// osd_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data); +// osd_printf_debug("%s:MTXC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data); switch(reg) { @@ -72,7 +72,7 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i //Execution Hack to avoid crash when switch back from Shadow RAM to Bios ROM, since i386 emu haven't yet pipelined execution structure. //It happens when exit from BIOS SETUP. #if 0 - if ((state->m_mxtc_config_reg[0x63] & 0x50) | ( state->m_mxtc_config_reg[0x63] & 0xA0)) // Only DO if comes a change to disable ROM. + if ((state->m_mtxc_config_reg[0x63] & 0x50) | ( state->m_mtxc_config_reg[0x63] & 0xA0)) // Only DO if comes a change to disable ROM. { if ( busdevice->machine(->safe_pc().device("maincpu"))==0xff74e) state->m_maincpu->set_pc(0xff74d); } @@ -85,17 +85,17 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i } } - state->m_mxtc_config_reg[reg] = data; + state->m_mtxc_config_reg[reg] = data; } void voyager_state::intel82439tx_init() { - m_mxtc_config_reg[0x60] = 0x02; - m_mxtc_config_reg[0x61] = 0x02; - m_mxtc_config_reg[0x62] = 0x02; - m_mxtc_config_reg[0x63] = 0x02; - m_mxtc_config_reg[0x64] = 0x02; - m_mxtc_config_reg[0x65] = 0x02; + m_mtxc_config_reg[0x60] = 0x02; + m_mtxc_config_reg[0x61] = 0x02; + m_mtxc_config_reg[0x62] = 0x02; + m_mtxc_config_reg[0x63] = 0x02; + m_mtxc_config_reg[0x64] = 0x02; + m_mtxc_config_reg[0x65] = 0x02; } static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask) @@ -107,19 +107,19 @@ static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int func if (ACCESSING_BITS_24_31) { - r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24; + r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24; } if (ACCESSING_BITS_16_23) { - r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16; + r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16; } if (ACCESSING_BITS_8_15) { - r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8; + r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8; } if (ACCESSING_BITS_0_7) { - r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0; + r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0; } return r; } @@ -128,19 +128,19 @@ static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int functi { if (ACCESSING_BITS_24_31) { - mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); } if (ACCESSING_BITS_16_23) { - mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); } if (ACCESSING_BITS_8_15) { - mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); } if (ACCESSING_BITS_0_7) { - mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); } } @@ -208,8 +208,8 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi WRITE32_MEMBER(voyager_state::bios_ram_w) { - //if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled - if (m_mxtc_config_reg[0x63] & 0x50) + //if (m_mtxc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x63] & 0x50) { COMBINE_DATA(m_bios_ram + offset); } diff --git a/src/mame/drivers/xtom3d.c b/src/mame/drivers/xtom3d.c index a32852f1761..5d42912f4eb 100644 --- a/src/mame/drivers/xtom3d.c +++ b/src/mame/drivers/xtom3d.c @@ -61,7 +61,7 @@ public: UINT32 *m_bios_ext4_ram; UINT32 *m_isa_ram1; UINT32 *m_isa_ram2; - UINT8 m_mxtc_config_reg[256]; + UINT8 m_mtxc_config_reg[256]; UINT8 m_piix4_config_reg[4][256]; DECLARE_WRITE32_MEMBER( isa_ram1_w ); @@ -78,20 +78,20 @@ public: void intel82439tx_init(); }; -// Intel 82439TX System Controller (MXTC) +// Intel 82439TX System Controller (MTXC) -static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg) +static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg) { xtom3d_state *state = busdevice->machine().driver_data<xtom3d_state>(); -// osd_printf_debug("MXTC: read %d, %02X\n", function, reg); +// osd_printf_debug("MTXC: read %d, %02X\n", function, reg); - return state->m_mxtc_config_reg[reg]; + return state->m_mtxc_config_reg[reg]; } -static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) +static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) { xtom3d_state *state = busdevice->machine().driver_data<xtom3d_state>(); - printf("MXTC: write %d, %02X, %02X\n", function, reg, data); + printf("MTXC: write %d, %02X, %02X\n", function, reg, data); /* memory banking with North Bridge: @@ -167,17 +167,17 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i } } - state->m_mxtc_config_reg[reg] = data; + state->m_mtxc_config_reg[reg] = data; } void xtom3d_state::intel82439tx_init() { - m_mxtc_config_reg[0x60] = 0x02; - m_mxtc_config_reg[0x61] = 0x02; - m_mxtc_config_reg[0x62] = 0x02; - m_mxtc_config_reg[0x63] = 0x02; - m_mxtc_config_reg[0x64] = 0x02; - m_mxtc_config_reg[0x65] = 0x02; + m_mtxc_config_reg[0x60] = 0x02; + m_mtxc_config_reg[0x61] = 0x02; + m_mtxc_config_reg[0x62] = 0x02; + m_mtxc_config_reg[0x63] = 0x02; + m_mtxc_config_reg[0x64] = 0x02; + m_mtxc_config_reg[0x65] = 0x02; } static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask) @@ -185,19 +185,19 @@ static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int func UINT32 r = 0; if (ACCESSING_BITS_24_31) { - r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24; + r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24; } if (ACCESSING_BITS_16_23) { - r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16; + r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16; } if (ACCESSING_BITS_8_15) { - r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8; + r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8; } if (ACCESSING_BITS_0_7) { - r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0; + r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0; } return r; } @@ -206,19 +206,19 @@ static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int functi { if (ACCESSING_BITS_24_31) { - mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); } if (ACCESSING_BITS_16_23) { - mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); } if (ACCESSING_BITS_8_15) { - mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); } if (ACCESSING_BITS_0_7) { - mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); + mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); } } @@ -283,7 +283,7 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi WRITE32_MEMBER(xtom3d_state::isa_ram1_w) { - if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled { COMBINE_DATA(m_isa_ram1 + offset); } @@ -291,7 +291,7 @@ WRITE32_MEMBER(xtom3d_state::isa_ram1_w) WRITE32_MEMBER(xtom3d_state::isa_ram2_w) { - if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled { COMBINE_DATA(m_isa_ram2 + offset); } @@ -299,7 +299,7 @@ WRITE32_MEMBER(xtom3d_state::isa_ram2_w) WRITE32_MEMBER(xtom3d_state::bios_ext1_ram_w) { - if (m_mxtc_config_reg[0x5e] & 0x2) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5e] & 0x2) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ext1_ram + offset); } @@ -308,7 +308,7 @@ WRITE32_MEMBER(xtom3d_state::bios_ext1_ram_w) WRITE32_MEMBER(xtom3d_state::bios_ext2_ram_w) { - if (m_mxtc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ext2_ram + offset); } @@ -317,7 +317,7 @@ WRITE32_MEMBER(xtom3d_state::bios_ext2_ram_w) WRITE32_MEMBER(xtom3d_state::bios_ext3_ram_w) { - if (m_mxtc_config_reg[0x5f] & 0x2) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5f] & 0x2) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ext3_ram + offset); } @@ -326,7 +326,7 @@ WRITE32_MEMBER(xtom3d_state::bios_ext3_ram_w) WRITE32_MEMBER(xtom3d_state::bios_ext4_ram_w) { - if (m_mxtc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ext4_ram + offset); } @@ -335,7 +335,7 @@ WRITE32_MEMBER(xtom3d_state::bios_ext4_ram_w) WRITE32_MEMBER(xtom3d_state::bios_ram_w) { - if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled + if (m_mtxc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled { COMBINE_DATA(m_bios_ram + offset); } |