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author Angelo Salese <angelosa@users.noreply.github.com>2013-01-10 20:08:18 +0000
committer Angelo Salese <angelosa@users.noreply.github.com>2013-01-10 20:08:18 +0000
commit567ccbc18a75b74eaa1fccc4a0e8e2667d3c3c03 (patch)
treed1ba9e280fb1454deefd63833e02820da1bc97da
parent7b174edcd86319c8e7348c37173d806902c4cad2 (diff)
RAM debug hooks (but save item doesn't yet work)ù
-rw-r--r--src/mame/includes/3do.h7
-rw-r--r--src/mame/machine/3do.c56
2 files changed, 63 insertions, 0 deletions
diff --git a/src/mame/includes/3do.h b/src/mame/includes/3do.h
index 80512a49879..dcd46435706 100644
--- a/src/mame/includes/3do.h
+++ b/src/mame/includes/3do.h
@@ -125,6 +125,11 @@ struct SVF {
UINT32 color;
};
+struct DSPP {
+ UINT16 *N;
+ UINT16 *EI;
+ UINT16 *EO;
+};
class _3do_state : public driver_device
{
@@ -142,7 +147,9 @@ public:
MADAM m_madam;
CLIO m_clio;
SVF m_svf;
+ DSPP m_dspp;
UINT8 m_nvram[0x8000];
+
// UINT8 m_video_bits[512];
DECLARE_READ8_MEMBER(_3do_nvarea_r);
DECLARE_WRITE8_MEMBER(_3do_nvarea_w);
diff --git a/src/mame/machine/3do.c b/src/mame/machine/3do.c
index 28524b5319c..aa2e84c5c6f 100644
--- a/src/mame/machine/3do.c
+++ b/src/mame/machine/3do.c
@@ -667,6 +667,24 @@ READ32_MEMBER(_3do_state::_3do_clio_r)
logerror( "%08X: CLIO read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset * 4 );
}
+ /* TODO: for debug, to be removed once that we write the CPU core */
+ if(offset >= 0x3800/4 && offset <= 0x39ff/4)
+ {
+ UINT32 res = 0;
+ offset &= (0xff/4);
+ res = (m_dspp.EO[(offset<<1)+0] << 16);
+ res |= (m_dspp.EO[(offset<<1)+1] & 0xffff);
+ return res;
+ }
+
+ if(offset >= 0x3c00/4 && offset <= 0x3fff/4)
+ {
+ UINT16 res;
+ offset &= (0x1ff/4);
+ res = m_dspp.EO[offset] & 0xffff;
+ return res;
+ }
+
switch( offset )
{
case 0x0000/4:
@@ -773,6 +791,37 @@ WRITE32_MEMBER(_3do_state::_3do_clio_w)
offset != 0x118/4 && offset != 0x11c/4)
logerror( "%08X: CLIO write offset = %08X, data = %08X, mask = %08X\n", machine().device("maincpu")->safe_pc(), offset*4, data, mem_mask );
+ /* TODO: for debug, to be removed once that we write the CPU core */
+ if(offset >= 0x1800/4 && offset <= 0x1fff/4)
+ {
+ offset &= (0x3ff/4);
+ m_dspp.N[(offset<<1)+0] = data >> 16;
+ m_dspp.N[(offset<<1)+1] = data & 0xffff;
+ return;
+ }
+
+ if(offset >= 0x2000/4 && offset <= 0x2fff/4)
+ {
+ offset &= (0x7ff/4);
+ m_dspp.N[offset] = data & 0xffff;
+ return;
+ }
+
+ if(offset >= 0x3000/4 && offset <= 0x31ff/4)
+ {
+ offset &= (0xff/4);
+ m_dspp.EI[(offset<<1)+0] = data >> 16;
+ m_dspp.EI[(offset<<1)+1] = data & 0xffff;
+ return;
+ }
+
+ if(offset >= 0x3400/4 && offset <= 0x37ff/4)
+ {
+ offset &= (0x1ff/4);
+ m_dspp.EI[offset] = data & 0xffff;
+ return;
+ }
+
switch( offset )
{
case 0x0000/4:
@@ -983,6 +1032,13 @@ void _3do_clio_init( running_machine &machine, screen_device *screen )
state->m_clio.cstatbits = 0x01; /* bit 0 = reset of clio caused by power on */
state->m_clio.unclerev = 0x03800000;
state->m_clio.expctl = 0x80; /* ARM has the expansion bus */
+ state->m_dspp.N = auto_alloc_array(machine, UINT16, 0x800 );
+ state->m_dspp.EI = auto_alloc_array(machine, UINT16, 0x200 );
+ state->m_dspp.EO = auto_alloc_array(machine, UINT16, 0x200 );
+
+ state_save_register_global_pointer(machine, state->m_dspp.N, 0x800);
+ state_save_register_global_pointer(machine, state->m_dspp.EI, 0x200);
+ state_save_register_global_pointer(machine, state->m_dspp.EO, 0x200);
}