diff options
| author | 2008-06-10 20:10:57 +0000 | |
|---|---|---|
| committer | 2008-06-10 20:10:57 +0000 | |
| commit | a96458747d41790e4e6fa62851a4d657bb1c8603 (patch) | |
| tree | aceefd3d51df9ddb85fff964d15809964f7e04e9 | |
| parent | 623b9cd69049654ecd6ad2eafe8c0ffbfd881438 (diff) | |
PPC common:
* reduced address bus width of 4xx series to 31 bits per the
documentation
PPC DRC:
* fixed bug that would jump to incorrect PC after filling the
TLB during a mismatch event
* added explicit address truncation to 31 bits for 4xx series
* added new PPCDRC_ACCURATE_SINGLES option, which removes the
excessive (and very likely unecessary) extra rounding when
performing the "fast" single-precision floating point ops
Konami drivers:
* designated fast RAM accesses for work RAM
* removed unnecessary mirroring
Model 3:
* identified and fixed VBLANK bit in real3d status which was
causing the system to hang at startup
* designated fast RAM accesses for work RAM
53C810:
* changed read/write handles to proper READ8/WRITE8_HANDLER
callbacks so they can eventually be used directly
| -rw-r--r-- | src/emu/cpu/powerpc/ppc.h | 3 | ||||
| -rw-r--r-- | src/emu/cpu/powerpc/ppccom.c | 3 | ||||
| -rw-r--r-- | src/emu/cpu/powerpc/ppcdrc.c | 21 | ||||
| -rw-r--r-- | src/emu/machine/53c810.c | 76 | ||||
| -rw-r--r-- | src/emu/machine/53c810.h | 4 | ||||
| -rw-r--r-- | src/mame/drivers/firebeat.c | 4 | ||||
| -rw-r--r-- | src/mame/drivers/gticlub.c | 54 | ||||
| -rw-r--r-- | src/mame/drivers/hornet.c | 40 | ||||
| -rw-r--r-- | src/mame/drivers/model3.c | 108 | ||||
| -rw-r--r-- | src/mame/drivers/nwk-tr.c | 50 | ||||
| -rw-r--r-- | src/mame/drivers/ultrsprt.c | 24 | ||||
| -rw-r--r-- | src/mame/drivers/zr107.c | 50 |
12 files changed, 273 insertions, 164 deletions
diff --git a/src/emu/cpu/powerpc/ppc.h b/src/emu/cpu/powerpc/ppc.h index 8e4d4c12ceb..37a3263190f 100644 --- a/src/emu/cpu/powerpc/ppc.h +++ b/src/emu/cpu/powerpc/ppc.h @@ -176,8 +176,9 @@ void mpc8240_get_info(UINT32 state, cpuinfo *info); #define PPCDRC_STRICT_VERIFY 0x0001 /* verify all instructions */ #define PPCDRC_FLUSH_PC 0x0002 /* flush the PC value before each memory access */ +#define PPCDRC_ACCURATE_SINGLES 0x0004 /* do excessive rounding to make single-precision results "accurate" */ -#define PPCDRC_COMPATIBLE_OPTIONS (PPCDRC_STRICT_VERIFY | PPCDRC_FLUSH_PC) +#define PPCDRC_COMPATIBLE_OPTIONS (PPCDRC_STRICT_VERIFY | PPCDRC_FLUSH_PC | PPCDRC_ACCURATE_SINGLES) #define PPCDRC_FASTEST_OPTIONS (0) #endif /* __PPC_H__ */ diff --git a/src/emu/cpu/powerpc/ppccom.c b/src/emu/cpu/powerpc/ppccom.c index 1e28b4d463c..0ee68c35858 100644 --- a/src/emu/cpu/powerpc/ppccom.c +++ b/src/emu/cpu/powerpc/ppccom.c @@ -482,7 +482,7 @@ void ppccom_tlb_fill(powerpc_state *ppc) { /* assume success and direct translation */ ppc->param0 = 0; - transaddr = address; + transaddr = address & 0x7fffffff; /* only check if PE is enabled */ if (ppc->msr & MSR4XX_PE) @@ -1876,6 +1876,7 @@ void ppc4xx_get_info(powerpc_state *ppc, UINT32 state, cpuinfo *info) case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_4: info->i = ppc4xx_get_irq_line(ppc, PPC4XX_IRQ_BIT_EXT4); break; case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break; + case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 31; break; case CPUINFO_INT_LOGADDR_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 0; break; case CPUINFO_INT_PAGE_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break; diff --git a/src/emu/cpu/powerpc/ppcdrc.c b/src/emu/cpu/powerpc/ppcdrc.c index 900f169fe96..9e81ce5d2b3 100644 --- a/src/emu/cpu/powerpc/ppcdrc.c +++ b/src/emu/cpu/powerpc/ppcdrc.c @@ -1224,6 +1224,7 @@ static void static_generate_tlb_mismatch(drcuml_state *drcuml) UML_CALLC(block, ppccom_tlb_fill, ppc); // callc tlbfill,ppc UML_CMP(block, MEM(&ppc->param0), IMM(1)); // cmp [param0],1 UML_JMPc(block, IF_A, isi = label++); // jmp isi,A + UML_MOV(block, MEM(&ppc->pc), IREG(0)); // mov <pc>,i0 save_fast_iregs(block); // <save fastregs> UML_EXIT(block, IMM(EXECUTE_MISSING_CODE)); // exit EXECUTE_MISSING_CODE UML_LABEL(block, isi); // isi: @@ -1493,6 +1494,8 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int mode, int UML_LABEL(block, tlbreturn = label++); // tlbreturn: UML_ROLINS(block, IREG(0), IREG(3), IMM(0), IMM(0xfffff000)); // rolins i0,i3,0,0xfffff000 } + else if (ppc->cap & PPCCAP_4XX) + UML_AND(block, IREG(0), IREG(0), IMM(0x7fffffff)); // and i0,i0,0x7fffffff UML_XOR(block, IREG(0), IREG(0), IMM((mode & MODE_LITTLE_ENDIAN) ? (8 - size) : 0)); // xor i0,i0,8-size for (ramnum = 0; ramnum < PPC_MAX_FASTRAM; ramnum++) @@ -3698,26 +3701,36 @@ static int generate_instruction_3b(drcuml_block *block, compiler_state *compiler switch (opswitch) { case 0x15: /* FADDSx */ + if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDADD(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdadd f0,ra,rb UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 return TRUE; case 0x14: /* FSUBSx */ + if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDSUB(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdsub f0,ra,rb UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 return TRUE; case 0x19: /* FMULSx */ + if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdmul f0,ra,rb UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 return TRUE; case 0x12: /* FDIVSx */ + if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDDIV(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fddiv f0,ra,rb UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 return TRUE; case 0x16: /* FSQRTSx */ + if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDSQRT(block, FREG(0), F64(G_RB(op))); // fdsqrt f0,rb UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 return TRUE; @@ -3729,18 +3742,24 @@ static int generate_instruction_3b(drcuml_block *block, compiler_state *compiler return TRUE; case 0x1d: /* FMADDSx */ + if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 return TRUE; case 0x1c: /* FMSUBSx */ + if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDSUB(block, FREG(0), FREG(0), F64(G_RB(op))); // fdsub f0,f0,rb UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 return TRUE; case 0x1f: /* FNMADDSx */ + if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb UML_FDNEG(block, FREG(0), FREG(0)); // fdneg f0,f0 @@ -3748,6 +3767,8 @@ static int generate_instruction_3b(drcuml_block *block, compiler_state *compiler return TRUE; case 0x1e: /* FNMSUBSx */ + if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDSUB(block, FREG(0), F64(G_RB(op)), FREG(0)); // fdsub f0,rb,f0 UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 diff --git a/src/emu/machine/53c810.c b/src/emu/machine/53c810.c index 3fa9db4e2c5..47128431a31 100644 --- a/src/emu/machine/53c810.c +++ b/src/emu/machine/53c810.c @@ -444,10 +444,10 @@ static void dma_exec(void) } } -UINT8 lsi53c810_reg_r(int reg) +READ8_HANDLER( lsi53c810_reg_r ) { - logerror("53c810: read reg %d:0x%x (PC=%x)\n", reg, reg, activecpu_get_pc()); - switch(reg) + logerror("53c810: read reg %d:0x%x (PC=%x)\n", offset, offset, activecpu_get_pc()); + switch(offset) { case 0x00: /* SCNTL0 */ return lsi810.scntl0; @@ -497,7 +497,7 @@ UINT8 lsi53c810_reg_r(int reg) case 0x35: case 0x36: case 0x37: - return lsi810.scratch_a[reg % 4]; + return lsi810.scratch_a[offset % 4]; case 0x39: /* DIEN */ return lsi810.dien; case 0x3b: /* DCNTL */ @@ -516,81 +516,81 @@ UINT8 lsi53c810_reg_r(int reg) case 0x5d: case 0x5e: case 0x5f: - return lsi810.scratch_b[reg % 4]; + return lsi810.scratch_b[offset % 4]; default: - fatalerror("LSI53C810: reg_r: Unknown reg %02X", reg); + fatalerror("LSI53C810: reg_r: Unknown reg %02X", offset); } return 0; } -void lsi53c810_reg_w(running_machine *machine, int reg, UINT8 value) +WRITE8_HANDLER( lsi53c810_reg_w ) { - logerror("53c810: %02x to reg %d:0x%x (PC=%x)\n", value, reg, reg, activecpu_get_pc()); - switch(reg) + logerror("53c810: %02x to reg %d:0x%x (PC=%x)\n", data, offset, offset, activecpu_get_pc()); + switch(offset) { case 0x00: /* SCNTL0 */ - lsi810.scntl0 = value; + lsi810.scntl0 = data; break; case 0x01: /* SCNTL1 */ - lsi810.scntl1 = value; + lsi810.scntl1 = data; break; case 0x02: /* SCNTL2 */ - lsi810.scntl2 = value; + lsi810.scntl2 = data; break; case 0x03: /* SCNTL3 */ - lsi810.scntl3 = value; + lsi810.scntl3 = data; break; case 0x04: /* SCID */ - lsi810.scid = value; + lsi810.scid = data; break; case 0x09: /* SOCL */ - lsi810.socl = value; + lsi810.socl = data; break; case 0x0d: /* SSTAT0 */ - lsi810.sstat0 = value; + lsi810.sstat0 = data; break; case 0x0e: /* SSTAT1 */ - lsi810.sstat1 = value; + lsi810.sstat1 = data; break; case 0x0f: /* SSTAT2 */ - lsi810.sstat2 = value; + lsi810.sstat2 = data; break; case 0x10: /* DSA [7-0] */ lsi810.dsa &= 0xffffff00; - lsi810.dsa |= value; + lsi810.dsa |= data; break; case 0x11: /* DSA [15-8] */ lsi810.dsa &= 0xffff00ff; - lsi810.dsa |= value << 8; + lsi810.dsa |= data << 8; break; case 0x12: /* DSA [23-16] */ lsi810.dsa &= 0xff00ffff; - lsi810.dsa |= value << 16; + lsi810.dsa |= data << 16; break; case 0x13: /* DSA [31-24] */ lsi810.dsa &= 0x00ffffff; - lsi810.dsa |= value << 24; + lsi810.dsa |= data << 24; break; case 0x14: /* ISTAT */ - lsi810.istat = value; + lsi810.istat = data; break; case 0x2c: /* DSP [7-0] */ lsi810.dsp &= 0xffffff00; - lsi810.dsp |= value; + lsi810.dsp |= data; break; case 0x2d: /* DSP [15-8] */ lsi810.dsp &= 0xffff00ff; - lsi810.dsp |= value << 8; + lsi810.dsp |= data << 8; break; case 0x2e: /* DSP [23-16] */ lsi810.dsp &= 0xff00ffff; - lsi810.dsp |= value << 16; + lsi810.dsp |= data << 16; break; case 0x2f: /* DSP [31-24] */ lsi810.dsp &= 0x00ffffff; - lsi810.dsp |= value << 24; + lsi810.dsp |= data << 24; lsi810.halted = 0; if((lsi810.dmode & 0x1) == 0 && !lsi810.halted) { dma_exec(); @@ -600,16 +600,16 @@ void lsi53c810_reg_w(running_machine *machine, int reg, UINT8 value) case 0x35: case 0x36: case 0x37: - lsi810.scratch_a[reg % 4] = value; + lsi810.scratch_a[offset % 4] = data; break; case 0x38: /* DMODE */ - lsi810.dmode = value; + lsi810.dmode = data; break; case 0x39: /* DIEN */ - lsi810.dien = value; + lsi810.dien = data; break; case 0x3b: /* DCNTL */ - lsi810.dcntl = value; + lsi810.dcntl = data; if(lsi810.dcntl & 0x14 && !lsi810.halted) /* single-step & start DMA */ { @@ -630,29 +630,29 @@ void lsi53c810_reg_w(running_machine *machine, int reg, UINT8 value) } break; case 0x40: /* SIEN0 */ - lsi810.sien0 = value; + lsi810.sien0 = data; break; case 0x41: /* SIEN1 */ - lsi810.sien1 = value; + lsi810.sien1 = data; break; case 0x48: /* STIME0 */ - lsi810.stime0 = value; + lsi810.stime0 = data; break; case 0x4a: /* RESPID */ - lsi810.respid = value; + lsi810.respid = data; break; case 0x4d: /* STEST1 */ - lsi810.stest1 = value; + lsi810.stest1 = data; break; case 0x5c: /* SCRATCH B */ case 0x5d: case 0x5e: case 0x5f: - lsi810.scratch_b[reg % 4] = value; + lsi810.scratch_b[offset % 4] = data; break; default: - fatalerror("LSI53C810: reg_w: Unknown reg %02X, %02X", reg, value); + fatalerror("LSI53C810: reg_w: Unknown reg %02X, %02X", offset, data); } } diff --git a/src/emu/machine/53c810.h b/src/emu/machine/53c810.h index 622fa36eb5a..3230c9913a4 100644 --- a/src/emu/machine/53c810.h +++ b/src/emu/machine/53c810.h @@ -19,8 +19,8 @@ extern void lsi53c810_write_data(int bytes, UINT8 *pData); extern void *lsi53c810_get_device(int id); -UINT8 lsi53c810_reg_r(int reg); -void lsi53c810_reg_w(running_machine *machine, int reg, UINT8 value); +READ8_HANDLER( lsi53c810_reg_r ); +WRITE8_HANDLER( lsi53c810_reg_w ); unsigned lsi53c810_dasm(char *buf, UINT32 pc); diff --git a/src/mame/drivers/firebeat.c b/src/mame/drivers/firebeat.c index 026a9e648f9..556cc0f4bb8 100644 --- a/src/mame/drivers/firebeat.c +++ b/src/mame/drivers/firebeat.c @@ -1744,6 +1744,7 @@ static READ16_HANDLER(spu_unk_r) /*****************************************************************************/ static ADDRESS_MAP_START( firebeat_map, ADDRESS_SPACE_PROGRAM, 32 ) + AM_RANGE(0x00000000, 0x01ffffff) AM_RAM AM_RANGE(0x70000000, 0x70000fff) AM_READWRITE(midi_uart_r, midi_uart_w) AM_RANGE(0x70006000, 0x70006003) AM_WRITE(extend_board_irq_w) AM_RANGE(0x70008000, 0x7000800f) AM_READ(keyboard_wheel_r) @@ -1761,8 +1762,7 @@ static ADDRESS_MAP_START( firebeat_map, ADDRESS_SPACE_PROGRAM, 32 ) AM_RANGE(0x7e800100, 0x7e8001ff) AM_READWRITE(gcu1_r, gcu1_w) AM_RANGE(0x7fe00000, 0x7fe0000f) AM_READWRITE(atapi_command_r, atapi_command_w) AM_RANGE(0x7fe80000, 0x7fe8000f) AM_READWRITE(atapi_control_r, atapi_control_w) - AM_RANGE(0x80000000, 0x81ffffff) AM_RAM - AM_RANGE(0xfff80000, 0xffffffff) AM_ROM AM_REGION(REGION_USER1, 0) /* System BIOS */ + AM_RANGE(0x7ff80000, 0x7fffffff) AM_ROM AM_REGION(REGION_USER1, 0) /* System BIOS */ ADDRESS_MAP_END static ADDRESS_MAP_START( spu_map, ADDRESS_SPACE_PROGRAM, 16 ) diff --git a/src/mame/drivers/gticlub.c b/src/mame/drivers/gticlub.c index dc7ee41a920..f1431d8087b 100644 --- a/src/mame/drivers/gticlub.c +++ b/src/mame/drivers/gticlub.c @@ -410,25 +410,38 @@ WRITE32_HANDLER( lanc_ram_w ) /******************************************************************/ +static MACHINE_START( gticlub ) +{ + /* set conservative DRC options */ + cpunum_set_info_int(0, CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS); + + /* configure fast RAM regions for DRC */ + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_SELECT, 0); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_START, 0x00000000); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_END, 0x000fffff); + cpunum_set_info_ptr(0, CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_READONLY, 0); +} + static ADDRESS_MAP_START( gticlub_map, ADDRESS_SPACE_PROGRAM, 32 ) - AM_RANGE(0x00000000, 0x000fffff) AM_MIRROR(0x80000000) AM_RAM AM_BASE(&work_ram) /* Work RAM */ - AM_RANGE(0x74000000, 0x740000ff) AM_MIRROR(0x80000000) AM_READWRITE(K001604_reg_r, K001604_reg_w) - AM_RANGE(0x74010000, 0x7401ffff) AM_MIRROR(0x80000000) AM_RAM_WRITE(paletteram32_w) AM_BASE(&paletteram32) - AM_RANGE(0x74020000, 0x7403ffff) AM_MIRROR(0x80000000) AM_READWRITE(K001604_tile_r, K001604_tile_w) - AM_RANGE(0x74040000, 0x7407ffff) AM_MIRROR(0x80000000) AM_READWRITE(K001604_char_r, K001604_char_w) - AM_RANGE(0x78000000, 0x7800ffff) AM_MIRROR(0x80000000) AM_READWRITE(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc) - AM_RANGE(0x78040000, 0x7804000f) AM_MIRROR(0x80000000) AM_READWRITE(K001006_0_r, K001006_0_w) - AM_RANGE(0x78080000, 0x7808000f) AM_MIRROR(0x80000000) AM_READWRITE(K001006_1_r, K001006_1_w) - AM_RANGE(0x780c0000, 0x780c0003) AM_MIRROR(0x80000000) AM_READWRITE(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc) - AM_RANGE(0x7e000000, 0x7e003fff) AM_MIRROR(0x80000000) AM_READWRITE8(sysreg_r, sysreg_w, 0xffffffff) - AM_RANGE(0x7e008000, 0x7e009fff) AM_MIRROR(0x80000000) AM_READWRITE8(K056230_r, K056230_w, 0xffffffff) - AM_RANGE(0x7e00a000, 0x7e00bfff) AM_MIRROR(0x80000000) AM_READWRITE(lanc_ram_r, lanc_ram_w) - AM_RANGE(0x7e00c000, 0x7e00c007) AM_MIRROR(0x80000000) AM_WRITE(K056800_host_w) - AM_RANGE(0x7e00c000, 0x7e00c007) AM_MIRROR(0x80000000) AM_READ(K056800_host_r) // Hang Pilot - AM_RANGE(0x7e00c008, 0x7e00c00f) AM_MIRROR(0x80000000) AM_READ(K056800_host_r) - AM_RANGE(0x7f000000, 0x7f3fffff) AM_MIRROR(0x80000000) AM_ROM AM_REGION(REGION_USER2, 0) /* Data ROM */ - AM_RANGE(0x7f800000, 0x7f9fffff) AM_MIRROR(0x80000000) AM_ROM AM_SHARE(2) - AM_RANGE(0x7fe00000, 0x7fffffff) AM_MIRROR(0x80000000) AM_ROM AM_REGION(REGION_USER1, 0) AM_SHARE(2) /* Program ROM */ + AM_RANGE(0x00000000, 0x000fffff) AM_RAM AM_BASE(&work_ram) /* Work RAM */ + AM_RANGE(0x74000000, 0x740000ff) AM_READWRITE(K001604_reg_r, K001604_reg_w) + AM_RANGE(0x74010000, 0x7401ffff) AM_RAM_WRITE(paletteram32_w) AM_BASE(&paletteram32) + AM_RANGE(0x74020000, 0x7403ffff) AM_READWRITE(K001604_tile_r, K001604_tile_w) + AM_RANGE(0x74040000, 0x7407ffff) AM_READWRITE(K001604_char_r, K001604_char_w) + AM_RANGE(0x78000000, 0x7800ffff) AM_READWRITE(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc) + AM_RANGE(0x78040000, 0x7804000f) AM_READWRITE(K001006_0_r, K001006_0_w) + AM_RANGE(0x78080000, 0x7808000f) AM_READWRITE(K001006_1_r, K001006_1_w) + AM_RANGE(0x780c0000, 0x780c0003) AM_READWRITE(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc) + AM_RANGE(0x7e000000, 0x7e003fff) AM_READWRITE8(sysreg_r, sysreg_w, 0xffffffff) + AM_RANGE(0x7e008000, 0x7e009fff) AM_READWRITE8(K056230_r, K056230_w, 0xffffffff) + AM_RANGE(0x7e00a000, 0x7e00bfff) AM_READWRITE(lanc_ram_r, lanc_ram_w) + AM_RANGE(0x7e00c000, 0x7e00c007) AM_WRITE(K056800_host_w) + AM_RANGE(0x7e00c000, 0x7e00c007) AM_READ(K056800_host_r) // Hang Pilot + AM_RANGE(0x7e00c008, 0x7e00c00f) AM_READ(K056800_host_r) + AM_RANGE(0x7f000000, 0x7f3fffff) AM_ROM AM_REGION(REGION_USER2, 0) /* Data ROM */ + AM_RANGE(0x7f800000, 0x7f9fffff) AM_ROM AM_SHARE(2) + AM_RANGE(0x7fe00000, 0x7fffffff) AM_ROM AM_REGION(REGION_USER1, 0) AM_SHARE(2) /* Program ROM */ ADDRESS_MAP_END /**********************************************************************/ @@ -718,6 +731,7 @@ static MACHINE_DRIVER_START( gticlub ) MDRV_INTERLEAVE(100) MDRV_NVRAM_HANDLER(gticlub) + MDRV_MACHINE_START(gticlub) MDRV_MACHINE_RESET(gticlub) /* video hardware */ @@ -766,6 +780,7 @@ static MACHINE_DRIVER_START( hangplt ) MDRV_INTERLEAVE(100) MDRV_NVRAM_HANDLER(gticlub) + MDRV_MACHINE_START(gticlub) MDRV_MACHINE_RESET(hangplt) /* video hardware */ @@ -973,9 +988,6 @@ static DRIVER_INIT(hangplt) static DRIVER_INIT(slrasslt) { DRIVER_INIT_CALL(gticlub); - - // enable self-modifying code checks - cpunum_set_info_int(0, CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_STRICT_VERIFY); } /*************************************************************************/ diff --git a/src/mame/drivers/hornet.c b/src/mame/drivers/hornet.c index 9ce76ad5562..d23cfec8eb6 100644 --- a/src/mame/drivers/hornet.c +++ b/src/mame/drivers/hornet.c @@ -760,24 +760,24 @@ static READ32_HANDLER( comm0_unk_r ) /*****************************************************************************/ static ADDRESS_MAP_START( hornet_map, ADDRESS_SPACE_PROGRAM, 32 ) - AM_RANGE(0x00000000, 0x003fffff) AM_MIRROR(0x80000000) AM_RAM AM_BASE(&workram) /* Work RAM */ - AM_RANGE(0x74000000, 0x740000ff) AM_MIRROR(0x80000000) AM_READWRITE(K037122_reg_r, K037122_reg_w) - AM_RANGE(0x74020000, 0x7403ffff) AM_MIRROR(0x80000000) AM_READWRITE(K037122_sram_r, K037122_sram_w) - AM_RANGE(0x74040000, 0x7407ffff) AM_MIRROR(0x80000000) AM_READWRITE(K037122_char_r, K037122_char_w) - AM_RANGE(0x78000000, 0x7800ffff) AM_MIRROR(0x80000000) AM_READWRITE(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc) - AM_RANGE(0x780c0000, 0x780c0003) AM_MIRROR(0x80000000) AM_READWRITE(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc) - AM_RANGE(0x7d000000, 0x7d00ffff) AM_MIRROR(0x80000000) AM_READ8(sysreg_r, 0xffffffff) - AM_RANGE(0x7d010000, 0x7d01ffff) AM_MIRROR(0x80000000) AM_WRITE8(sysreg_w, 0xffffffff) - AM_RANGE(0x7d020000, 0x7d021fff) AM_MIRROR(0x80000000) AM_READWRITE(timekeeper_0_32be_r, timekeeper_0_32be_w) /* M48T58Y RTC/NVRAM */ - AM_RANGE(0x7d030000, 0x7d030007) AM_MIRROR(0x80000000) AM_READWRITE(K056800_host_r, K056800_host_w) - AM_RANGE(0x7d042000, 0x7d043fff) AM_MIRROR(0x80000000) AM_RAM /* COMM BOARD 0 */ - AM_RANGE(0x7d044000, 0x7d044007) AM_MIRROR(0x80000000) AM_READ(comm0_unk_r) - AM_RANGE(0x7d048000, 0x7d048003) AM_MIRROR(0x80000000) AM_WRITE(comm1_w) - AM_RANGE(0x7d04a000, 0x7d04a003) AM_MIRROR(0x80000000) AM_WRITE(comm_rombank_w) - AM_RANGE(0x7d050000, 0x7d05ffff) AM_MIRROR(0x80000000) AM_ROMBANK(1) /* COMM BOARD 1 */ - AM_RANGE(0x7e000000, 0x7e7fffff) AM_MIRROR(0x80000000) AM_ROM AM_REGION(REGION_USER2, 0) /* Data ROM */ - AM_RANGE(0x7f000000, 0x7f3fffff) AM_MIRROR(0x80000000) AM_ROM AM_SHARE(2) - AM_RANGE(0x7fc00000, 0x7fffffff) AM_MIRROR(0x80000000) AM_ROM AM_REGION(REGION_USER1, 0) AM_SHARE(2) /* Program ROM */ + AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_BASE(&workram) /* Work RAM */ + AM_RANGE(0x74000000, 0x740000ff) AM_READWRITE(K037122_reg_r, K037122_reg_w) + AM_RANGE(0x74020000, 0x7403ffff) AM_READWRITE(K037122_sram_r, K037122_sram_w) + AM_RANGE(0x74040000, 0x7407ffff) AM_READWRITE(K037122_char_r, K037122_char_w) + AM_RANGE(0x78000000, 0x7800ffff) AM_READWRITE(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc) + AM_RANGE(0x780c0000, 0x780c0003) AM_READWRITE(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc) + AM_RANGE(0x7d000000, 0x7d00ffff) AM_READ8(sysreg_r, 0xffffffff) + AM_RANGE(0x7d010000, 0x7d01ffff) AM_WRITE8(sysreg_w, 0xffffffff) + AM_RANGE(0x7d020000, 0x7d021fff) AM_READWRITE(timekeeper_0_32be_r, timekeeper_0_32be_w) /* M48T58Y RTC/NVRAM */ + AM_RANGE(0x7d030000, 0x7d030007) AM_READWRITE(K056800_host_r, K056800_host_w) + AM_RANGE(0x7d042000, 0x7d043fff) AM_RAM /* COMM BOARD 0 */ + AM_RANGE(0x7d044000, 0x7d044007) AM_READ(comm0_unk_r) + AM_RANGE(0x7d048000, 0x7d048003) AM_WRITE(comm1_w) + AM_RANGE(0x7d04a000, 0x7d04a003) AM_WRITE(comm_rombank_w) + AM_RANGE(0x7d050000, 0x7d05ffff) AM_ROMBANK(1) /* COMM BOARD 1 */ + AM_RANGE(0x7e000000, 0x7e7fffff) AM_ROM AM_REGION(REGION_USER2, 0) /* Data ROM */ + AM_RANGE(0x7f000000, 0x7f3fffff) AM_ROM AM_SHARE(2) + AM_RANGE(0x7fc00000, 0x7fffffff) AM_ROM AM_REGION(REGION_USER1, 0) AM_SHARE(2) /* Program ROM */ ADDRESS_MAP_END /*****************************************************************************/ @@ -967,8 +967,8 @@ static MACHINE_START( hornet ) /* configure fast RAM regions for DRC */ cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_SELECT, 0); - cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_START, 0x80000000); - cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_END, 0x803fffff); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_START, 0x00000000); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_END, 0x003fffff); cpunum_set_info_ptr(0, CPUINFO_PTR_PPC_FASTRAM_BASE, workram); cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_READONLY, 0); } diff --git a/src/mame/drivers/model3.c b/src/mame/drivers/model3.c index 61818b7c141..c524f6ac2b4 100644 --- a/src/mame/drivers/model3.c +++ b/src/mame/drivers/model3.c @@ -433,11 +433,6 @@ void model3_set_irq_line(running_machine *machine, UINT8 bit, int state) } -#define BYTE_REVERSE32(x) (((x >> 24) & 0xff) | \ - ((x >> 8) & 0xff00) | \ - ((x << 8) & 0xff0000) | \ - ((x << 24) & 0xff000000)) - static UINT32 pci_device_get_reg(int device, int reg) { switch(device) @@ -581,7 +576,7 @@ static WRITE64_HANDLER( mpc105_addr_w ) { if (ACCESSING_BITS_32_63) { - UINT32 d = BYTE_REVERSE32((UINT32)(data >> 32)); + UINT32 d = FLIPENDIAN_INT32((UINT32)(data >> 32)); mpc105_addr = data >> 32; pci_bus = (d >> 16) & 0xff; @@ -594,22 +589,22 @@ static WRITE64_HANDLER( mpc105_addr_w ) static READ64_HANDLER( mpc105_data_r ) { if(pci_device == 0) { - return ((UINT64)(BYTE_REVERSE32(mpc105_regs[(pci_reg/2)+1])) << 32) | - ((UINT64)(BYTE_REVERSE32(mpc105_regs[(pci_reg/2)+0]))); + return ((UINT64)(FLIPENDIAN_INT32(mpc105_regs[(pci_reg/2)+1])) << 32) | + ((UINT64)(FLIPENDIAN_INT32(mpc105_regs[(pci_reg/2)+0]))); } - return BYTE_REVERSE32(pci_device_get_reg(pci_device, pci_reg)); + return FLIPENDIAN_INT32(pci_device_get_reg(pci_device, pci_reg)); } static WRITE64_HANDLER( mpc105_data_w ) { if(pci_device == 0) { - mpc105_regs[(pci_reg/2)+1] = BYTE_REVERSE32((UINT32)(data >> 32)); - mpc105_regs[(pci_reg/2)+0] = BYTE_REVERSE32((UINT32)(data)); + mpc105_regs[(pci_reg/2)+1] = FLIPENDIAN_INT32((UINT32)(data >> 32)); + mpc105_regs[(pci_reg/2)+0] = FLIPENDIAN_INT32((UINT32)(data)); return; } if (ACCESSING_BITS_0_31) { - pci_device_set_reg(pci_device, pci_reg, BYTE_REVERSE32((UINT32)data)); + pci_device_set_reg(pci_device, pci_reg, FLIPENDIAN_INT32((UINT32)data)); } } @@ -659,7 +654,7 @@ static WRITE64_HANDLER( mpc106_addr_w ) { if (ACCESSING_BITS_32_63) { - UINT32 d = BYTE_REVERSE32((UINT32)(data >> 32)); + UINT32 d = FLIPENDIAN_INT32((UINT32)(data >> 32)); if (((d >> 8) & 0xffffff) == 0x800000) { @@ -680,29 +675,29 @@ static WRITE64_HANDLER( mpc106_addr_w ) static READ64_HANDLER( mpc106_data_r ) { if(pci_device == 0) { - return ((UINT64)(BYTE_REVERSE32(mpc106_regs[(pci_reg/2)+1])) << 32) | - ((UINT64)(BYTE_REVERSE32(mpc106_regs[(pci_reg/2)+0]))); + return ((UINT64)(FLIPENDIAN_INT32(mpc106_regs[(pci_reg/2)+1])) << 32) | + ((UINT64)(FLIPENDIAN_INT32(mpc106_regs[(pci_reg/2)+0]))); } if (ACCESSING_BITS_32_63) { - return (UINT64)(BYTE_REVERSE32(pci_device_get_reg(pci_device, pci_reg))) << 32; + return (UINT64)(FLIPENDIAN_INT32(pci_device_get_reg(pci_device, pci_reg))) << 32; } else { - return (UINT64)(BYTE_REVERSE32(pci_device_get_reg(pci_device, pci_reg))); + return (UINT64)(FLIPENDIAN_INT32(pci_device_get_reg(pci_device, pci_reg))); } } static WRITE64_HANDLER( mpc106_data_w ) { if(pci_device == 0) { - mpc106_regs[(pci_reg/2)+1] = BYTE_REVERSE32((UINT32)(data >> 32)); - mpc106_regs[(pci_reg/2)+0] = BYTE_REVERSE32((UINT32)(data)); + mpc106_regs[(pci_reg/2)+1] = FLIPENDIAN_INT32((UINT32)(data >> 32)); + mpc106_regs[(pci_reg/2)+0] = FLIPENDIAN_INT32((UINT32)(data)); return; } if (ACCESSING_BITS_0_31) { - pci_device_set_reg(pci_device, pci_reg, BYTE_REVERSE32((UINT32)data)); + pci_device_set_reg(pci_device, pci_reg, FLIPENDIAN_INT32((UINT32)data)); } } @@ -745,28 +740,28 @@ static READ64_HANDLER(scsi_r) int reg = offset*8; UINT64 r = 0; if (ACCESSING_BITS_56_63) { - r |= (UINT64)lsi53c810_reg_r(reg+0) << 56; + r |= (UINT64)lsi53c810_reg_r(machine, reg+0) << 56; } if (ACCESSING_BITS_48_55) { - r |= (UINT64)lsi53c810_reg_r(reg+1) << 48; + r |= (UINT64)lsi53c810_reg_r(machine, reg+1) << 48; } if (ACCESSING_BITS_40_47) { - r |= (UINT64)lsi53c810_reg_r(reg+2) << 40; + r |= (UINT64)lsi53c810_reg_r(machine, reg+2) << 40; } if (ACCESSING_BITS_32_39) { - r |= (UINT64)lsi53c810_reg_r(reg+3) << 32; + r |= (UINT64)lsi53c810_reg_r(machine, reg+3) << 32; } if (ACCESSING_BITS_24_31) { - r |= (UINT64)lsi53c810_reg_r(reg+4) << 24; + r |= (UINT64)lsi53c810_reg_r(machine, reg+4) << 24; } if (ACCESSING_BITS_16_23) { - r |= (UINT64)lsi53c810_reg_r(reg+5) << 16; + r |= (UINT64)lsi53c810_reg_r(machine, reg+5) << 16; } if (ACCESSING_BITS_8_15) { - r |= (UINT64)lsi53c810_reg_r(reg+6) << 8; + r |= (UINT64)lsi53c810_reg_r(machine, reg+6) << 8; } if (ACCESSING_BITS_0_7) { - r |= (UINT64)lsi53c810_reg_r(reg+7) << 0; + r |= (UINT64)lsi53c810_reg_r(machine, reg+7) << 0; } return r; @@ -805,13 +800,12 @@ static UINT32 scsi_fetch(UINT32 dsp) { UINT32 result; result = program_read_dword_64be(dsp); - return BYTE_REVERSE32(result); + return FLIPENDIAN_INT32(result); } static void scsi_irq_callback(running_machine *machine, int state) { scsi_irq_state = state; -// model3_irq_state |= irq_enable & ~0x60; /* FIXME: enable only SCSI interrupt */ update_irq_state(machine); } @@ -847,18 +841,18 @@ static WRITE64_HANDLER( real3d_dma_w ) { case 0: if(ACCESSING_BITS_32_63) { /* DMA source address */ - dma_source = BYTE_REVERSE32((UINT32)(data >> 32)); + dma_source = FLIPENDIAN_INT32((UINT32)(data >> 32)); return; } if(ACCESSING_BITS_0_31) { /* DMA destination address */ - dma_dest = BYTE_REVERSE32((UINT32)(data)); + dma_dest = FLIPENDIAN_INT32((UINT32)(data)); return; } break; case 1: if(ACCESSING_BITS_32_63) /* DMA length */ { - int length = BYTE_REVERSE32((UINT32)(data >> 32)) * 4; + int length = FLIPENDIAN_INT32((UINT32)(data >> 32)) * 4; if (dma_endian & 0x80) { real3d_dma_callback(dma_source, dma_dest, length, 0); @@ -887,9 +881,9 @@ static WRITE64_HANDLER( real3d_dma_w ) break; case 2: if(ACCESSING_BITS_32_63) { /* DMA command */ - UINT32 cmd = BYTE_REVERSE32((UINT32)(data >> 32)); + UINT32 cmd = FLIPENDIAN_INT32((UINT32)(data >> 32)); if(cmd & 0x20000000) { - dma_data = BYTE_REVERSE32(real3d_device_id); /* (PCI Vendor & Device ID) */ + dma_data = FLIPENDIAN_INT32(real3d_device_id); /* (PCI Vendor & Device ID) */ } else if(cmd & 0x80000000) { dma_status ^= 0xffffffff; @@ -1012,15 +1006,38 @@ static void model3_exit(running_machine *machine) lsi53c810_exit(&scsi_intf); } +static void configure_fast_ram(running_machine *machine) +{ + /* set conservative DRC options */ + cpunum_set_info_int(0, CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS - PPCDRC_ACCURATE_SINGLES); + + /* configure fast RAM regions for DRC */ + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_SELECT, 0); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_START, 0x00000000); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_END, 0x007fffff); + cpunum_set_info_ptr(0, CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_READONLY, 0); +} + static MACHINE_START(model3_10) { lsi53c810_init(&scsi_intf); add_exit_callback(machine, model3_exit); + configure_fast_ram(machine); } static MACHINE_START(model3_15) { lsi53c810_init(&scsi_intf); add_exit_callback(machine, model3_exit); + configure_fast_ram(machine); +} +static MACHINE_START(model3_20) +{ + configure_fast_ram(machine); +} +static MACHINE_START(model3_21) +{ + configure_fast_ram(machine); } static void model3_init(running_machine *machine, int step) @@ -1332,6 +1349,14 @@ static UINT64 real3d_status = 0; static READ64_HANDLER(real3d_status_r) { real3d_status ^= U64(0xffffffffffffffff); + if (offset == 0) + { + /* pretty sure this is VBLANK */ + real3d_status &= ~U64(0x0000000200000000); + if (video_screen_get_vblank(machine->primary_screen)) + real3d_status |= U64(0x0000000200000000); + return real3d_status; + } return real3d_status; } @@ -4118,9 +4143,8 @@ static MACHINE_DRIVER_START( model3_10 ) MDRV_SCREEN_ADD("main", RASTER) MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16) MDRV_SCREEN_REFRESH_RATE(60) - MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0)) - MDRV_SCREEN_SIZE(496, 384) MDRV_SCREEN_VISIBLE_AREA(0, 495, 0, 383) + MDRV_SCREEN_SIZE(512, 400) MDRV_PALETTE_LENGTH(32768) MDRV_PALETTE_INIT(RRRRR_GGGGG_BBBBB) @@ -4156,9 +4180,8 @@ static MACHINE_DRIVER_START( model3_15 ) MDRV_SCREEN_ADD("main", RASTER) MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16) MDRV_SCREEN_REFRESH_RATE(60) - MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0)) - MDRV_SCREEN_SIZE(496, 384) MDRV_SCREEN_VISIBLE_AREA(0, 495, 0, 383) + MDRV_SCREEN_SIZE(496, 400) MDRV_PALETTE_LENGTH(32768) MDRV_PALETTE_INIT(RRRRR_GGGGG_BBBBB) @@ -4186,6 +4209,7 @@ static MACHINE_DRIVER_START( model3_20 ) MDRV_CPU_ADD(M68000, 12000000) MDRV_CPU_PROGRAM_MAP(model3_snd, 0) + MDRV_MACHINE_START(model3_20) MDRV_MACHINE_RESET(model3_20) MDRV_NVRAM_HANDLER(model3) @@ -4193,9 +4217,8 @@ static MACHINE_DRIVER_START( model3_20 ) MDRV_SCREEN_ADD("main", RASTER) MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16) MDRV_SCREEN_REFRESH_RATE(60) - MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0)) - MDRV_SCREEN_SIZE(496, 384) MDRV_SCREEN_VISIBLE_AREA(0, 495, 0, 383) + MDRV_SCREEN_SIZE(496, 400) MDRV_PALETTE_LENGTH(32768) MDRV_PALETTE_INIT(RRRRR_GGGGG_BBBBB) @@ -4223,6 +4246,7 @@ static MACHINE_DRIVER_START( model3_21 ) MDRV_CPU_ADD(M68000, 12000000) MDRV_CPU_PROGRAM_MAP(model3_snd, 0) + MDRV_MACHINE_START(model3_21) MDRV_MACHINE_RESET(model3_21) MDRV_NVRAM_HANDLER(model3) @@ -4231,8 +4255,8 @@ static MACHINE_DRIVER_START( model3_21 ) MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16) MDRV_SCREEN_REFRESH_RATE(60) MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0)) - MDRV_SCREEN_SIZE(496, 384) MDRV_SCREEN_VISIBLE_AREA(0, 495, 0, 383) + MDRV_SCREEN_SIZE(496, 400) MDRV_PALETTE_LENGTH(32768) MDRV_PALETTE_INIT(RRRRR_GGGGG_BBBBB) diff --git a/src/mame/drivers/nwk-tr.c b/src/mame/drivers/nwk-tr.c index c51026070a7..a01bf3f9ce1 100644 --- a/src/mame/drivers/nwk-tr.c +++ b/src/mame/drivers/nwk-tr.c @@ -755,25 +755,38 @@ static WRITE32_HANDLER( lanc2_w ) /*****************************************************************************/ +static MACHINE_START( nwktr ) +{ + /* set conservative DRC options */ + cpunum_set_info_int(0, CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS); + + /* configure fast RAM regions for DRC */ + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_SELECT, 0); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_START, 0x00000000); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_END, 0x003fffff); + cpunum_set_info_ptr(0, CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_READONLY, 0); +} + static ADDRESS_MAP_START( nwktr_map, ADDRESS_SPACE_PROGRAM, 32 ) - AM_RANGE(0x00000000, 0x003fffff) AM_MIRROR(0x80000000) AM_RAM AM_BASE(&work_ram) /* Work RAM */ - AM_RANGE(0x74000000, 0x740000ff) AM_MIRROR(0x80000000) AM_READWRITE(K001604_reg_r, K001604_reg_w) - AM_RANGE(0x74010000, 0x74017fff) AM_MIRROR(0x80000000) AM_RAM_WRITE(paletteram32_w) AM_BASE(&paletteram32) - AM_RANGE(0x74020000, 0x7403ffff) AM_MIRROR(0x80000000) AM_READWRITE(K001604_tile_r, K001604_tile_w) - AM_RANGE(0x74040000, 0x7407ffff) AM_MIRROR(0x80000000) AM_READWRITE(K001604_char_r, K001604_char_w) - AM_RANGE(0x78000000, 0x7800ffff) AM_MIRROR(0x80000000) AM_READWRITE(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc) - AM_RANGE(0x780c0000, 0x780c0003) AM_MIRROR(0x80000000) AM_READWRITE(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc) - AM_RANGE(0x7d000000, 0x7d00ffff) AM_MIRROR(0x80000000) AM_READ(sysreg_r) - AM_RANGE(0x7d010000, 0x7d01ffff) AM_MIRROR(0x80000000) AM_WRITE(sysreg_w) - AM_RANGE(0x7d020000, 0x7d021fff) AM_MIRROR(0x80000000) AM_READWRITE(timekeeper_0_32be_r, timekeeper_0_32be_w) /* M48T58Y RTC/NVRAM */ - AM_RANGE(0x7d030000, 0x7d030007) AM_MIRROR(0x80000000) AM_READ(K056800_host_r) - AM_RANGE(0x7d030000, 0x7d030007) AM_MIRROR(0x80000000) AM_WRITE(K056800_host_w) - AM_RANGE(0x7d030008, 0x7d03000f) AM_MIRROR(0x80000000) AM_WRITE(K056800_host_w) - AM_RANGE(0x7d040000, 0x7d04ffff) AM_MIRROR(0x80000000) AM_READWRITE(lanc1_r, lanc1_w) - AM_RANGE(0x7d050000, 0x7d05ffff) AM_MIRROR(0x80000000) AM_READWRITE(lanc2_r, lanc2_w) - AM_RANGE(0x7e000000, 0x7e7fffff) AM_MIRROR(0x80000000) AM_ROM AM_REGION(REGION_USER2, 0) /* Data ROM */ - AM_RANGE(0x7f000000, 0x7f1fffff) AM_MIRROR(0x80000000) AM_ROM AM_SHARE(2) - AM_RANGE(0x7fe00000, 0x7fffffff) AM_MIRROR(0x80000000) AM_ROM AM_REGION(REGION_USER1, 0) AM_SHARE(2) /* Program ROM */ + AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_BASE(&work_ram) /* Work RAM */ + AM_RANGE(0x74000000, 0x740000ff) AM_READWRITE(K001604_reg_r, K001604_reg_w) + AM_RANGE(0x74010000, 0x74017fff) AM_RAM_WRITE(paletteram32_w) AM_BASE(&paletteram32) + AM_RANGE(0x74020000, 0x7403ffff) AM_READWRITE(K001604_tile_r, K001604_tile_w) + AM_RANGE(0x74040000, 0x7407ffff) AM_READWRITE(K001604_char_r, K001604_char_w) + AM_RANGE(0x78000000, 0x7800ffff) AM_READWRITE(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc) + AM_RANGE(0x780c0000, 0x780c0003) AM_READWRITE(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc) + AM_RANGE(0x7d000000, 0x7d00ffff) AM_READ(sysreg_r) + AM_RANGE(0x7d010000, 0x7d01ffff) AM_WRITE(sysreg_w) + AM_RANGE(0x7d020000, 0x7d021fff) AM_READWRITE(timekeeper_0_32be_r, timekeeper_0_32be_w) /* M48T58Y RTC/NVRAM */ + AM_RANGE(0x7d030000, 0x7d030007) AM_READ(K056800_host_r) + AM_RANGE(0x7d030000, 0x7d030007) AM_WRITE(K056800_host_w) + AM_RANGE(0x7d030008, 0x7d03000f) AM_WRITE(K056800_host_w) + AM_RANGE(0x7d040000, 0x7d04ffff) AM_READWRITE(lanc1_r, lanc1_w) + AM_RANGE(0x7d050000, 0x7d05ffff) AM_READWRITE(lanc2_r, lanc2_w) + AM_RANGE(0x7e000000, 0x7e7fffff) AM_ROM AM_REGION(REGION_USER2, 0) /* Data ROM */ + AM_RANGE(0x7f000000, 0x7f1fffff) AM_ROM AM_SHARE(2) + AM_RANGE(0x7fe00000, 0x7fffffff) AM_ROM AM_REGION(REGION_USER1, 0) AM_SHARE(2) /* Program ROM */ ADDRESS_MAP_END /*****************************************************************************/ @@ -906,6 +919,7 @@ static MACHINE_DRIVER_START( nwktr ) MDRV_INTERLEAVE(100) + MDRV_MACHINE_START(nwktr) MDRV_MACHINE_RESET(nwktr) MDRV_NVRAM_HANDLER( timekeeper_0 ) diff --git a/src/mame/drivers/ultrsprt.c b/src/mame/drivers/ultrsprt.c index 016cd522ee2..16afa777355 100644 --- a/src/mame/drivers/ultrsprt.c +++ b/src/mame/drivers/ultrsprt.c @@ -12,6 +12,7 @@ #include "machine/konamiic.h" static UINT32 *vram; +static UINT32 *workram; static VIDEO_UPDATE( ultrsprt ) { @@ -81,8 +82,26 @@ static WRITE32_HANDLER( int_ack_w ) cpunum_set_input_line(machine, 0, INPUT_LINE_IRQ1, CLEAR_LINE); } +static MACHINE_START( ultrsprt ) +{ + /* set conservative DRC options */ + cpunum_set_info_int(0, CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS); + + /* configure fast RAM regions for DRC */ + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_SELECT, 0); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_START, 0x00000000); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_END, 0x0007ffff); + cpunum_set_info_ptr(0, CPUINFO_PTR_PPC_FASTRAM_BASE, vram); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_READONLY, 0); + + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_SELECT, 1); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_START, 0x7f000000); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_END, 0x7f01ffff); + cpunum_set_info_ptr(0, CPUINFO_PTR_PPC_FASTRAM_BASE, workram); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_READONLY, 0); +} + static ADDRESS_MAP_START( ultrsprt_map, ADDRESS_SPACE_PROGRAM, 32 ) - ADDRESS_MAP_GLOBAL_MASK(0x7fffffff) AM_RANGE(0x00000000, 0x0007ffff) AM_RAM AM_BASE(&vram) AM_RANGE(0x70000000, 0x70000003) AM_READWRITE(eeprom_r, eeprom_w) AM_RANGE(0x70000020, 0x70000023) AM_READ(control1_r) @@ -90,7 +109,7 @@ static ADDRESS_MAP_START( ultrsprt_map, ADDRESS_SPACE_PROGRAM, 32 ) AM_RANGE(0x70000080, 0x70000087) AM_WRITE(K056800_host_w) AM_RANGE(0x70000088, 0x7000008f) AM_READ(K056800_host_r) AM_RANGE(0x700000e0, 0x700000e3) AM_WRITE(int_ack_w) - AM_RANGE(0x7f000000, 0x7f01ffff) AM_RAM + AM_RANGE(0x7f000000, 0x7f01ffff) AM_RAM AM_BASE(&workram) AM_RANGE(0x7f700000, 0x7f703fff) AM_RAM_WRITE(palette_w) AM_BASE(&paletteram32) AM_RANGE(0x7fa00000, 0x7fbfffff) AM_ROM AM_SHARE(1) AM_RANGE(0x7fc00000, 0x7fdfffff) AM_ROM AM_SHARE(1) @@ -231,6 +250,7 @@ static MACHINE_DRIVER_START( ultrsprt ) MDRV_INTERLEAVE(200) MDRV_NVRAM_HANDLER(ultrsprt) + MDRV_MACHINE_START(ultrsprt) /* video hardware */ MDRV_SCREEN_ADD("main", RASTER) diff --git a/src/mame/drivers/zr107.c b/src/mame/drivers/zr107.c index 7ccc3f30823..430072243ab 100644 --- a/src/mame/drivers/zr107.c +++ b/src/mame/drivers/zr107.c @@ -300,24 +300,38 @@ static WRITE32_HANDLER( ccu_w ) /******************************************************************/ +static UINT32 *workram; +static MACHINE_START( zr107 ) +{ + /* set conservative DRC options */ + cpunum_set_info_int(0, CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS); + + /* configure fast RAM regions for DRC */ + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_SELECT, 0); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_START, 0x00000000); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_END, 0x000fffff); + cpunum_set_info_ptr(0, CPUINFO_PTR_PPC_FASTRAM_BASE, workram); + cpunum_set_info_int(0, CPUINFO_INT_PPC_FASTRAM_READONLY, 0); +} + static ADDRESS_MAP_START( zr107_map, ADDRESS_SPACE_PROGRAM, 32 ) - AM_RANGE(0x00000000, 0x000fffff) AM_MIRROR(0x80000000) AM_RAM /* Work RAM */ - AM_RANGE(0x74000000, 0x74003fff) AM_MIRROR(0x80000000) AM_READWRITE(K056832_ram_long_r, K056832_ram_long_w) - AM_RANGE(0x74020000, 0x7402003f) AM_MIRROR(0x80000000) AM_READWRITE(K056832_long_r, K056832_long_w) - AM_RANGE(0x74060000, 0x7406003f) AM_MIRROR(0x80000000) AM_READWRITE(ccu_r, ccu_w) - AM_RANGE(0x74080000, 0x74081fff) AM_MIRROR(0x80000000) AM_RAM_WRITE(paletteram32_w) AM_BASE(&paletteram32) - AM_RANGE(0x740a0000, 0x740a3fff) AM_MIRROR(0x80000000) AM_READ(K056832_rom_long_r) - AM_RANGE(0x78000000, 0x7800ffff) AM_MIRROR(0x80000000) AM_READWRITE(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc) /* 21N 21K 23N 23K */ - AM_RANGE(0x78010000, 0x7801ffff) AM_MIRROR(0x80000000) AM_WRITE(cgboard_dsp_shared_w_ppc) - AM_RANGE(0x78040000, 0x7804000f) AM_MIRROR(0x80000000) AM_READWRITE(K001006_0_r, K001006_0_w) - AM_RANGE(0x780c0000, 0x780c0007) AM_MIRROR(0x80000000) AM_READWRITE(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc) - AM_RANGE(0x7e000000, 0x7e003fff) AM_MIRROR(0x80000000) AM_READWRITE(sysreg_r, sysreg_w) - AM_RANGE(0x7e008000, 0x7e009fff) AM_MIRROR(0x80000000) AM_READWRITE8(K056230_r, K056230_w, 0xffffffff) /* LANC registers */ - AM_RANGE(0x7e00a000, 0x7e00bfff) AM_MIRROR(0x80000000) AM_READWRITE(lanc_ram_r, lanc_ram_w) /* LANC Buffer RAM (27E) */ - AM_RANGE(0x7e00c000, 0x7e00c007) AM_MIRROR(0x80000000) AM_WRITE(K056800_host_w) - AM_RANGE(0x7e00c008, 0x7e00c00f) AM_MIRROR(0x80000000) AM_READ(K056800_host_r) - AM_RANGE(0x7f800000, 0x7f9fffff) AM_MIRROR(0x80000000) AM_ROM AM_SHARE(2) - AM_RANGE(0x7fe00000, 0x7fffffff) AM_MIRROR(0x80000000) AM_ROM AM_REGION(REGION_USER1, 0) AM_SHARE(2) /* Program ROM */ + AM_RANGE(0x00000000, 0x000fffff) AM_RAM AM_BASE(&workram) /* Work RAM */ + AM_RANGE(0x74000000, 0x74003fff) AM_READWRITE(K056832_ram_long_r, K056832_ram_long_w) + AM_RANGE(0x74020000, 0x7402003f) AM_READWRITE(K056832_long_r, K056832_long_w) + AM_RANGE(0x74060000, 0x7406003f) AM_READWRITE(ccu_r, ccu_w) + AM_RANGE(0x74080000, 0x74081fff) AM_RAM_WRITE(paletteram32_w) AM_BASE(&paletteram32) + AM_RANGE(0x740a0000, 0x740a3fff) AM_READ(K056832_rom_long_r) + AM_RANGE(0x78000000, 0x7800ffff) AM_READWRITE(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc) /* 21N 21K 23N 23K */ + AM_RANGE(0x78010000, 0x7801ffff) AM_WRITE(cgboard_dsp_shared_w_ppc) + AM_RANGE(0x78040000, 0x7804000f) AM_READWRITE(K001006_0_r, K001006_0_w) + AM_RANGE(0x780c0000, 0x780c0007) AM_READWRITE(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc) + AM_RANGE(0x7e000000, 0x7e003fff) AM_READWRITE(sysreg_r, sysreg_w) + AM_RANGE(0x7e008000, 0x7e009fff) AM_READWRITE8(K056230_r, K056230_w, 0xffffffff) /* LANC registers */ + AM_RANGE(0x7e00a000, 0x7e00bfff) AM_READWRITE(lanc_ram_r, lanc_ram_w) /* LANC Buffer RAM (27E) */ + AM_RANGE(0x7e00c000, 0x7e00c007) AM_WRITE(K056800_host_w) + AM_RANGE(0x7e00c008, 0x7e00c00f) AM_READ(K056800_host_r) + AM_RANGE(0x7f800000, 0x7f9fffff) AM_ROM AM_SHARE(2) + AM_RANGE(0x7fe00000, 0x7fffffff) AM_ROM AM_REGION(REGION_USER1, 0) AM_SHARE(2) /* Program ROM */ ADDRESS_MAP_END @@ -579,6 +593,7 @@ static MACHINE_DRIVER_START( zr107 ) MDRV_INTERLEAVE(500) MDRV_NVRAM_HANDLER(93C46) + MDRV_MACHINE_START(zr107) MDRV_MACHINE_RESET(zr107) /* video hardware */ @@ -623,6 +638,7 @@ static MACHINE_DRIVER_START( jetwave ) MDRV_INTERLEAVE(500) MDRV_NVRAM_HANDLER(93C46) + MDRV_MACHINE_START(zr107) MDRV_MACHINE_RESET(zr107) /* video hardware */ |
