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author angelosa <lordkale4@gmail.com>2025-10-31 19:36:39 +0100
committer angelosa <lordkale4@gmail.com>2025-10-31 19:36:59 +0100
commit38da243d1fb996f0cf99817dab5650731e09e881 (patch)
tree5f8ada5672a9ab1019ccd94f9a6484558f06a9f2
parent60c9a1e2937f93f29d87eb5d796b1ef869e6ed38 (diff)
cpu/m68000/mcf5206e.cpp: make it accept external interrupts, fix CPU space (misc/gamtor.cpp cares)
-rw-r--r--src/devices/cpu/m68000/mcf5206e.cpp144
-rw-r--r--src/devices/cpu/m68000/mcf5206e.h200
-rw-r--r--src/mame/misc/gamtor.cpp11
3 files changed, 203 insertions, 152 deletions
diff --git a/src/devices/cpu/m68000/mcf5206e.cpp b/src/devices/cpu/m68000/mcf5206e.cpp
index 80305b54c64..7e521b118ea 100644
--- a/src/devices/cpu/m68000/mcf5206e.cpp
+++ b/src/devices/cpu/m68000/mcf5206e.cpp
@@ -37,7 +37,7 @@
#define LOG_DRAM (1U << 7)
#define LOG_SIM (1U << 8)
#define LOG_DMA (1U << 9)
-#define VERBOSE ( LOG_DEBUG | LOG_UART | LOG_SWDT | LOG_MBUS | LOG_DRAM | LOG_SIM | LOG_DMA )
+#define VERBOSE ( LOG_DEBUG | LOG_UART | LOG_SWDT | LOG_MBUS | LOG_DRAM | LOG_SIM | LOG_DMA | LOG_TIMER )
#include "logmacro.h"
#define INT_LEVEL(N) ((N&0x1c) >> 2)
@@ -220,8 +220,9 @@ void mcf5206e_device::coldfire_register_map(address_map &map)
map(0xf0000240, 0xf000025f).m(m_dma[1], FUNC(coldfire_dma_device::dma_map));
}
-void mcf5206e_device::coldfire_vector_map(address_map &map){
- map(0xfffffe0, 0xffffffc).r(m_sim, FUNC(coldfire_sim_device::interrupt_callback));
+void mcf5206e_device::coldfire_vector_map(address_map &map)
+{
+ map(0xfffffe0, 0xfffffff).r(m_sim, FUNC(coldfire_sim_device::interrupt_callback));
}
/*
@@ -343,7 +344,8 @@ void mcf5206e_device::ppddr_w(u8 data)
{
LOGMASKED(LOG_DEBUG, "%s: (Port A Data Direction Register) PPDDR_w %02x\n", this->machine().describe_context(), data);
- if(m_ppddr != data){
+ if(m_ppddr != data)
+ {
// Updating the register updates the pins immediately
u8 mask = 0;
if(!BIT(m_sim->get_par(), 4)) mask |= 0x0f; // PP 0-3 / DDATA 0-3
@@ -414,7 +416,6 @@ void coldfire_sim_device::device_reset()
m_simr = 0xc0;
m_marb = 0x00;
- m_ipr = 0x3ffe;
m_sypcr = 0x00;
m_swivr = 0x0f;
m_imr = 0x3ffe;
@@ -462,13 +463,15 @@ void coldfire_sim_device::sim_map(address_map &map)
}
// MBAR + 0x003: SIM Configuration Register - Not really applicable to MAME as there's no BDM port currently but hey.
-void coldfire_sim_device::simr_w(u8 data){
+void coldfire_sim_device::simr_w(u8 data)
+{
LOGMASKED(LOG_DEBUG, "%s: SIMR_w %02x\n", this->machine().describe_context(), data);
m_simr = data;
}
// MBAR + 0x003: Bus Master Arbitration Control
-void coldfire_sim_device::marb_w(u8 data){
+void coldfire_sim_device::marb_w(u8 data)
+{
LOGMASKED(LOG_DEBUG, "%s: (Bus Master Arbitration Control) MARB_w %02x\n", this->machine().describe_context(), data);
m_marb = data;
}
@@ -476,7 +479,8 @@ void coldfire_sim_device::marb_w(u8 data){
// MBAR + 0x014 -> 0x022: Interupt Control Registers
u8 coldfire_sim_device::icr_r(offs_t offset)
{
- if(offset > 15){
+ if(offset > 15)
+ {
logerror("%s: Request to read invalid ICR offset received: %d\n", this->machine().describe_context(), offset);
return 0;
}
@@ -551,29 +555,46 @@ void coldfire_sim_device::set_external_interrupt(int level, int state)
}
}
+void mcf5206e_device::execute_set_input(int inputnum, int state)
+{
+ m68000_musashi_device::execute_set_input(inputnum, state);
+ // HACK: make it accept external interrupts
+ if (inputnum == 1 || inputnum == 4 || inputnum == 7)
+ m_sim->set_ipr(inputnum, state);
+
+ if (BIT(m_sim->get_par(), 6))
+ popmessage("mcf5206e: encoded interrupt priority!");
+}
+
// Return the vector for the highest priority and level interrupt
u8 coldfire_sim_device::interrupt_callback(offs_t level)
{
u8 ipl = (level >> 1) & 7; // Should be 2 for coldFire, really
+
u8 highest_priority_icr = 0;
u8 highest_priority_device = 0;
- if(!this->machine().side_effects_disabled()) {
+ if(!this->machine().side_effects_disabled())
+ {
//logerror("%s: interrupt_callback(%u), ipl: %x, m_ipr: %x, m_imr: %x\n", this->machine().describe_context(), level, ipl, m_ipr, m_imr);
m_maincpu->set_input_line(ipl, CLEAR_LINE);
}
- for (int i = 0; i < 15; i++) {
+ for (int i = 0; i < 15; i++)
+ {
//if(!this->machine().side_effects_disabled()) logerror("i: %x, m_icr: %x, ipl: %x, ipr_bit: %x\n", i, INT_LEVEL(m_icr[i]), ipl, BIT(m_ipr, 1 + i));
- if (BIT(m_ipr, 1 +i) && (INT_LEVEL(m_icr[i]) == ipl)) {
- if (highest_priority_device == 0 || INT_PRIORITY(m_icr[i]) > INT_PRIORITY(highest_priority_icr)) {
+ if (BIT(m_ipr, 1 + i) && (INT_LEVEL(m_icr[i]) == ipl))
+ {
+ if (highest_priority_device == 0 || INT_PRIORITY(m_icr[i]) > INT_PRIORITY(highest_priority_icr))
+ {
highest_priority_icr = m_icr[i];
highest_priority_device = i + 1;
}
}
}
- if (highest_priority_device == 0) {
+ if (highest_priority_device == 0)
+ {
if(!this->machine().side_effects_disabled()) logerror("%s: Spurious interrupt detected: %u\n", this->machine().describe_context(), ipl);
return EXCEPTION_SPURIOUS_INTERRUPT;
}
@@ -583,11 +604,15 @@ u8 coldfire_sim_device::interrupt_callback(offs_t level)
u8 vector = 0xff;
// Check if ICR specifies to use autovectoring
- if (BIT(highest_priority_icr, 7)) {
+ if (BIT(highest_priority_icr, 7))
+ {
vector = m68000_base_device::autovector(ipl);
- } else {
+ }
+ else
+ {
// Determine the correct vector to return
- switch (highest_priority_device) {
+ switch (highest_priority_device)
+ {
case EXTERNAL_IPL_1:
case EXTERNAL_IPL_2:
case EXTERNAL_IPL_3:
@@ -595,27 +620,34 @@ u8 coldfire_sim_device::interrupt_callback(offs_t level)
case EXTERNAL_IPL_5:
case EXTERNAL_IPL_6:
case EXTERNAL_IPL_7:
- if (!BIT(highest_priority_icr, 7)) vector = irq_vector_cb();
+ if (!BIT(highest_priority_icr, 7))
+ vector = irq_vector_cb();
break;
case WATCHDOG_IRQ:
- if (!BIT(highest_priority_icr, 7)) vector = m_swivr;
+ if (!BIT(highest_priority_icr, 7))
+ vector = m_swivr;
break;
case UART_1_IRQ:
- if (!BIT(highest_priority_icr, 7)) vector = m_maincpu->m_uart[0]->get_irq_vector();
+ if (!BIT(highest_priority_icr, 7))
+ vector = m_maincpu->m_uart[0]->get_irq_vector();
break;
case UART_2_IRQ:
- if (!BIT(highest_priority_icr, 7)) vector = m_maincpu->m_uart[1]->get_irq_vector();
+ if (!BIT(highest_priority_icr, 7))
+ vector = m_maincpu->m_uart[1]->get_irq_vector();
break;
case DMA_0_IRQ:
- if (!BIT(highest_priority_icr, 7)) vector = m_maincpu->m_dma[0]->get_irq_vector();
+ if (!BIT(highest_priority_icr, 7))
+ vector = m_maincpu->m_dma[0]->get_irq_vector();
//m_maincpu->m_dma[0]->dma_int_callback();
break;
case DMA_1_IRQ:
- if (!BIT(highest_priority_icr, 7)) vector = m_maincpu->m_dma[1]->get_irq_vector();
+ if (!BIT(highest_priority_icr, 7))
+ vector = m_maincpu->m_dma[1]->get_irq_vector();
//m_maincpu->m_dma[1]->dma_int_callback();
break;
default:
- if(!this->machine().side_effects_disabled()) logerror("%s: Vector required for device that only supports autovectoring: %u, %u\n",
+ if(!this->machine().side_effects_disabled())
+ logerror("%s: Vector required for device that only supports autovectoring: %u, %u\n",
this->machine().describe_context(), ipl, highest_priority_device);
vector = EXCEPTION_UNINITIALIZED_INTERRUPT;
break;
@@ -631,11 +663,16 @@ void coldfire_sim_device::set_interrupt(int interrupt, int state)
//LOGMASKED(LOG_DEBUG, "%s: set_interrupt(%u, %u): %x, %d, %d\n", this->machine().describe_context(), interrupt, state, m_ipr, BIT(m_imr, interrupt), m_imr & interrupt);
+ //printf("%d %d -> %04x %04x\n", interrupt, state, m_imr, m_ipr);
+
// IMR enables interrupts when bit is 0
- if(state != CLEAR_LINE){
- if(!BIT(m_imr, interrupt)){
+ if(state != CLEAR_LINE)
+ {
+ if(!BIT(m_imr, interrupt))
+ {
u8 icr = 0;
- switch (interrupt){
+ switch (interrupt)
+ {
case EXTERNAL_IPL_1: icr = m_icr[ICR1]; break;
case EXTERNAL_IPL_2: icr = m_icr[ICR2]; break;
case EXTERNAL_IPL_3: icr = m_icr[ICR3]; break;
@@ -673,7 +710,8 @@ void coldfire_sim_device::rsr_w(u8 data)
// MBAR + 0x041
void coldfire_sim_device::sypcr_w(u8 data)
{
- if(!m_sypcr_locked){
+ if(!m_sypcr_locked)
+ {
// SYPCR is a write-once register, whatever is written first remains until system reset.
LOGMASKED(LOG_SWDT, "%s: (System Protection Control) SYPCR_w %02x\n", this->machine().describe_context(), data);
m_sypcr_locked = true;
@@ -681,12 +719,17 @@ void coldfire_sim_device::sypcr_w(u8 data)
// Bus monitoring is not supported (nor will it be?)
- if(BIT(m_sypcr, 6)){
+ if(BIT(m_sypcr, 6))
+ {
m_swdt->watchdog_enable(BIT(data, 7));
- } else {
- // Set timer for interrupt
}
- } else {
+ else
+ {
+ // TODO: Set timer for interrupt
+ }
+ }
+ else
+ {
LOG("%s: Write to SYPCR_w (%02x) when PCR is locked\n", this->machine().describe_context(), data);
}
}
@@ -702,8 +745,10 @@ void coldfire_sim_device::swivr_w(u8 data)
void coldfire_sim_device::swsr_w(u8 data)
{
LOGMASKED(LOG_SWDT, "%s: (Software Watchdog Service Routine) SWIVR_r %02x\n", this->machine().describe_context(), data);
- if(data == swdt_reset_sequence[m_swdt_w_count]) m_swdt_w_count++;
- if(m_swdt_w_count == 2) {
+ if(data == swdt_reset_sequence[m_swdt_w_count])
+ m_swdt_w_count++;
+ if(m_swdt_w_count == 2)
+ {
m_swdt->watchdog_reset();
m_swdt_w_count = 0;
}
@@ -719,8 +764,8 @@ TIMER_CALLBACK_MEMBER(coldfire_sim_device::swdt_callback)
* Timer Module/s
* Creates an MCF5206e compatible 16-bit timer
*/
-coldfire_timer_device::coldfire_timer_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
- device_t(mconfig, COLDFIRE_TIMER, tag, owner, clock)
+coldfire_timer_device::coldfire_timer_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
+ : device_t(mconfig, COLDFIRE_TIMER, tag, owner, clock)
, write_irq(*this)
{
}
@@ -746,7 +791,8 @@ void coldfire_timer_device::device_start()
save_item(NAME(m_timer_start_time));
}
-void coldfire_timer_device::device_reset(){
+void coldfire_timer_device::device_reset()
+{
m_tmr = 0x0000;
m_trr = 0xffff;
m_tcn = 0x0000;
@@ -759,19 +805,24 @@ void coldfire_timer_device::device_reset(){
TIMER_CALLBACK_MEMBER(coldfire_timer_device::timer_callback)
{
- if(m_tmr & T_FRR){
+ if(m_tmr & T_FRR)
+ {
// FRR resets counter to 0
m_tcn = 0;
}
m_ter |= T_EREF;
- write_irq(ASSERT_LINE);
+
+ // TODO: capture edge irq modes
+ if(BIT(m_tmr, 4))
+ write_irq(ASSERT_LINE);
}
void coldfire_timer_device::tmr_w(u16 data)
{
u16 cmd = data;
- if((m_tmr & T_RST) && !(cmd & T_RST)){
+ if((m_tmr & T_RST) && !(cmd & T_RST))
+ {
// T_RST high to low resets the entire timer
device_reset();
return;
@@ -779,8 +830,9 @@ void coldfire_timer_device::tmr_w(u16 data)
m_tmr = cmd;
- if (m_tmr & T_RST){
- // todo: add tin pin support
+ if(m_tmr & T_RST)
+ {
+ // TODO: add tin pin support
int div, start, interval;
start = (m_trr - m_tcn);
div = ((m_tmr & 0xff00) >> 8) + 1; // 1 -> 256 division scale
@@ -867,8 +919,8 @@ void mcf5206e_device::init_regs(bool first_init)
* Hosts I2C and Motorola extensions to the format. Can act as a device or host.
*/
-coldfire_mbus_device::coldfire_mbus_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
- device_t(mconfig, COLDFIRE_MBUS, tag, owner, clock)
+coldfire_mbus_device::coldfire_mbus_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
+ : device_t(mconfig, COLDFIRE_MBUS, tag, owner, clock)
, write_sda(*this)
, write_scl(*this)
, write_irq(*this)
@@ -922,7 +974,7 @@ void coldfire_mbus_device::mbus_map(address_map &map)
TIMER_CALLBACK_MEMBER(coldfire_mbus_device::mbus_callback)
{
- // Do bit transfers etc
+ // TODO: Do bit transfers etc
}
void coldfire_mbus_device::madr_w(u8 data)
@@ -978,8 +1030,8 @@ void coldfire_mbus_device::mbdr_w(u8 data)
*
*/
-coldfire_dma_device::coldfire_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
- device_t(mconfig, COLDFIRE_DMA, tag, owner, clock)
+coldfire_dma_device::coldfire_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
+ : device_t(mconfig, COLDFIRE_DMA, tag, owner, clock)
, write_irq(*this)
{
}
diff --git a/src/devices/cpu/m68000/mcf5206e.h b/src/devices/cpu/m68000/mcf5206e.h
index eb07d0e4511..6dfb558f040 100644
--- a/src/devices/cpu/m68000/mcf5206e.h
+++ b/src/devices/cpu/m68000/mcf5206e.h
@@ -34,105 +34,112 @@ class mcf5206e_device; // Forward declaration
class coldfire_sim_device : public device_t
{
- friend class mcf5206e_device;
+friend class mcf5206e_device;
- public:
- enum {
- ICR1 = 0, // Bit 1
- ICR2, // Bit 2
- ICR3, // Bit 3
- ICR4, // Bit 4
- ICR5, // Bit 5
- ICR6, // Bit 6
- ICR7, // Bit 7
- ICR_SWDT, // Bit 8
- ICR_TMR1, // Bit 9
- ICR_TMR2, // Bit 10
- ICR_MBUS, // Bit 11
- ICR_UART1, // Bit 12
- ICR_UART2, // Bit 13
- ICR_DMA0, // Bit 14
- ICR_DMA1, // Bit 15
- MAX_ICR
- };
-
- template <typename T>
- coldfire_sim_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock, T &&cpu_tag)
- : coldfire_sim_device(mconfig, tag, owner, clock)
- {
- m_maincpu.set_tag(std::forward<T>(cpu_tag));
- }
-
- coldfire_sim_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
-
- void sim_map(address_map &map);
-
- u8 interrupt_callback(offs_t int_level);
-
- void write_irq_1(int state) { set_external_interrupt(1, state); }
- void write_irq_4(int state) { set_external_interrupt(4, state); }
- void write_irq_7(int state) { set_external_interrupt(7, state); }
-
- void set_external_interrupt_level(int level){ set_external_interrupt(level, HOLD_LINE); };
- void set_external_interrupt(int level, int state);
- void set_internal_interrupt_request(int device, int state){ set_interrupt(device, state); }
-
- u16 get_par(){ return m_par; }
+public:
+ enum {
+ ICR1 = 0, // Bit 1
+ ICR2, // Bit 2
+ ICR3, // Bit 3
+ ICR4, // Bit 4
+ ICR5, // Bit 5
+ ICR6, // Bit 6
+ ICR7, // Bit 7
+ ICR_SWDT, // Bit 8
+ ICR_TMR1, // Bit 9
+ ICR_TMR2, // Bit 10
+ ICR_MBUS, // Bit 11
+ ICR_UART1, // Bit 12
+ ICR_UART2, // Bit 13
+ ICR_DMA0, // Bit 14
+ ICR_DMA1, // Bit 15
+ MAX_ICR
+ };
+
+ template <typename T>
+ coldfire_sim_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock, T &&cpu_tag)
+ : coldfire_sim_device(mconfig, tag, owner, clock)
+ {
+ m_maincpu.set_tag(std::forward<T>(cpu_tag));
+ }
+
+ coldfire_sim_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+ void sim_map(address_map &map);
+
+ u8 interrupt_callback(offs_t int_level);
+
+ void write_irq_1(int state) { set_external_interrupt(1, state); }
+ void write_irq_4(int state) { set_external_interrupt(4, state); }
+ void write_irq_7(int state) { set_external_interrupt(7, state); }
+
+ void set_external_interrupt_level(int level){ set_external_interrupt(level, HOLD_LINE); };
+ void set_external_interrupt(int level, int state);
+ void set_internal_interrupt_request(int device, int state){ set_interrupt(device, state); }
+
+ void set_ipr(u16 inputnum, int state)
+ {
+ if (!state)
+ m_ipr &= ~(1 << inputnum);
+ else
+ m_ipr |= (1 << inputnum);
+ }
+ u16 get_par(){ return m_par; }
- protected:
- void device_start() override ATTR_COLD;
- void device_reset() override ATTR_COLD;
- void device_add_mconfig(machine_config &config) override ATTR_COLD;
+protected:
+ void device_start() override ATTR_COLD;
+ void device_reset() override ATTR_COLD;
+ void device_add_mconfig(machine_config &config) override ATTR_COLD;
- private:
- void set_interrupt(int interrupt, int state);
-
- TIMER_CALLBACK_MEMBER(swdt_callback);
-
- void icr_info(u8 icr);
-
- devcb_read8 irq_vector_cb;
-
- u8 simr_r(){ return m_simr; } // sim configuration register
- u8 marb_r(){ return m_marb; } // bus master arbitration control
- u8 icr_r(offs_t offset); // interrupt control register
- u16 imr_r(){ return m_imr; } // interrupt mask register
- u16 ipr_r(){ return m_ipr; } // interrupt pending register
- u8 sypcr_r(){ return m_sypcr; } // system protection control register
- u8 swivr_r(){ return m_swivr; } // software watchdog interrupt vector register
- u8 rsr_r(){ return m_rsr; } // reset status register
- u16 par_r(){ return m_par; } // pin assignment register
-
- void simr_w(u8 data);
- void marb_w(u8 data);
- void icr_w(offs_t offset, u8 data);
- void imr_w(u16 data);
- void sypcr_w(u8 data);
- void swivr_w(u8 data);
- void swsr_w(u8 data); // software watchdog service routine (kick)
- void rsr_w(u8 data);
- void par_w(u16 data);
-
- const u8 swdt_reset_sequence[2] = { 0x55, 0xaa };
- u8 m_swdt_w_count;
- bool m_sypcr_locked;
-
- u8 m_simr;
- u8 m_marb;
- u8 m_icr[15];
- u16 m_par;
- u16 m_imr;
- u16 m_ipr;
- u8 m_sypcr;
- u8 m_swivr;
- u8 m_rsr;
-
- u8 m_external_ipl;
-
- emu_timer *m_timer_swdt;
-
- required_device<mcf5206e_device> m_maincpu;
- required_device<watchdog_timer_device> m_swdt;
+private:
+ void set_interrupt(int interrupt, int state);
+
+ TIMER_CALLBACK_MEMBER(swdt_callback);
+
+ void icr_info(u8 icr);
+
+ devcb_read8 irq_vector_cb;
+
+ u8 simr_r(){ return m_simr; } // sim configuration register
+ u8 marb_r(){ return m_marb; } // bus master arbitration control
+ u8 icr_r(offs_t offset); // interrupt control register
+ u16 imr_r(){ return m_imr; } // interrupt mask register
+ u16 ipr_r(){ return m_ipr; } // interrupt pending register
+ u8 sypcr_r(){ return m_sypcr; } // system protection control register
+ u8 swivr_r(){ return m_swivr; } // software watchdog interrupt vector register
+ u8 rsr_r(){ return m_rsr; } // reset status register
+ u16 par_r(){ return m_par; } // pin assignment register
+
+ void simr_w(u8 data);
+ void marb_w(u8 data);
+ void icr_w(offs_t offset, u8 data);
+ void imr_w(u16 data);
+ void sypcr_w(u8 data);
+ void swivr_w(u8 data);
+ void swsr_w(u8 data); // software watchdog service routine (kick)
+ void rsr_w(u8 data);
+ void par_w(u16 data);
+
+ const u8 swdt_reset_sequence[2] = { 0x55, 0xaa };
+ u8 m_swdt_w_count;
+ bool m_sypcr_locked;
+
+ u8 m_simr;
+ u8 m_marb;
+ u8 m_icr[15];
+ u16 m_par;
+ u16 m_imr;
+ u16 m_ipr;
+ u8 m_sypcr;
+ u8 m_swivr;
+ u8 m_rsr;
+
+ u8 m_external_ipl;
+
+ emu_timer *m_timer_swdt;
+
+ required_device<mcf5206e_device> m_maincpu;
+ required_device<watchdog_timer_device> m_swdt;
};
@@ -357,6 +364,7 @@ protected:
virtual void device_reset() override;
//virtual void device_clock_changed() override { }
virtual void device_add_mconfig(machine_config &config) override;
+ void execute_set_input(int inputnum, int state) override;
virtual space_config_vector memory_space_config() const override;
address_space_config m_coldfire_register_map;
diff --git a/src/mame/misc/gamtor.cpp b/src/mame/misc/gamtor.cpp
index 1745d6b49b6..0a6ec3613da 100644
--- a/src/mame/misc/gamtor.cpp
+++ b/src/mame/misc/gamtor.cpp
@@ -16,19 +16,13 @@
and dies during what it calls 'EEPROM test' (investigate - is it hooked up in the coldfire
peripheral area?)
- llcharm ->
- 'maincpu' (014902D2): unmapped program memory write to 000000D8 = 00000000 & FFFFFFFF
- 'maincpu' (01490312): unmapped program memory write to 000000B8 = 0BB19C00 & FFFFFFFF
- 'maincpu' (0149031C): unmapped program memory write to 000000D8 = 00000001 & FFFFFFFF
- 'maincpu' (01490312): unmapped program memory write to 000000B8 = 038B9C00 & FFFFFFFF
- 'maincpu' (0149031C): unmapped program memory write to 000000D8 = 00000001 & FFFFFFFF
+ Update: calls MBUS in Coldfire (i2c), which currently is tied to machine().rand() ...
*/
#include "emu.h"
#include "cpu/m68000/mcf5206e.h"
-#include "machine/mcf5206e.h"
#include "video/pc_vga.h"
#include "speaker.h"
@@ -156,7 +150,6 @@ void gaminator_state::gaminator_map(address_map &map)
map(0x440a0000, 0x440bffff).rw("vga", FUNC(gamtor_vga_device::mem_r), FUNC(gamtor_vga_device::mem_w));
map(0xe0000000, 0xe00001ff).ram(); // nvram?
- map(0xf0000000, 0xf00003ff).rw("maincpu_onboard", FUNC(mcf5206e_peripheral_device::dev_r), FUNC(mcf5206e_peripheral_device::dev_w)); // technically this can be moved with MBAR
}
static INPUT_PORTS_START( gaminator )
@@ -168,8 +161,6 @@ void gaminator_state::gaminator(machine_config &config)
{
MCF5206E(config, m_maincpu, 40000000); /* definitely Coldfire, model / clock uncertain */
m_maincpu->set_addrmap(AS_PROGRAM, &gaminator_state::gaminator_map);
- m_maincpu->set_vblank_int("screen", FUNC(gaminator_state::irq6_line_hold)); // irq6 seems to be needed to get past the ROM checking
- MCF5206E_PERIPHERAL(config, "maincpu_onboard", 0, m_maincpu);
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
screen.set_raw(XTAL(25'174'800),900,0,640,526,0,480);