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author Aaron Giles <aaron@aarongiles.com>2020-04-28 12:17:21 -0700
committer couriersud <couriersud@gmx.org>2020-04-29 12:21:31 +0200
commit302223432b26910a577b5124ffefe9b1f48be3b2 (patch)
treee95d88f9e6a3081a4aee3e84934f4508a7dbecad
parent85454208d5b3837c373a70925d0b6dbd6aa6a215 (diff)
Some initial changes.
-rw-r--r--src/lib/netlist/macro/nlm_opamp.cpp7
-rw-r--r--src/lib/netlist/macro/nlm_opamp.h3
-rw-r--r--src/lib/netlist/macro/nlm_ttl74xx.cpp40
-rw-r--r--src/lib/netlist/macro/nlm_ttl74xx.h8
4 files changed, 58 insertions, 0 deletions
diff --git a/src/lib/netlist/macro/nlm_opamp.cpp b/src/lib/netlist/macro/nlm_opamp.cpp
index fc6ee3b94fe..f50beed9071 100644
--- a/src/lib/netlist/macro/nlm_opamp.cpp
+++ b/src/lib/netlist/macro/nlm_opamp.cpp
@@ -134,6 +134,13 @@ static NETLIST_START(MB3614_DIP)
NETLIST_END()
+static NETLIST_START(TL081_DIP)
+ OPAMP(A, "TL084")
+
+ INCLUDE(opamp_layout_1_7_4)
+
+NETLIST_END()
+
static NETLIST_START(TL084_DIP)
OPAMP(A, "TL084")
OPAMP(B, "TL084")
diff --git a/src/lib/netlist/macro/nlm_opamp.h b/src/lib/netlist/macro/nlm_opamp.h
index c0a1486aa2f..91eb206b9de 100644
--- a/src/lib/netlist/macro/nlm_opamp.h
+++ b/src/lib/netlist/macro/nlm_opamp.h
@@ -24,6 +24,9 @@
#define LM324_DIP(name) \
NET_REGISTER_DEV(LM324_DIP, name)
+#define TL081_DIP(name) \
+ NET_REGISTER_DEV(TL081_DIP, name)
+
#define TL084_DIP(name) \
NET_REGISTER_DEV(TL084_DIP, name)
diff --git a/src/lib/netlist/macro/nlm_ttl74xx.cpp b/src/lib/netlist/macro/nlm_ttl74xx.cpp
index e96c32f66cf..6fac72d5c92 100644
--- a/src/lib/netlist/macro/nlm_ttl74xx.cpp
+++ b/src/lib/netlist/macro/nlm_ttl74xx.cpp
@@ -122,6 +122,37 @@ static NETLIST_START(TTL_7404_DIP)
NETLIST_END()
/*
+ * DM7406: Hex Inverting Buffers with
+ * High Voltage Open-Collector Outputs
+ *
+ * Naming conventions follow Fairchild Semiconductor datasheet
+ *
+ */
+
+static NETLIST_START(TTL_7406_DIP)
+ TTL_7406_GATE(A)
+ TTL_7406_GATE(B)
+ TTL_7406_GATE(C)
+ TTL_7406_GATE(D)
+ TTL_7406_GATE(E)
+ TTL_7406_GATE(F)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
+
+ DIPPINS( /* +--------------+ */
+ A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
+ A.Y, /* Y1 |2 13| A6 */ F.A,
+ B.A, /* A2 |3 12| Y6 */ F.Y,
+ B.Y, /* Y2 |4 7406 11| A5 */ E.A,
+ C.A, /* A3 |5 10| Y5 */ E.Y,
+ C.Y, /* Y3 |6 9| A4 */ D.A,
+ A.GND,/* GND |7 8| Y4 */ D.Y
+ /* +--------------+ */
+ )
+NETLIST_END()
+
+/*
* DM7408: Quad 2-Input AND Gates
*
*
@@ -946,6 +977,14 @@ NETLIST_START(TTL74XX_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
+ TRUTHTABLE_START(TTL_7406_GATE, 1, 1, "")
+ TT_HEAD("A|Y ")
+ TT_LINE("0|1|15")
+ TT_LINE("1|0|23")
+ /* Open Collector */
+ TT_FAMILY("74XXOC")
+ TRUTHTABLE_END()
+
TRUTHTABLE_START(TTL_7408_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|0|15")
@@ -1370,6 +1409,7 @@ NETLIST_START(TTL74XX_lib)
LOCAL_LIB_ENTRY(TTL_7400_DIP)
LOCAL_LIB_ENTRY(TTL_7402_DIP)
LOCAL_LIB_ENTRY(TTL_7404_DIP)
+ LOCAL_LIB_ENTRY(TTL_7406_DIP)
LOCAL_LIB_ENTRY(TTL_7408_DIP)
LOCAL_LIB_ENTRY(TTL_7410_DIP)
LOCAL_LIB_ENTRY(TTL_7411_DIP)
diff --git a/src/lib/netlist/macro/nlm_ttl74xx.h b/src/lib/netlist/macro/nlm_ttl74xx.h
index 544445c83e6..ac1a6a60240 100644
--- a/src/lib/netlist/macro/nlm_ttl74xx.h
+++ b/src/lib/netlist/macro/nlm_ttl74xx.h
@@ -57,6 +57,14 @@
#define TTL_7404_DIP(name) \
NET_REGISTER_DEV(TTL_7404_DIP, name)
+
+#define TTL_7406_GATE(name) \
+ NET_REGISTER_DEV(TTL_7406_GATE, name)
+
+#define TTL_7406_DIP(name) \
+ NET_REGISTER_DEV(TTL_7406_DIP, name)
+
+
#define TTL_7408_GATE(name) \
NET_REGISTER_DEV(TTL_7408_GATE, name)