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Diffstat (limited to 'src/devices/cpu/m68hc16/cpu16dasm.cpp')
-rw-r--r--src/devices/cpu/m68hc16/cpu16dasm.cpp14
1 files changed, 9 insertions, 5 deletions
diff --git a/src/devices/cpu/m68hc16/cpu16dasm.cpp b/src/devices/cpu/m68hc16/cpu16dasm.cpp
index 7523afcbc5e..3d646639058 100644
--- a/src/devices/cpu/m68hc16/cpu16dasm.cpp
+++ b/src/devices/cpu/m68hc16/cpu16dasm.cpp
@@ -9,6 +9,10 @@
the 8-bit direct mode no longer exists. The use of PC+6 as the base
for relative jump destinations is an artifact of pipelining.
+ For whatever reason, Motorola's assembler chose to retain LSL, LSLA,
+ LSLB, etc. as mnemonic aliases for ASL, ASLA, ASLB and so on, but
+ eliminated BHS and BLO as alternate mnemonics for BCC and BCS.
+
***************************************************************************/
#include "emu.h"
@@ -361,8 +365,8 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] =
{ "clr", cpu16_disassembler::mode::IND, 0 },
{ "tst", cpu16_disassembler::mode::IND, 0 },
{ "", cpu16_disassembler::mode::UND, 0 },
- { "bclr", cpu16_disassembler::mode::IND, 0 },
- { "bset", cpu16_disassembler::mode::IND, 0 },
+ { "bclr", cpu16_disassembler::mode::BIT, 0 },
+ { "bset", cpu16_disassembler::mode::BIT, 0 },
{ "", cpu16_disassembler::mode::UND, 0 },
{ "", cpu16_disassembler::mode::UND, 0 },
{ "rol", cpu16_disassembler::mode::IND, 0 },
@@ -804,10 +808,10 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] =
{ "", cpu16_disassembler::mode::UND, 0 },
// 27BX
- { "ldhi", cpu16_disassembler::mode::EXT, 0 },
+ { "ldhi", cpu16_disassembler::mode::INH, 0 },
{ "tedm", cpu16_disassembler::mode::INH, 0 },
{ "tem", cpu16_disassembler::mode::INH, 0 },
- { "tmexd", cpu16_disassembler::mode::INH, 0 },
+ { "tmxed", cpu16_disassembler::mode::INH, 0 },
{ "tmer", cpu16_disassembler::mode::INH, 0 },
{ "tmet", cpu16_disassembler::mode::INH, 0 },
{ "aslm", cpu16_disassembler::mode::INH, 0 },
@@ -951,7 +955,7 @@ const cpu16_disassembler::opcode_info cpu16_disassembler::s_opinfo[4][256] =
// 373X
{ "sube", cpu16_disassembler::mode::IMM, 0 },
{ "adde", cpu16_disassembler::mode::IMM, 0 },
- { "sbcd", cpu16_disassembler::mode::IMM, 0 },
+ { "sbce", cpu16_disassembler::mode::IMM, 0 },
{ "adce", cpu16_disassembler::mode::IMM, 0 },
{ "eore", cpu16_disassembler::mode::IMM, 0 },
{ "lde", cpu16_disassembler::mode::IMM, 0 },