diff options
author | 2021-01-06 20:53:12 +0700 | |
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committer | 2021-01-06 20:53:12 +0700 | |
commit | bb7ca8d920114a558127bd125e6ac00a1de4135d (patch) | |
tree | bc60832dd422c3c05b85a8e3a6644347206154fb /src | |
parent | 805d1a815bb32b2ee5106d47e4976c803621c49b (diff) |
fix several genuine issues found by coverity
Diffstat (limited to 'src')
-rw-r--r-- | src/devices/bus/interpro/sr/gt.cpp | 4 | ||||
-rw-r--r-- | src/devices/bus/nscsi/cd.cpp | 2 | ||||
-rw-r--r-- | src/devices/cpu/mips/r4000.cpp | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/devices/bus/interpro/sr/gt.cpp b/src/devices/bus/interpro/sr/gt.cpp index 768bf221ec5..4d7318eea19 100644 --- a/src/devices/bus/interpro/sr/gt.cpp +++ b/src/devices/bus/interpro/sr/gt.cpp @@ -687,7 +687,7 @@ void gt_device_base::ri_xfer_w(offs_t offset, u32 data, u32 mem_mask) // initiate ri line draw u32 address = m_ri_initial_address; - u32 error = m_ri_initial_error; + s32 error = m_ri_initial_error; for (int i = 0; i < m_ri_stop_count; i++) { @@ -1571,7 +1571,7 @@ u32 gtdb_device::vram_r(offs_t offset, const bool linear) const return gt_device_base::vram_r(offset, linear); } -void gtdb_device::vram_w(const offs_t offset, const u32 data, const u32 mem_mask, const bool linear) const +void gtdb_device::vram_w(const offs_t offset, const u32 data, u32 mem_mask, const bool linear) const { if (m_control & GFX_HILITE_SEL) { diff --git a/src/devices/bus/nscsi/cd.cpp b/src/devices/bus/nscsi/cd.cpp index 4d81d3dc9a2..0271efbf082 100644 --- a/src/devices/bus/nscsi/cd.cpp +++ b/src/devices/bus/nscsi/cd.cpp @@ -460,7 +460,7 @@ void nscsi_cdrom_device::scsi_command() "Session info", "Full TOC", "PMA", - "ATIP" + "ATIP", "Reserved 5", "Reserved 6", "Reserved 7", diff --git a/src/devices/cpu/mips/r4000.cpp b/src/devices/cpu/mips/r4000.cpp index f3bb66b28c0..802ab7d04f4 100644 --- a/src/devices/cpu/mips/r4000.cpp +++ b/src/devices/cpu/mips/r4000.cpp @@ -3043,11 +3043,11 @@ void r4000_base_device::cp1_execute(u32 const op) // TODO: MIPS3 only switch (op & 0x3f) { - case 0x02a00020: // CVT.S.L + case 0x20: // CVT.S.L if ((SR & SR_FR) || !(op & ODD_REGS)) cp1_set(FDREG, i64_to_f32(s64(m_f[FSREG])).v); break; - case 0x02a00021: // CVT.D.L + case 0x21: // CVT.D.L if ((SR & SR_FR) || !(op & ODD_REGS)) cp1_set(FDREG, i64_to_f64(s64(m_f[FSREG])).v); break; |