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author Miodrag Milanovic <mmicko@gmail.com>2016-10-22 13:13:17 +0200
committer Miodrag Milanovic <mmicko@gmail.com>2016-10-22 13:13:17 +0200
commitddb290d5f615019c33c42b8d94e5a5254cabcf33 (patch)
treea70f688b0df3acd19da7b1151e5902e3c6af3fa5 /src/mame/drivers/xtom3d.cpp
parent333bff8de64dfaeb98134000412796b4fdef970b (diff)
NOTICE (TYPE NAME CONSOLIDATION)
Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8 also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
Diffstat (limited to 'src/mame/drivers/xtom3d.cpp')
-rw-r--r--src/mame/drivers/xtom3d.cpp52
1 files changed, 26 insertions, 26 deletions
diff --git a/src/mame/drivers/xtom3d.cpp b/src/mame/drivers/xtom3d.cpp
index c017d160442..5e725ea928f 100644
--- a/src/mame/drivers/xtom3d.cpp
+++ b/src/mame/drivers/xtom3d.cpp
@@ -56,15 +56,15 @@ public:
: pcat_base_state(mconfig, type, tag)
{ }
- std::unique_ptr<UINT32[]> m_bios_ram;
- std::unique_ptr<UINT32[]> m_bios_ext1_ram;
- std::unique_ptr<UINT32[]> m_bios_ext2_ram;
- std::unique_ptr<UINT32[]> m_bios_ext3_ram;
- std::unique_ptr<UINT32[]> m_bios_ext4_ram;
- std::unique_ptr<UINT32[]> m_isa_ram1;
- std::unique_ptr<UINT32[]> m_isa_ram2;
- UINT8 m_mtxc_config_reg[256];
- UINT8 m_piix4_config_reg[4][256];
+ std::unique_ptr<uint32_t[]> m_bios_ram;
+ std::unique_ptr<uint32_t[]> m_bios_ext1_ram;
+ std::unique_ptr<uint32_t[]> m_bios_ext2_ram;
+ std::unique_ptr<uint32_t[]> m_bios_ext3_ram;
+ std::unique_ptr<uint32_t[]> m_bios_ext4_ram;
+ std::unique_ptr<uint32_t[]> m_isa_ram1;
+ std::unique_ptr<uint32_t[]> m_isa_ram2;
+ uint8_t m_mtxc_config_reg[256];
+ uint8_t m_piix4_config_reg[4][256];
DECLARE_WRITE32_MEMBER( isa_ram1_w );
DECLARE_WRITE32_MEMBER( isa_ram2_w );
@@ -82,7 +82,7 @@ public:
// Intel 82439TX System Controller (MTXC)
-static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
+static uint8_t mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
{
xtom3d_state *state = busdevice->machine().driver_data<xtom3d_state>();
// osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
@@ -90,7 +90,7 @@ static UINT8 mtxc_config_r(device_t *busdevice, device_t *device, int function,
return state->m_mtxc_config_reg[reg];
}
-static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
+static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, uint8_t data)
{
xtom3d_state *state = busdevice->machine().driver_data<xtom3d_state>();
printf("MTXC: write %d, %02X, %02X\n", function, reg, data);
@@ -182,9 +182,9 @@ void xtom3d_state::intel82439tx_init()
m_mtxc_config_reg[0x65] = 0x02;
}
-static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
+static uint32_t intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, uint32_t mem_mask)
{
- UINT32 r = 0;
+ uint32_t r = 0;
if (ACCESSING_BITS_24_31)
{
r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24;
@@ -204,7 +204,7 @@ static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int func
return r;
}
-static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int function, int reg, UINT32 data, UINT32 mem_mask)
+static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int function, int reg, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_24_31)
{
@@ -226,23 +226,23 @@ static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int functi
// Intel 82371AB PCI-to-ISA / IDE bridge (PIIX4)
-static UINT8 piix4_config_r(device_t *busdevice, device_t *device, int function, int reg)
+static uint8_t piix4_config_r(device_t *busdevice, device_t *device, int function, int reg)
{
xtom3d_state *state = busdevice->machine().driver_data<xtom3d_state>();
// osd_printf_debug("PIIX4: read %d, %02X\n", function, reg);
return state->m_piix4_config_reg[function][reg];
}
-static void piix4_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
+static void piix4_config_w(device_t *busdevice, device_t *device, int function, int reg, uint8_t data)
{
xtom3d_state *state = busdevice->machine().driver_data<xtom3d_state>();
// osd_printf_debug("%s:PIIX4: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
state->m_piix4_config_reg[function][reg] = data;
}
-static UINT32 intel82371ab_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
+static uint32_t intel82371ab_pci_r(device_t *busdevice, device_t *device, int function, int reg, uint32_t mem_mask)
{
- UINT32 r = 0;
+ uint32_t r = 0;
if (ACCESSING_BITS_24_31)
{
r |= piix4_config_r(busdevice, device, function, reg + 3) << 24;
@@ -262,7 +262,7 @@ static UINT32 intel82371ab_pci_r(device_t *busdevice, device_t *device, int func
return r;
}
-static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int function, int reg, UINT32 data, UINT32 mem_mask)
+static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int function, int reg, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_24_31)
{
@@ -372,13 +372,13 @@ ADDRESS_MAP_END
void xtom3d_state::machine_start()
{
- m_bios_ram = std::make_unique<UINT32[]>(0x10000/4);
- m_bios_ext1_ram = std::make_unique<UINT32[]>(0x4000/4);
- m_bios_ext2_ram = std::make_unique<UINT32[]>(0x4000/4);
- m_bios_ext3_ram = std::make_unique<UINT32[]>(0x4000/4);
- m_bios_ext4_ram = std::make_unique<UINT32[]>(0x4000/4);
- m_isa_ram1 = std::make_unique<UINT32[]>(0x4000/4);
- m_isa_ram2 = std::make_unique<UINT32[]>(0x4000/4);
+ m_bios_ram = std::make_unique<uint32_t[]>(0x10000/4);
+ m_bios_ext1_ram = std::make_unique<uint32_t[]>(0x4000/4);
+ m_bios_ext2_ram = std::make_unique<uint32_t[]>(0x4000/4);
+ m_bios_ext3_ram = std::make_unique<uint32_t[]>(0x4000/4);
+ m_bios_ext4_ram = std::make_unique<uint32_t[]>(0x4000/4);
+ m_isa_ram1 = std::make_unique<uint32_t[]>(0x4000/4);
+ m_isa_ram2 = std::make_unique<uint32_t[]>(0x4000/4);
intel82439tx_init();
}