diff options
author | 2018-05-06 00:40:40 +1000 | |
---|---|---|
committer | 2018-05-06 00:51:27 +1000 | |
commit | 4ea3cd0bc1f54e47a0d38a47afac38101549e9ee (patch) | |
tree | bbadc20010b6bad48cf321b1c864655587e4b8ad /src/mame/drivers/ngen.cpp | |
parent | bba5127d7a73ca44fdc0dcab7286846c81206771 (diff) |
Streamline machine configuration macros - everyone's a device edition.
Start replacing special device macros with additional constructors,
starting with ISA, INTELLEC 4 and RS-232 buses.
Allow an object finder to take on the target of another object finder.
(For a combination of the previous two things in action, see either the
INTELLEC 4 driver, or the Apple 2 PC Exporter card. Also check out
looping over a device finder array to instantiate devices in some
places. Lots of things no longer need to pass tags around.)
Start supplying default clocks for things that have a standard clock or
have all clocks internal.
Eliminate the separate DEV versions of the DEVCB_ macros. Previously,
the plain versions were a shortcut for DEVICE_SELF as the target. You
can now supply a string tag (relative to current device being
configured), an object finder (takes on the base and relative tag), or
a reference to a device/interface (only do this if you know the device
won't be replaced out from under it, but that's a safe assumption for
your subdevices). In almost all cases, you can get the effect you want
by supplying *this as the target.
Eliminate sound and CPU versions of macros. They serve no useful
purpose, provide no extra checks, make error messages longer, add
indirection, and mislead newbies into thinking there's a difference.
Remove a lot of now-unnecessary ":" prefixes binding things relative to
machine root.
Clean up some miscellaneous rot.
Examples of new functionality in use in (some more subtle than others):
* src/mame/drivers/intellec4.cpp
* src/mame/drivers/tranz330.cpp
* src/mame/drivers/osboren1.cpp
* src/mame/drivers/zorba.cpp
* src/mame/devices/smioc.cpp
* src/devices/bus/a2bus/pc_xporter.cpp
* src/devices/bus/isa/isa.h
* src/devices/bus/isa/isa.h
* src/devices/bus/intellec4/intellec4.h
Diffstat (limited to 'src/mame/drivers/ngen.cpp')
-rw-r--r-- | src/mame/drivers/ngen.cpp | 226 |
1 files changed, 113 insertions, 113 deletions
diff --git a/src/mame/drivers/ngen.cpp b/src/mame/drivers/ngen.cpp index 311aa87d137..c47c841f63f 100644 --- a/src/mame/drivers/ngen.cpp +++ b/src/mame/drivers/ngen.cpp @@ -928,62 +928,62 @@ static void ngen_floppies(device_slot_interface &device) MACHINE_CONFIG_START(ngen_state::ngen) // basic machine hardware - MCFG_CPU_ADD("maincpu", I80186, XTAL(16'000'000) / 2) - MCFG_CPU_PROGRAM_MAP(ngen_mem) - MCFG_CPU_IO_MAP(ngen_io) - MCFG_80186_CHIP_SELECT_CB(WRITE16(ngen_state, cpu_peripheral_cb)) - MCFG_80186_TMROUT0_HANDLER(WRITELINE(ngen_state, cpu_timer_w)) - MCFG_80186_IRQ_SLAVE_ACK(READ8(ngen_state, irq_cb)) + MCFG_DEVICE_ADD("maincpu", I80186, XTAL(16'000'000) / 2) + MCFG_DEVICE_PROGRAM_MAP(ngen_mem) + MCFG_DEVICE_IO_MAP(ngen_io) + MCFG_80186_CHIP_SELECT_CB(WRITE16(*this, ngen_state, cpu_peripheral_cb)) + MCFG_80186_TMROUT0_HANDLER(WRITELINE(*this, ngen_state, cpu_timer_w)) + MCFG_80186_IRQ_SLAVE_ACK(READ8(*this, ngen_state, irq_cb)) MCFG_DEVICE_ADD("pic", PIC8259, 0) - MCFG_PIC8259_OUT_INT_CB(DEVWRITELINE("maincpu", i80186_cpu_device, int0_w)) + MCFG_PIC8259_OUT_INT_CB(WRITELINE("maincpu", i80186_cpu_device, int0_w)) MCFG_DEVICE_ADD("pit", PIT8254, 0) MCFG_PIT8253_CLK0(78120/4) // 19.53kHz, /4 of the CPU timer output? - MCFG_PIT8253_OUT0_HANDLER(WRITELINE(ngen_state, pit_out0_w)) // RS232 channel B baud rate + MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, ngen_state, pit_out0_w)) // RS232 channel B baud rate MCFG_PIT8253_CLK1(XTAL(14'745'600)/12) // correct? - based on patent - MCFG_PIT8253_OUT1_HANDLER(WRITELINE(ngen_state, pit_out1_w)) // RS232 channel A baud rate + MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, ngen_state, pit_out1_w)) // RS232 channel A baud rate MCFG_PIT8253_CLK2(XTAL(14'745'600)/12) - MCFG_PIT8253_OUT2_HANDLER(WRITELINE(ngen_state, pit_out2_w)) + MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, ngen_state, pit_out2_w)) MCFG_DEVICE_ADD("dmac", AM9517A, XTAL(14'745'600) / 3) // NEC D8237A, divisor unknown - MCFG_I8237_OUT_HREQ_CB(WRITELINE(ngen_state, dma_hrq_changed)) - MCFG_I8237_OUT_EOP_CB(WRITELINE(ngen_state, dma_eop_changed)) - MCFG_I8237_IN_MEMR_CB(READ8(ngen_state, dma_read_word)) // DMA is always 16-bit - MCFG_I8237_OUT_MEMW_CB(WRITE8(ngen_state, dma_write_word)) - MCFG_I8237_OUT_DACK_0_CB(WRITELINE(ngen_state, dack0_w)) - MCFG_I8237_OUT_DACK_1_CB(WRITELINE(ngen_state, dack1_w)) - MCFG_I8237_OUT_DACK_2_CB(WRITELINE(ngen_state, dack2_w)) - MCFG_I8237_OUT_DACK_3_CB(WRITELINE(ngen_state, dack3_w)) - MCFG_I8237_IN_IOR_0_CB(READ8(ngen_state, dma_0_dack_r)) - MCFG_I8237_IN_IOR_1_CB(READ8(ngen_state, dma_1_dack_r)) - MCFG_I8237_IN_IOR_2_CB(READ8(ngen_state, dma_2_dack_r)) - MCFG_I8237_IN_IOR_3_CB(READ8(ngen_state, dma_3_dack_r)) - MCFG_I8237_OUT_IOW_0_CB(WRITE8(ngen_state, dma_0_dack_w)) - MCFG_I8237_OUT_IOW_1_CB(WRITE8(ngen_state, dma_1_dack_w)) - MCFG_I8237_OUT_IOW_2_CB(WRITE8(ngen_state, dma_2_dack_w)) - MCFG_I8237_OUT_IOW_3_CB(WRITE8(ngen_state, dma_3_dack_w)) + MCFG_I8237_OUT_HREQ_CB(WRITELINE(*this, ngen_state, dma_hrq_changed)) + MCFG_I8237_OUT_EOP_CB(WRITELINE(*this, ngen_state, dma_eop_changed)) + MCFG_I8237_IN_MEMR_CB(READ8(*this, ngen_state, dma_read_word)) // DMA is always 16-bit + MCFG_I8237_OUT_MEMW_CB(WRITE8(*this, ngen_state, dma_write_word)) + MCFG_I8237_OUT_DACK_0_CB(WRITELINE(*this, ngen_state, dack0_w)) + MCFG_I8237_OUT_DACK_1_CB(WRITELINE(*this, ngen_state, dack1_w)) + MCFG_I8237_OUT_DACK_2_CB(WRITELINE(*this, ngen_state, dack2_w)) + MCFG_I8237_OUT_DACK_3_CB(WRITELINE(*this, ngen_state, dack3_w)) + MCFG_I8237_IN_IOR_0_CB(READ8(*this, ngen_state, dma_0_dack_r)) + MCFG_I8237_IN_IOR_1_CB(READ8(*this, ngen_state, dma_1_dack_r)) + MCFG_I8237_IN_IOR_2_CB(READ8(*this, ngen_state, dma_2_dack_r)) + MCFG_I8237_IN_IOR_3_CB(READ8(*this, ngen_state, dma_3_dack_r)) + MCFG_I8237_OUT_IOW_0_CB(WRITE8(*this, ngen_state, dma_0_dack_w)) + MCFG_I8237_OUT_IOW_1_CB(WRITE8(*this, ngen_state, dma_1_dack_w)) + MCFG_I8237_OUT_IOW_2_CB(WRITE8(*this, ngen_state, dma_2_dack_w)) + MCFG_I8237_OUT_IOW_3_CB(WRITE8(*this, ngen_state, dma_3_dack_w)) // I/O board MCFG_DEVICE_ADD("iouart", UPD7201, 0) // clocked by PIT channel 2? - MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_txd)) - MCFG_Z80DART_OUT_TXDB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_txd)) - MCFG_Z80DART_OUT_DTRA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_dtr)) - MCFG_Z80DART_OUT_DTRB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_dtr)) - MCFG_Z80DART_OUT_RTSA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_rts)) - MCFG_Z80DART_OUT_RTSB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_rts)) - - MCFG_RS232_PORT_ADD("rs232_a", default_rs232_devices, nullptr) - MCFG_RS232_RXD_HANDLER(DEVWRITELINE("iouart", upd7201_device, rxa_w)) - MCFG_RS232_CTS_HANDLER(DEVWRITELINE("iouart", upd7201_device, ctsa_w)) - MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_device, dcda_w)) - MCFG_RS232_RI_HANDLER(DEVWRITELINE("iouart", upd7201_device, ria_w)) - - MCFG_RS232_PORT_ADD("rs232_b", default_rs232_devices, nullptr) - MCFG_RS232_RXD_HANDLER(DEVWRITELINE("iouart", upd7201_device, rxb_w)) - MCFG_RS232_CTS_HANDLER(DEVWRITELINE("iouart", upd7201_device, ctsb_w)) - MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_device, dcdb_w)) - MCFG_RS232_RI_HANDLER(DEVWRITELINE("iouart", upd7201_device, rib_w)) + MCFG_Z80DART_OUT_TXDA_CB(WRITELINE("rs232_a", rs232_port_device, write_txd)) + MCFG_Z80DART_OUT_TXDB_CB(WRITELINE("rs232_b", rs232_port_device, write_txd)) + MCFG_Z80DART_OUT_DTRA_CB(WRITELINE("rs232_a", rs232_port_device, write_dtr)) + MCFG_Z80DART_OUT_DTRB_CB(WRITELINE("rs232_b", rs232_port_device, write_dtr)) + MCFG_Z80DART_OUT_RTSA_CB(WRITELINE("rs232_a", rs232_port_device, write_rts)) + MCFG_Z80DART_OUT_RTSB_CB(WRITELINE("rs232_b", rs232_port_device, write_rts)) + + MCFG_DEVICE_ADD("rs232_a", RS232_PORT, default_rs232_devices, nullptr) + MCFG_RS232_RXD_HANDLER(WRITELINE("iouart", upd7201_device, rxa_w)) + MCFG_RS232_CTS_HANDLER(WRITELINE("iouart", upd7201_device, ctsa_w)) + MCFG_RS232_DCD_HANDLER(WRITELINE("iouart", upd7201_device, dcda_w)) + MCFG_RS232_RI_HANDLER(WRITELINE("iouart", upd7201_device, ria_w)) + + MCFG_DEVICE_ADD("rs232_b", RS232_PORT, default_rs232_devices, nullptr) + MCFG_RS232_RXD_HANDLER(WRITELINE("iouart", upd7201_device, rxb_w)) + MCFG_RS232_CTS_HANDLER(WRITELINE("iouart", upd7201_device, ctsb_w)) + MCFG_RS232_DCD_HANDLER(WRITELINE("iouart", upd7201_device, dcdb_w)) + MCFG_RS232_RI_HANDLER(WRITELINE("iouart", upd7201_device, rib_w)) // TODO: SCN2652 MPCC (not implemented), used for RS-422 cluster communications? @@ -1002,32 +1002,32 @@ MACHINE_CONFIG_START(ngen_state::ngen) // keyboard UART (patent says i8251 is used for keyboard communications, it is located on the video board) MCFG_DEVICE_ADD("videouart", I8251, 0) // main clock unknown, Rx/Tx clocks are 19.53kHz -// MCFG_I8251_TXEMPTY_HANDLER(DEVWRITELINE("pic",pic8259_device,ir4_w)) - MCFG_I8251_TXD_HANDLER(DEVWRITELINE("keyboard", rs232_port_device, write_txd)) - MCFG_RS232_PORT_ADD("keyboard", keyboard, "ngen") - MCFG_RS232_RXD_HANDLER(DEVWRITELINE("videouart", i8251_device, write_rxd)) +// MCFG_I8251_TXEMPTY_HANDLER(WRITELINE("pic",pic8259_device,ir4_w)) + MCFG_I8251_TXD_HANDLER(WRITELINE("keyboard", rs232_port_device, write_txd)) + MCFG_DEVICE_ADD("keyboard", RS232_PORT, keyboard, "ngen") + MCFG_RS232_RXD_HANDLER(WRITELINE("videouart", i8251_device, write_rxd)) MCFG_DEVICE_ADD("refresh_clock", CLOCK, 19200*16) // should be 19530Hz - MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(ngen_state,timer_clk_out)) + MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(*this, ngen_state,timer_clk_out)) // floppy disk / hard disk module (WD2797 FDC, WD1010 HDC, plus an 8253 timer for each) MCFG_WD2797_ADD("fdc", XTAL(20'000'000) / 20) - MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(ngen_state,fdc_irq_w)) - MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("maincpu",i80186_cpu_device,drq1_w)) + MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(*this, ngen_state,fdc_irq_w)) + MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE("maincpu",i80186_cpu_device,drq1_w)) MCFG_WD_FDC_FORCE_READY MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0) MCFG_PIT8253_CLK0(0) - MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w)) // clocked on FDC data register access + MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic",pic8259_device,ir5_w)) // clocked on FDC data register access MCFG_PIT8253_CLK1(XTAL(20'000'000) / 20) -// MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w)) // 1MHz +// MCFG_PIT8253_OUT1_HANDLER(WRITELINE("pic",pic8259_device,ir5_w)) // 1MHz MCFG_PIT8253_CLK2(XTAL(20'000'000) / 20) -// MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w)) +// MCFG_PIT8253_OUT2_HANDLER(WRITELINE("pic",pic8259_device,ir5_w)) // TODO: WD1010 HDC (not implemented), use WD2010 for now MCFG_DEVICE_ADD("hdc", WD2010, XTAL(20'000'000) / 4) - MCFG_WD2010_OUT_INTRQ_CB(DEVWRITELINE("pic",pic8259_device,ir2_w)) - MCFG_WD2010_IN_BCS_CB(READ8(ngen_state,hd_buffer_r)) - MCFG_WD2010_OUT_BCS_CB(WRITE8(ngen_state,hd_buffer_w)) + MCFG_WD2010_OUT_INTRQ_CB(WRITELINE("pic",pic8259_device,ir2_w)) + MCFG_WD2010_IN_BCS_CB(READ8(*this, ngen_state,hd_buffer_r)) + MCFG_WD2010_OUT_BCS_CB(WRITE8(*this, ngen_state,hd_buffer_w)) MCFG_WD2010_IN_DRDY_CB(VCC) MCFG_WD2010_IN_INDEX_CB(VCC) MCFG_WD2010_IN_WF_CB(VCC) @@ -1041,60 +1041,60 @@ MACHINE_CONFIG_START(ngen_state::ngen) MACHINE_CONFIG_END MACHINE_CONFIG_START(ngen386_state::ngen386) - MCFG_CPU_ADD("i386cpu", I386, XTAL(50'000'000) / 2) - MCFG_CPU_PROGRAM_MAP(ngen386_mem) - MCFG_CPU_IO_MAP(ngen386_io) - MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic", pic8259_device, inta_cb) + MCFG_DEVICE_ADD("i386cpu", I386, XTAL(50'000'000) / 2) + MCFG_DEVICE_PROGRAM_MAP(ngen386_mem) + MCFG_DEVICE_IO_MAP(ngen386_io) + MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic", pic8259_device, inta_cb) MCFG_DEVICE_ADD("pic", PIC8259, 0) MCFG_PIC8259_OUT_INT_CB(INPUTLINE("i386cpu", 0)) MCFG_DEVICE_ADD("pit", PIT8254, 0) MCFG_PIT8253_CLK0(78120/4) // 19.53kHz, /4 of the CPU timer output? - MCFG_PIT8253_OUT0_HANDLER(WRITELINE(ngen_state, pit_out0_w)) // RS232 channel B baud rate + MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, ngen_state, pit_out0_w)) // RS232 channel B baud rate MCFG_PIT8253_CLK1(XTAL(14'745'600)/12) // correct? - based on patent - MCFG_PIT8253_OUT1_HANDLER(WRITELINE(ngen_state, pit_out1_w)) // RS232 channel A baud rate + MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, ngen_state, pit_out1_w)) // RS232 channel A baud rate MCFG_PIT8253_CLK2(XTAL(14'745'600)/12) - MCFG_PIT8253_OUT2_HANDLER(WRITELINE(ngen_state, pit_out2_w)) + MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, ngen_state, pit_out2_w)) MCFG_DEVICE_ADD("dmac", AM9517A, XTAL(14'745'600) / 3) // NEC D8237A, divisor unknown - MCFG_I8237_OUT_HREQ_CB(WRITELINE(ngen_state, dma_hrq_changed)) - MCFG_I8237_OUT_EOP_CB(WRITELINE(ngen_state, dma_eop_changed)) - MCFG_I8237_IN_MEMR_CB(READ8(ngen_state, dma_read_word)) // DMA is always 16-bit - MCFG_I8237_OUT_MEMW_CB(WRITE8(ngen_state, dma_write_word)) - MCFG_I8237_OUT_DACK_0_CB(WRITELINE(ngen_state, dack0_w)) - MCFG_I8237_OUT_DACK_1_CB(WRITELINE(ngen_state, dack1_w)) - MCFG_I8237_OUT_DACK_2_CB(WRITELINE(ngen_state, dack2_w)) - MCFG_I8237_OUT_DACK_3_CB(WRITELINE(ngen_state, dack3_w)) - MCFG_I8237_IN_IOR_0_CB(READ8(ngen_state, dma_0_dack_r)) - MCFG_I8237_IN_IOR_1_CB(READ8(ngen_state, dma_1_dack_r)) - MCFG_I8237_IN_IOR_2_CB(READ8(ngen_state, dma_2_dack_r)) - MCFG_I8237_IN_IOR_3_CB(READ8(ngen_state, dma_3_dack_r)) - MCFG_I8237_OUT_IOW_0_CB(WRITE8(ngen_state, dma_0_dack_w)) - MCFG_I8237_OUT_IOW_1_CB(WRITE8(ngen_state, dma_1_dack_w)) - MCFG_I8237_OUT_IOW_2_CB(WRITE8(ngen_state, dma_2_dack_w)) - MCFG_I8237_OUT_IOW_3_CB(WRITE8(ngen_state, dma_3_dack_w)) + MCFG_I8237_OUT_HREQ_CB(WRITELINE(*this, ngen_state, dma_hrq_changed)) + MCFG_I8237_OUT_EOP_CB(WRITELINE(*this, ngen_state, dma_eop_changed)) + MCFG_I8237_IN_MEMR_CB(READ8(*this, ngen_state, dma_read_word)) // DMA is always 16-bit + MCFG_I8237_OUT_MEMW_CB(WRITE8(*this, ngen_state, dma_write_word)) + MCFG_I8237_OUT_DACK_0_CB(WRITELINE(*this, ngen_state, dack0_w)) + MCFG_I8237_OUT_DACK_1_CB(WRITELINE(*this, ngen_state, dack1_w)) + MCFG_I8237_OUT_DACK_2_CB(WRITELINE(*this, ngen_state, dack2_w)) + MCFG_I8237_OUT_DACK_3_CB(WRITELINE(*this, ngen_state, dack3_w)) + MCFG_I8237_IN_IOR_0_CB(READ8(*this, ngen_state, dma_0_dack_r)) + MCFG_I8237_IN_IOR_1_CB(READ8(*this, ngen_state, dma_1_dack_r)) + MCFG_I8237_IN_IOR_2_CB(READ8(*this, ngen_state, dma_2_dack_r)) + MCFG_I8237_IN_IOR_3_CB(READ8(*this, ngen_state, dma_3_dack_r)) + MCFG_I8237_OUT_IOW_0_CB(WRITE8(*this, ngen_state, dma_0_dack_w)) + MCFG_I8237_OUT_IOW_1_CB(WRITE8(*this, ngen_state, dma_1_dack_w)) + MCFG_I8237_OUT_IOW_2_CB(WRITE8(*this, ngen_state, dma_2_dack_w)) + MCFG_I8237_OUT_IOW_3_CB(WRITE8(*this, ngen_state, dma_3_dack_w)) // I/O board MCFG_DEVICE_ADD("iouart", UPD7201, 0) // clocked by PIT channel 2? - MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_txd)) - MCFG_Z80DART_OUT_TXDB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_txd)) - MCFG_Z80DART_OUT_DTRA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_dtr)) - MCFG_Z80DART_OUT_DTRB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_dtr)) - MCFG_Z80DART_OUT_RTSA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_rts)) - MCFG_Z80DART_OUT_RTSB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_rts)) - - MCFG_RS232_PORT_ADD("rs232_a", default_rs232_devices, nullptr) - MCFG_RS232_RXD_HANDLER(DEVWRITELINE("iouart", upd7201_device, rxa_w)) - MCFG_RS232_CTS_HANDLER(DEVWRITELINE("iouart", upd7201_device, ctsa_w)) - MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_device, dcda_w)) - MCFG_RS232_RI_HANDLER(DEVWRITELINE("iouart", upd7201_device, ria_w)) - - MCFG_RS232_PORT_ADD("rs232_b", default_rs232_devices, nullptr) - MCFG_RS232_RXD_HANDLER(DEVWRITELINE("iouart", upd7201_device, rxb_w)) - MCFG_RS232_CTS_HANDLER(DEVWRITELINE("iouart", upd7201_device, ctsb_w)) - MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_device, dcdb_w)) - MCFG_RS232_RI_HANDLER(DEVWRITELINE("iouart", upd7201_device, rib_w)) + MCFG_Z80DART_OUT_TXDA_CB(WRITELINE("rs232_a", rs232_port_device, write_txd)) + MCFG_Z80DART_OUT_TXDB_CB(WRITELINE("rs232_b", rs232_port_device, write_txd)) + MCFG_Z80DART_OUT_DTRA_CB(WRITELINE("rs232_a", rs232_port_device, write_dtr)) + MCFG_Z80DART_OUT_DTRB_CB(WRITELINE("rs232_b", rs232_port_device, write_dtr)) + MCFG_Z80DART_OUT_RTSA_CB(WRITELINE("rs232_a", rs232_port_device, write_rts)) + MCFG_Z80DART_OUT_RTSB_CB(WRITELINE("rs232_b", rs232_port_device, write_rts)) + + MCFG_DEVICE_ADD("rs232_a", RS232_PORT, default_rs232_devices, nullptr) + MCFG_RS232_RXD_HANDLER(WRITELINE("iouart", upd7201_device, rxa_w)) + MCFG_RS232_CTS_HANDLER(WRITELINE("iouart", upd7201_device, ctsa_w)) + MCFG_RS232_DCD_HANDLER(WRITELINE("iouart", upd7201_device, dcda_w)) + MCFG_RS232_RI_HANDLER(WRITELINE("iouart", upd7201_device, ria_w)) + + MCFG_DEVICE_ADD("rs232_b", RS232_PORT, default_rs232_devices, nullptr) + MCFG_RS232_RXD_HANDLER(WRITELINE("iouart", upd7201_device, rxb_w)) + MCFG_RS232_CTS_HANDLER(WRITELINE("iouart", upd7201_device, ctsb_w)) + MCFG_RS232_DCD_HANDLER(WRITELINE("iouart", upd7201_device, dcdb_w)) + MCFG_RS232_RI_HANDLER(WRITELINE("iouart", upd7201_device, rib_w)) // TODO: SCN2652 MPCC (not implemented), used for RS-422 cluster communications? @@ -1113,32 +1113,32 @@ MACHINE_CONFIG_START(ngen386_state::ngen386) // keyboard UART (patent says i8251 is used for keyboard communications, it is located on the video board) MCFG_DEVICE_ADD("videouart", I8251, 0) // main clock unknown, Rx/Tx clocks are 19.53kHz -// MCFG_I8251_TXEMPTY_HANDLER(DEVWRITELINE("pic",pic8259_device,ir4_w)) - MCFG_I8251_TXD_HANDLER(DEVWRITELINE("keyboard", rs232_port_device, write_txd)) - MCFG_RS232_PORT_ADD("keyboard", keyboard, "ngen") - MCFG_RS232_RXD_HANDLER(DEVWRITELINE("videouart", i8251_device, write_rxd)) +// MCFG_I8251_TXEMPTY_HANDLER(WRITELINE("pic",pic8259_device,ir4_w)) + MCFG_I8251_TXD_HANDLER(WRITELINE("keyboard", rs232_port_device, write_txd)) + MCFG_DEVICE_ADD("keyboard", RS232_PORT, keyboard, "ngen") + MCFG_RS232_RXD_HANDLER(WRITELINE("videouart", i8251_device, write_rxd)) MCFG_DEVICE_ADD("refresh_clock", CLOCK, 19200*16) // should be 19530Hz - MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(ngen_state,timer_clk_out)) + MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(*this, ngen_state,timer_clk_out)) // floppy disk / hard disk module (WD2797 FDC, WD1010 HDC, plus an 8253 timer for each) MCFG_WD2797_ADD("fdc", XTAL(20'000'000) / 20) - MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(ngen_state,fdc_irq_w)) -// MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("i386cpu",i80186_cpu_device,drq1_w)) + MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(*this, ngen_state,fdc_irq_w)) +// MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE("i386cpu",i80186_cpu_device,drq1_w)) MCFG_WD_FDC_FORCE_READY MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0) MCFG_PIT8253_CLK0(0) - MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w)) // clocked on FDC data register access + MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic",pic8259_device,ir5_w)) // clocked on FDC data register access MCFG_PIT8253_CLK1(XTAL(20'000'000) / 20) -// MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w)) // 1MHz +// MCFG_PIT8253_OUT1_HANDLER(WRITELINE("pic",pic8259_device,ir5_w)) // 1MHz MCFG_PIT8253_CLK2(XTAL(20'000'000) / 20) -// MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w)) +// MCFG_PIT8253_OUT2_HANDLER(WRITELINE("pic",pic8259_device,ir5_w)) // TODO: WD1010 HDC (not implemented), use WD2010 for now MCFG_DEVICE_ADD("hdc", WD2010, XTAL(20'000'000) / 4) - MCFG_WD2010_OUT_INTRQ_CB(DEVWRITELINE("pic",pic8259_device,ir2_w)) - MCFG_WD2010_IN_BCS_CB(READ8(ngen_state,hd_buffer_r)) - MCFG_WD2010_OUT_BCS_CB(WRITE8(ngen_state,hd_buffer_w)) + MCFG_WD2010_OUT_INTRQ_CB(WRITELINE("pic",pic8259_device,ir2_w)) + MCFG_WD2010_IN_BCS_CB(READ8(*this, ngen_state,hd_buffer_r)) + MCFG_WD2010_OUT_BCS_CB(WRITE8(*this, ngen_state,hd_buffer_w)) MCFG_WD2010_IN_DRDY_CB(VCC) MCFG_WD2010_IN_INDEX_CB(VCC) MCFG_WD2010_IN_WF_CB(VCC) @@ -1152,8 +1152,8 @@ MACHINE_CONFIG_END MACHINE_CONFIG_START(ngen386_state::_386i) ngen386(config); - MCFG_CPU_MODIFY("i386cpu") - MCFG_CPU_PROGRAM_MAP(ngen386i_mem) + MCFG_DEVICE_MODIFY("i386cpu") + MCFG_DEVICE_PROGRAM_MAP(ngen386i_mem) MACHINE_CONFIG_END ROM_START( ngen ) |