diff options
author | 2016-10-22 13:13:17 +0200 | |
---|---|---|
committer | 2016-10-22 13:13:17 +0200 | |
commit | ddb290d5f615019c33c42b8d94e5a5254cabcf33 (patch) | |
tree | a70f688b0df3acd19da7b1151e5902e3c6af3fa5 /src/mame/drivers/model3.cpp | |
parent | 333bff8de64dfaeb98134000412796b4fdef970b (diff) |
NOTICE (TYPE NAME CONSOLIDATION)
Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8
also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
Diffstat (limited to 'src/mame/drivers/model3.cpp')
-rw-r--r-- | src/mame/drivers/model3.cpp | 186 |
1 files changed, 93 insertions, 93 deletions
diff --git a/src/mame/drivers/model3.cpp b/src/mame/drivers/model3.cpp index 3c448e3912f..a49b05f83c5 100644 --- a/src/mame/drivers/model3.cpp +++ b/src/mame/drivers/model3.cpp @@ -755,7 +755,7 @@ void model3_state::update_irq_state() } } -void model3_state::set_irq_line(UINT8 bit, int line) +void model3_state::set_irq_line(uint8_t bit, int line) { if (line != CLEAR_LINE) m_irq_state |= bit; @@ -769,7 +769,7 @@ void model3_state::set_irq_line(UINT8 bit, int line) /* Motorola MPC105 PCI Bridge/Memory Controller */ -UINT32 model3_state::pci_device_get_reg() +uint32_t model3_state::pci_device_get_reg() { int device = m_pci_device; int reg = m_pci_reg; @@ -822,7 +822,7 @@ UINT32 model3_state::pci_device_get_reg() return 0; } -void model3_state::pci_device_set_reg(UINT32 value) +void model3_state::pci_device_set_reg(uint32_t value) { int device = m_pci_device; int reg = m_pci_reg; @@ -899,7 +899,7 @@ READ64_MEMBER(model3_state::mpc105_addr_r) { if (ACCESSING_BITS_32_63) { - return (UINT64)m_mpc105_addr << 32; + return (uint64_t)m_mpc105_addr << 32; } return 0; } @@ -908,7 +908,7 @@ WRITE64_MEMBER(model3_state::mpc105_addr_w) { if (ACCESSING_BITS_32_63) { - UINT32 d = flipendian_int32((UINT32)(data >> 32)); + uint32_t d = flipendian_int32((uint32_t)(data >> 32)); m_mpc105_addr = data >> 32; m_pci_bus = (d >> 16) & 0xff; @@ -921,8 +921,8 @@ WRITE64_MEMBER(model3_state::mpc105_addr_w) READ64_MEMBER(model3_state::mpc105_data_r) { if(m_pci_device == 0) { - return ((UINT64)(flipendian_int32(m_mpc105_regs[(m_pci_reg/2)+1])) << 32) | - ((UINT64)(flipendian_int32(m_mpc105_regs[(m_pci_reg/2)+0]))); + return ((uint64_t)(flipendian_int32(m_mpc105_regs[(m_pci_reg/2)+1])) << 32) | + ((uint64_t)(flipendian_int32(m_mpc105_regs[(m_pci_reg/2)+0]))); } return flipendian_int32(pci_device_get_reg()); } @@ -930,26 +930,26 @@ READ64_MEMBER(model3_state::mpc105_data_r) WRITE64_MEMBER(model3_state::mpc105_data_w) { if(m_pci_device == 0) { - m_mpc105_regs[(m_pci_reg/2)+1] = flipendian_int32((UINT32)(data >> 32)); - m_mpc105_regs[(m_pci_reg/2)+0] = flipendian_int32((UINT32)(data)); + m_mpc105_regs[(m_pci_reg/2)+1] = flipendian_int32((uint32_t)(data >> 32)); + m_mpc105_regs[(m_pci_reg/2)+0] = flipendian_int32((uint32_t)(data)); return; } if (ACCESSING_BITS_0_31) { - pci_device_set_reg(flipendian_int32((UINT32)data)); + pci_device_set_reg(flipendian_int32((uint32_t)data)); } } READ64_MEMBER(model3_state::mpc105_reg_r) { - return ((UINT64)(m_mpc105_regs[(offset*2)+0]) << 32) | - (UINT64)(m_mpc105_regs[(offset*2)+1]); + return ((uint64_t)(m_mpc105_regs[(offset*2)+0]) << 32) | + (uint64_t)(m_mpc105_regs[(offset*2)+1]); } WRITE64_MEMBER(model3_state::mpc105_reg_w) { - m_mpc105_regs[(offset*2)+0] = (UINT32)(data >> 32); - m_mpc105_regs[(offset*2)+1] = (UINT32)data; + m_mpc105_regs[(offset*2)+0] = (uint32_t)(data >> 32); + m_mpc105_regs[(offset*2)+1] = (uint32_t)data; } static void mpc105_init(running_machine &machine) @@ -976,7 +976,7 @@ READ64_MEMBER(model3_state::mpc106_addr_r) { if (ACCESSING_BITS_32_63) { - return (UINT64)m_mpc106_addr << 32; + return (uint64_t)m_mpc106_addr << 32; } return 0; } @@ -985,7 +985,7 @@ WRITE64_MEMBER(model3_state::mpc106_addr_w) { if (ACCESSING_BITS_32_63) { - UINT32 d = flipendian_int32((UINT32)(data >> 32)); + uint32_t d = flipendian_int32((uint32_t)(data >> 32)); if (((d >> 8) & 0xffffff) == 0x800000) { @@ -1006,42 +1006,42 @@ WRITE64_MEMBER(model3_state::mpc106_addr_w) READ64_MEMBER(model3_state::mpc106_data_r) { if(m_pci_device == 0) { - return ((UINT64)(flipendian_int32(m_mpc106_regs[(m_pci_reg/2)+1])) << 32) | - ((UINT64)(flipendian_int32(m_mpc106_regs[(m_pci_reg/2)+0]))); + return ((uint64_t)(flipendian_int32(m_mpc106_regs[(m_pci_reg/2)+1])) << 32) | + ((uint64_t)(flipendian_int32(m_mpc106_regs[(m_pci_reg/2)+0]))); } if (ACCESSING_BITS_32_63) { - return (UINT64)(flipendian_int32(pci_device_get_reg())) << 32; + return (uint64_t)(flipendian_int32(pci_device_get_reg())) << 32; } else { - return (UINT64)(flipendian_int32(pci_device_get_reg())); + return (uint64_t)(flipendian_int32(pci_device_get_reg())); } } WRITE64_MEMBER(model3_state::mpc106_data_w) { if(m_pci_device == 0) { - m_mpc106_regs[(m_pci_reg/2)+1] = flipendian_int32((UINT32)(data >> 32)); - m_mpc106_regs[(m_pci_reg/2)+0] = flipendian_int32((UINT32)(data)); + m_mpc106_regs[(m_pci_reg/2)+1] = flipendian_int32((uint32_t)(data >> 32)); + m_mpc106_regs[(m_pci_reg/2)+0] = flipendian_int32((uint32_t)(data)); return; } if (ACCESSING_BITS_0_31) { - pci_device_set_reg(flipendian_int32((UINT32)data)); + pci_device_set_reg(flipendian_int32((uint32_t)data)); } } READ64_MEMBER(model3_state::mpc106_reg_r) { - return ((UINT64)(m_mpc106_regs[(offset*2)+0]) << 32) | - (UINT64)(m_mpc106_regs[(offset*2)+1]); + return ((uint64_t)(m_mpc106_regs[(offset*2)+0]) << 32) | + (uint64_t)(m_mpc106_regs[(offset*2)+1]); } WRITE64_MEMBER(model3_state::mpc106_reg_w) { - m_mpc106_regs[(offset*2)+0] = (UINT32)(data >> 32); - m_mpc106_regs[(offset*2)+1] = (UINT32)data; + m_mpc106_regs[(offset*2)+0] = (uint32_t)(data >> 32); + m_mpc106_regs[(offset*2)+1] = (uint32_t)data; } static void mpc106_init(running_machine &machine) @@ -1070,30 +1070,30 @@ static void mpc106_init(running_machine &machine) READ64_MEMBER(model3_state::scsi_r) { int reg = offset*8; - UINT64 r = 0; + uint64_t r = 0; if (ACCESSING_BITS_56_63) { - r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+0) << 56; + r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+0) << 56; } if (ACCESSING_BITS_48_55) { - r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+1) << 48; + r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+1) << 48; } if (ACCESSING_BITS_40_47) { - r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+2) << 40; + r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+2) << 40; } if (ACCESSING_BITS_32_39) { - r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+3) << 32; + r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+3) << 32; } if (ACCESSING_BITS_24_31) { - r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+4) << 24; + r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+4) << 24; } if (ACCESSING_BITS_16_23) { - r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+5) << 16; + r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+5) << 16; } if (ACCESSING_BITS_8_15) { - r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+6) << 8; + r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+6) << 8; } if (ACCESSING_BITS_0_7) { - r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+7) << 0; + r |= (uint64_t)m_lsi53c810->lsi53c810_reg_r(reg+7) << 0; } return r; @@ -1131,7 +1131,7 @@ WRITE64_MEMBER(model3_state::scsi_w) LSI53C810_FETCH_CB(model3_state::scsi_fetch) { address_space &space = m_maincpu->space(AS_PROGRAM); - UINT32 result = space.read_dword(dsp); + uint32_t result = space.read_dword(dsp); return flipendian_int32(result); } @@ -1157,7 +1157,7 @@ READ64_MEMBER(model3_state::real3d_dma_r) } break; } - osd_printf_debug("real3d_dma_r: %08X, %08X%08X\n", offset, (UINT32)(mem_mask >> 32), (UINT32)(mem_mask)); + osd_printf_debug("real3d_dma_r: %08X, %08X%08X\n", offset, (uint32_t)(mem_mask >> 32), (uint32_t)(mem_mask)); return 0; } @@ -1167,18 +1167,18 @@ WRITE64_MEMBER(model3_state::real3d_dma_w) { case 0: if(ACCESSING_BITS_32_63) { /* DMA source address */ - m_dma_source = flipendian_int32((UINT32)(data >> 32)); + m_dma_source = flipendian_int32((uint32_t)(data >> 32)); return; } if(ACCESSING_BITS_0_31) { /* DMA destination address */ - m_dma_dest = flipendian_int32((UINT32)(data)); + m_dma_dest = flipendian_int32((uint32_t)(data)); return; } break; case 1: if(ACCESSING_BITS_32_63) /* DMA length */ { - int length = flipendian_int32((UINT32)(data >> 32)) * 4; + int length = flipendian_int32((uint32_t)(data >> 32)) * 4; if (m_dma_endian & 0x80) { real3d_dma_callback(m_dma_source, m_dma_dest, length, 0); @@ -1207,7 +1207,7 @@ WRITE64_MEMBER(model3_state::real3d_dma_w) break; case 2: if(ACCESSING_BITS_32_63) { /* DMA command */ - UINT32 cmd = flipendian_int32((UINT32)(data >> 32)); + uint32_t cmd = flipendian_int32((uint32_t)(data >> 32)); if(cmd & 0x20000000) { m_dma_data = flipendian_int32(m_real3d_device_id); /* (PCI Vendor & Device ID) */ } @@ -1225,7 +1225,7 @@ WRITE64_MEMBER(model3_state::real3d_dma_w) } return; } - logerror("real3d_dma_w: %08X, %08X%08X, %08X%08X", offset, (UINT32)(data >> 32), (UINT32)(data), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask)); + logerror("real3d_dma_w: %08X, %08X%08X, %08X%08X", offset, (uint32_t)(data >> 32), (uint32_t)(data), (uint32_t)(mem_mask >> 32), (uint32_t)(mem_mask)); } LSI53C810_DMA_CB(model3_state::real3d_dma_callback) @@ -1375,7 +1375,7 @@ READ64_MEMBER(model3_state::model3_ctrl_r) case 0: if (ACCESSING_BITS_56_63) { - return (UINT64)m_controls_bank << 56; + return (uint64_t)m_controls_bank << 56; } else if (ACCESSING_BITS_24_31) { @@ -1393,7 +1393,7 @@ READ64_MEMBER(model3_state::model3_ctrl_r) case 1: if (ACCESSING_BITS_56_63) { - return (UINT64)ioport("IN2")->read() << 56; + return (uint64_t)ioport("IN2")->read() << 56; } else if (ACCESSING_BITS_24_31) { @@ -1413,14 +1413,14 @@ READ64_MEMBER(model3_state::model3_ctrl_r) case 5: if (ACCESSING_BITS_24_31) /* Serial comm RX FIFO 1 */ { - return (UINT64)m_serial_fifo1 << 24; + return (uint64_t)m_serial_fifo1 << 24; } break; case 6: if (ACCESSING_BITS_56_63) /* Serial comm RX FIFO 2 */ { - return (UINT64)m_serial_fifo2 << 56; + return (uint64_t)m_serial_fifo2 << 56; } else if (ACCESSING_BITS_24_31) /* Serial comm full/empty flags */ { @@ -1431,15 +1431,15 @@ READ64_MEMBER(model3_state::model3_ctrl_r) case 7: if (ACCESSING_BITS_24_31) /* ADC Data read */ { - const UINT8 adc_data = m_adc_ports[m_adc_channel].read_safe(0); + const uint8_t adc_data = m_adc_ports[m_adc_channel].read_safe(0); m_adc_channel++; m_adc_channel &= 0x7; - return (UINT64)adc_data << 24; + return (uint64_t)adc_data << 24; } break; } - logerror("ctrl_r: %02X, %08X%08X", offset, (UINT32)(mem_mask >> 32), (UINT32)(mem_mask)); + logerror("ctrl_r: %02X, %08X%08X", offset, (uint32_t)(mem_mask >> 32), (uint32_t)(mem_mask)); return 0; } @@ -1514,7 +1514,7 @@ WRITE64_MEMBER(model3_state::model3_ctrl_w) } break; default: - //osd_printf_debug("Lightgun: Unknown command %02X at %08X\n", (UINT32)(data >> 24), space.device().safe_pc()); + //osd_printf_debug("Lightgun: Unknown command %02X at %08X\n", (uint32_t)(data >> 24), space.device().safe_pc()); break; } } @@ -1536,7 +1536,7 @@ WRITE64_MEMBER(model3_state::model3_ctrl_w) return; } - logerror("ctrl_w: %02X, %08X%08X, %08X%08X", offset, (UINT32)(data >> 32), (UINT32)(data), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask)); + logerror("ctrl_w: %02X, %08X%08X, %08X%08X", offset, (uint32_t)(data >> 32), (uint32_t)(data), (uint32_t)(mem_mask >> 32), (uint32_t)(mem_mask)); } READ64_MEMBER(model3_state::model3_sys_r) @@ -1548,14 +1548,14 @@ READ64_MEMBER(model3_state::model3_sys_r) case 0x08/8: if (ACCESSING_BITS_56_63) { - return ((UINT64)m_crom_bank << 56); + return ((uint64_t)m_crom_bank << 56); } break; case 0x10/8: if (ACCESSING_BITS_56_63) { - UINT64 res = tap_read(); + uint64_t res = tap_read(); return res<<61; } @@ -1563,14 +1563,14 @@ READ64_MEMBER(model3_state::model3_sys_r) { return (m_irq_enable<<24); } - else logerror("m3_sys: Unk sys_r @ 0x10: mask = %x\n", (UINT32)mem_mask); + else logerror("m3_sys: Unk sys_r @ 0x10: mask = %x\n", (uint32_t)mem_mask); break; case 0x18/8: // printf("read irq_state %x (PC %x)\n", m_irq_state, space.device().safe_pc()); - return (UINT64)m_irq_state<<56 | 0xff000000; + return (uint64_t)m_irq_state<<56 | 0xff000000; } - logerror("Unknown model3 sys_r: offs %08X mask %08X\n", offset, (UINT32)mem_mask); + logerror("Unknown model3 sys_r: offs %08X mask %08X\n", offset, (uint32_t)mem_mask); return 0; } @@ -1590,8 +1590,8 @@ WRITE64_MEMBER(model3_state::model3_sys_w) case 0x18/8: if ((mem_mask & 0xff000000) == 0xff000000) // int ACK with bits in REVERSE ORDER from the other registers (Seeeee-gaaaa!) { // may also be a secondary enable based on behavior of e.g. magtruck VBL handler -// UINT32 old_irq = m_irq_state; - UINT8 ack = (data>>24)&0xff, realack; +// uint32_t old_irq = m_irq_state; + uint8_t ack = (data>>24)&0xff, realack; int i; switch (ack) @@ -1646,12 +1646,12 @@ WRITE64_MEMBER(model3_state::model3_sys_w) READ64_MEMBER(model3_state::model3_rtc_r) { - UINT64 r = 0; + uint64_t r = 0; if(ACCESSING_BITS_56_63) { - r |= (UINT64)rtc72421_r(space, (offset*2)+0, (UINT32)(mem_mask >> 32)) << 32; + r |= (uint64_t)rtc72421_r(space, (offset*2)+0, (uint32_t)(mem_mask >> 32)) << 32; } if(ACCESSING_BITS_24_31) { - r |= (UINT64)rtc72421_r(space, (offset*2)+1, (UINT32)(mem_mask)); + r |= (uint64_t)rtc72421_r(space, (offset*2)+1, (uint32_t)(mem_mask)); } return r; } @@ -1659,10 +1659,10 @@ READ64_MEMBER(model3_state::model3_rtc_r) WRITE64_MEMBER(model3_state::model3_rtc_w) { if(ACCESSING_BITS_56_63) { - rtc72421_w(space, (offset*2)+0, (UINT32)(data >> 32), (UINT32)(mem_mask >> 32)); + rtc72421_w(space, (offset*2)+0, (uint32_t)(data >> 32), (uint32_t)(mem_mask >> 32)); } if(ACCESSING_BITS_24_31) { - rtc72421_w(space, (offset*2)+1, (UINT32)(data), (UINT32)(mem_mask)); + rtc72421_w(space, (offset*2)+1, (uint32_t)(data), (uint32_t)(mem_mask)); } } @@ -1687,7 +1687,7 @@ READ8_MEMBER(model3_state::model3_sound_r) { case 4: { - UINT8 res = 0; + uint8_t res = 0; res |= 1; res |= 0x2; // magtruck country check return res; @@ -1736,7 +1736,7 @@ WRITE8_MEMBER(model3_state::model3_sound_w) READ64_MEMBER(model3_state::model3_5881prot_r) { - UINT64 retvalue = U64(0xffffffffffffffff); + uint64_t retvalue = U64(0xffffffffffffffff); if (offset == 0x00 / 8) { @@ -1753,17 +1753,17 @@ READ64_MEMBER(model3_state::model3_5881prot_r) } else { - UINT8* base; + uint8_t* base; retvalue = m_cryptdevice->do_decrypt(base); // retvalue = ((retvalue & 0xff00) >> 8) | ((retvalue & 0x00ff) << 8); // don't endian swap the return value on this hardware retvalue <<= 16; } - // printf("model3_5881prot_r offset %08x : %08x%08x (%08x%08x)\n", offset * 8, (UINT32)(retvalue >> 32), (UINT32)(retvalue & 0xffffffff), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask & 0xffffffff)); + // printf("model3_5881prot_r offset %08x : %08x%08x (%08x%08x)\n", offset * 8, (uint32_t)(retvalue >> 32), (uint32_t)(retvalue & 0xffffffff), (uint32_t)(mem_mask >> 32), (uint32_t)(mem_mask & 0xffffffff)); } else { - printf("model3_5881prot_r offset %08x : %08x%08x (%08x%08x)\n", offset * 8, (UINT32)(retvalue >> 32), (UINT32)(retvalue & 0xffffffff), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask & 0xffffffff)); + printf("model3_5881prot_r offset %08x : %08x%08x (%08x%08x)\n", offset * 8, (uint32_t)(retvalue >> 32), (uint32_t)(retvalue & 0xffffffff), (uint32_t)(mem_mask >> 32), (uint32_t)(mem_mask & 0xffffffff)); } return retvalue; @@ -1786,14 +1786,14 @@ WRITE64_MEMBER(model3_state::model3_5881prot_w) } else if (offset == 0x18 / 8) { - UINT16 subkey = data >> (32 + 16); + uint16_t subkey = data >> (32 + 16); subkey = ((subkey & 0xff00) >> 8) | ((subkey & 0x00ff) << 8); // endian swap the sub-key for this hardware printf("model3_5881prot_w setting subkey %04x\n", subkey); m_cryptdevice->set_subkey(subkey); } else { - printf("model3_5881prot_w offset %08x : %08x%08x (%08x%08x)\n", offset * 8, (UINT32)(data >> 32), (UINT32)(data & 0xffffffff), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask & 0xffffffff)); + printf("model3_5881prot_w offset %08x : %08x%08x (%08x%08x)\n", offset * 8, (uint32_t)(data >> 32), (uint32_t)(data & 0xffffffff), (uint32_t)(mem_mask >> 32), (uint32_t)(mem_mask & 0xffffffff)); } } @@ -5475,7 +5475,7 @@ WRITE16_MEMBER(model3_state::model3snd_ctrl) // handle sample banking if (memregion("scsp2")->bytes() > 0x800000) { - UINT8 *snd = memregion("scsp2")->base(); + uint8_t *snd = memregion("scsp2")->base(); if (data & 0x20) { membank("bank4")->set_base(snd + 0x200000); @@ -5720,9 +5720,9 @@ static MACHINE_CONFIG_START(model3_21, model3_state) MACHINE_CONFIG_END -UINT16 model3_state::crypt_read_callback(UINT32 addr) +uint16_t model3_state::crypt_read_callback(uint32_t addr) { - UINT16 dat = 0; + uint16_t dat = 0; if (addr < 0x8000) { dat = m_maincpu->space().read_word((0xf0180000 + 4 * addr)); // every other word is unused in this RAM, probably 32-bit ram on 64-bit bus? @@ -5745,13 +5745,13 @@ static void interleave_vroms(running_machine &machine) model3_state *state = machine.driver_data<model3_state>(); int start; int i,j,x; - UINT16 *vrom1 = (UINT16*)state->memregion("user3")->base(); - UINT16 *vrom2 = (UINT16*)state->memregion("user4")->base(); + uint16_t *vrom1 = (uint16_t*)state->memregion("user3")->base(); + uint16_t *vrom2 = (uint16_t*)state->memregion("user4")->base(); int vrom_length = state->memregion("user3")->bytes(); - UINT16 *vrom; + uint16_t *vrom; - state->m_vrom = std::make_unique<UINT32[]>(0x4000000/4); - vrom = (UINT16 *)state->m_vrom.get(); + state->m_vrom = std::make_unique<uint32_t[]>(0x4000000/4); + vrom = (uint16_t *)state->m_vrom.get(); if( vrom_length <= 0x1000000 ) { start = 0x1000000; @@ -5818,7 +5818,7 @@ DRIVER_INIT_MEMBER(model3_state,model3_20) DRIVER_INIT_MEMBER(model3_state,lostwsga) { - UINT32 *rom = (UINT32*)memregion("user1")->base(); + uint32_t *rom = (uint32_t*)memregion("user1")->base(); DRIVER_INIT_CALL(model3_15); m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc1000000, 0xc10000ff, read64_delegate(FUNC(model3_state::scsi_r),this), write64_delegate(FUNC(model3_state::scsi_w),this)); @@ -5832,7 +5832,7 @@ DRIVER_INIT_MEMBER(model3_state,scud) /* TODO: network device at 0xC0000000 - FF */ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64_delegate(FUNC(model3_state::scsi_r),this), write64_delegate(FUNC(model3_state::scsi_w),this)); -// UINT32 *rom = (UINT32*)memregion("user1")->base(); +// uint32_t *rom = (uint32_t*)memregion("user1")->base(); // rom[(0x799de8^4)/4] = 0x00050208; // secret debug menu } @@ -5859,7 +5859,7 @@ DRIVER_INIT_MEMBER(model3_state,lemans24) DRIVER_INIT_MEMBER(model3_state,vf3) { - //UINT32 *rom = (UINT32*)memregion("user1")->base(); + //uint32_t *rom = (uint32_t*)memregion("user1")->base(); DRIVER_INIT_CALL(model3_10); @@ -5891,7 +5891,7 @@ DRIVER_INIT_MEMBER(model3_state,vs29815) { m_step15_with_mpc106 = true; - UINT32 *rom = (UINT32*)memregion("user1")->base(); + uint32_t *rom = (uint32_t*)memregion("user1")->base(); rom[(0x6028ec^4)/4] = 0x60000000; rom[(0x60290c^4)/4] = 0x60000000; @@ -5972,7 +5972,7 @@ DRIVER_INIT_MEMBER(model3_state,srally2) DRIVER_INIT_CALL(model3_20); - UINT32 *rom = (UINT32*)memregion("user1")->base(); + uint32_t *rom = (uint32_t*)memregion("user1")->base(); rom[(0x7c0c4^4)/4] = 0x60000000; rom[(0x7c0c8^4)/4] = 0x60000000; rom[(0x7c0cc^4)/4] = 0x60000000; @@ -5984,7 +5984,7 @@ DRIVER_INIT_MEMBER(model3_state,srally2) DRIVER_INIT_MEMBER(model3_state,swtrilgy) { - UINT32 *rom = (UINT32*)memregion("user1")->base(); + uint32_t *rom = (uint32_t*)memregion("user1")->base(); DRIVER_INIT_CALL(model3_20); // Unemulated JTAG stuff, see srally2 @@ -6002,7 +6002,7 @@ DRIVER_INIT_MEMBER(model3_state,swtrilgy) DRIVER_INIT_MEMBER(model3_state,swtrilga) { - //UINT32 *rom = (UINT32*)memregion("user1")->base(); + //uint32_t *rom = (uint32_t*)memregion("user1")->base(); DRIVER_INIT_CALL(model3_20); DRIVER_INIT_CALL(genprot); @@ -6027,7 +6027,7 @@ DRIVER_INIT_MEMBER(model3_state,dirtdvls) DRIVER_INIT_MEMBER(model3_state,daytona2) { -// UINT32 *rom = (UINT32*)memregion("user1")->base(); +// uint32_t *rom = (uint32_t*)memregion("user1")->base(); DRIVER_INIT_CALL(model3_20); m_maincpu->space(AS_PROGRAM).install_write_handler(0xc3800000, 0xc3800007, write64_delegate(FUNC(model3_state::daytona2_rombank_w),this)); @@ -6043,7 +6043,7 @@ DRIVER_INIT_MEMBER(model3_state,daytona2) DRIVER_INIT_MEMBER(model3_state,dayto2pe) { -// UINT32 *rom = (UINT32*)memregion("user1")->base(); +// uint32_t *rom = (uint32_t*)memregion("user1")->base(); DRIVER_INIT_CALL(model3_20); m_maincpu->space(AS_PROGRAM).install_write_handler(0xc3800000, 0xc3800007, write64_delegate(FUNC(model3_state::daytona2_rombank_w),this)); @@ -6060,7 +6060,7 @@ DRIVER_INIT_MEMBER(model3_state,dayto2pe) DRIVER_INIT_MEMBER(model3_state,spikeout) { - UINT32 *rom = (UINT32*)memregion("user1")->base(); + uint32_t *rom = (uint32_t*)memregion("user1")->base(); DRIVER_INIT_CALL(model3_20); rom[(0x6059cc^4)/4] = 0x60000000; @@ -6070,7 +6070,7 @@ DRIVER_INIT_MEMBER(model3_state,spikeout) DRIVER_INIT_MEMBER(model3_state,spikeofe) { - UINT32 *rom = (UINT32*)memregion("user1")->base(); + uint32_t *rom = (uint32_t*)memregion("user1")->base(); DRIVER_INIT_CALL(model3_20); rom[(0x6059cc^4)/4] = 0x60000000; @@ -6084,7 +6084,7 @@ DRIVER_INIT_MEMBER(model3_state,eca) DRIVER_INIT_CALL(genprot); // base = 0xffc80000 - UINT32 *rom = (UINT32*)memregion("user1")->base(); + uint32_t *rom = (uint32_t*)memregion("user1")->base(); // cabinet network error rom[(0x4a45e4^4)/4] = 0x60000000; @@ -6096,7 +6096,7 @@ DRIVER_INIT_MEMBER(model3_state,eca) DRIVER_INIT_MEMBER(model3_state,skichamp) { - //UINT32 *rom = (UINT32*)memregion("user1")->base(); + //uint32_t *rom = (uint32_t*)memregion("user1")->base(); DRIVER_INIT_CALL(model3_20); /* @@ -6109,7 +6109,7 @@ DRIVER_INIT_MEMBER(model3_state,skichamp) DRIVER_INIT_MEMBER(model3_state,oceanhun) { - UINT32 *rom = (UINT32*)memregion("user1")->base(); + uint32_t *rom = (uint32_t*)memregion("user1")->base(); DRIVER_INIT_CALL(model3_20); rom[(0x57995c^4)/4] = 0x60000000; // decrementer |