diff options
author | 2016-10-22 13:13:17 +0200 | |
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committer | 2016-10-22 13:13:17 +0200 | |
commit | ddb290d5f615019c33c42b8d94e5a5254cabcf33 (patch) | |
tree | a70f688b0df3acd19da7b1151e5902e3c6af3fa5 /src/devices/cpu/arm/armdasm.cpp | |
parent | 333bff8de64dfaeb98134000412796b4fdef970b (diff) |
NOTICE (TYPE NAME CONSOLIDATION)
Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8
also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
Diffstat (limited to 'src/devices/cpu/arm/armdasm.cpp')
-rw-r--r-- | src/devices/cpu/arm/armdasm.cpp | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/devices/cpu/arm/armdasm.cpp b/src/devices/cpu/arm/armdasm.cpp index 83860b22aff..08a0b282afe 100644 --- a/src/devices/cpu/arm/armdasm.cpp +++ b/src/devices/cpu/arm/armdasm.cpp @@ -9,10 +9,10 @@ #include "emu.h" #include "arm.h" -static char *WriteImmediateOperand( char *pBuf, UINT32 opcode ) +static char *WriteImmediateOperand( char *pBuf, uint32_t opcode ) { /* rrrrbbbbbbbb */ - UINT32 imm; + uint32_t imm; int r; imm = opcode&0xff; @@ -22,7 +22,7 @@ static char *WriteImmediateOperand( char *pBuf, UINT32 opcode ) return pBuf; } -static char *WriteDataProcessingOperand( char *pBuf, UINT32 opcode, int printOp0, int printOp1, int printOp2 ) +static char *WriteDataProcessingOperand( char *pBuf, uint32_t opcode, int printOp0, int printOp1, int printOp2 ) { /* ccccctttmmmm */ static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" }; @@ -55,7 +55,7 @@ static char *WriteDataProcessingOperand( char *pBuf, UINT32 opcode, int printOp0 return pBuf; } -static char *WriteRegisterOperand1( char *pBuf, UINT32 opcode ) +static char *WriteRegisterOperand1( char *pBuf, uint32_t opcode ) { /* ccccctttmmmm */ static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" }; @@ -80,7 +80,7 @@ static char *WriteRegisterOperand1( char *pBuf, UINT32 opcode ) } /* WriteRegisterOperand */ -static char *WriteBranchAddress( char *pBuf, UINT32 pc, UINT32 opcode ) +static char *WriteBranchAddress( char *pBuf, uint32_t pc, uint32_t opcode ) { opcode &= 0x00ffffff; if( opcode&0x00800000 ) @@ -102,7 +102,7 @@ static char *WritePadding( char *pBuf, const char *pBuf0 ) return pBuf; } -static UINT32 arm_disasm( char *pBuf, UINT32 pc, UINT32 opcode ) +static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode ) { const char *pBuf0; @@ -121,7 +121,7 @@ static UINT32 arm_disasm( char *pBuf, UINT32 pc, UINT32 opcode ) "ORR","MOV","BIC","MVN" }; const char *pConditionCode; - UINT32 dasmflags = 0; + uint32_t dasmflags = 0; pConditionCode= pConditionCodeTable[opcode>>28]; pBuf0 = pBuf; @@ -397,12 +397,12 @@ static UINT32 arm_disasm( char *pBuf, UINT32 pc, UINT32 opcode ) CPU_DISASSEMBLE( arm ) { - UINT32 opcode = oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24); + uint32_t opcode = oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24); return 4 | arm_disasm(buffer, pc, opcode); } CPU_DISASSEMBLE( arm_be ) { - UINT32 opcode = oprom[3] | (oprom[2] << 8) | (oprom[1] << 16) | (oprom[0] << 24); + uint32_t opcode = oprom[3] | (oprom[2] << 8) | (oprom[1] << 16) | (oprom[0] << 24); return 4 | arm_disasm(buffer, pc, opcode); } |