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author couriersud <couriersud@gmx.org>2019-03-25 21:34:24 +0100
committer couriersud <couriersud@gmx.org>2019-03-25 21:45:37 +0100
commit39a7c420b1a956cfb680481077ed19f6315c6d37 (patch)
tree966378b573dcd8c08ac9e25000ef60c6dcb0ee39 /docs/source/conf.py
parenta105f9f456636c1de7396d5a79ad40c2237f6591 (diff)
netlist: add MOSFET model. [Couriersud]
- added MOSFET model. Currently capacitances are not modelled. This is a 3-pin model (Bulk connected to Source) with provisions to extend it to 4-pin at a later stage. - Add a capacitor generic model which is charge conserving. Switch netlist to use this model instead of constant capacity model. - Start putting constants into a central place. Please expect minor timing differences due to a different numerical path. The cmos inverter example illustrates the analog implementation of a cmos inverter gate. These were used a lot back in the 70s/80s to generate sinus waves. The model should also be able to better emulate 4066 analog switches. The addition of a relatively simple capacitor model is planned at a later stage. Expect everything from the MOSFET model at the current stage. Wrong results as well as convergence issues and crashes.
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