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author AJR <ajrhacker@users.noreply.github.com>2019-04-14 08:59:55 -0400
committer AJR <ajrhacker@users.noreply.github.com>2019-04-14 09:02:49 -0400
commitf23f57846ff9977d5e50881a852738a2e4fe362c (patch)
treedbc4352bba59db71fd3b4e27936aed987145c352
parent1320dd39101b261ffc0825d0abc04cd45f2fe71a (diff)
cdi070, cdicdic, cdislave, mcd212: Modernize interrupt handling (nw)
-rw-r--r--src/mame/drivers/cdi.cpp27
-rw-r--r--src/mame/includes/cdi.h1
-rw-r--r--src/mame/machine/cdi070.cpp438
-rw-r--r--src/mame/machine/cdi070.h35
-rw-r--r--src/mame/machine/cdicdic.cpp43
-rw-r--r--src/mame/machine/cdicdic.h7
-rw-r--r--src/mame/machine/cdislave.cpp21
-rw-r--r--src/mame/machine/cdislave.h6
-rw-r--r--src/mame/video/mcd212.cpp70
-rw-r--r--src/mame/video/mcd212.h8
10 files changed, 470 insertions, 186 deletions
diff --git a/src/mame/drivers/cdi.cpp b/src/mame/drivers/cdi.cpp
index 6df32896e33..9ac8f14e86f 100644
--- a/src/mame/drivers/cdi.cpp
+++ b/src/mame/drivers/cdi.cpp
@@ -144,6 +144,12 @@ void cdi_state::cdimono2_slave_mem(address_map &map)
map(0x0100, 0x1fff).rom().region("slave", 0x100);
}
+
+void cdi_state::cdi070_cpuspace(address_map &map)
+{
+ map(0xfffffff0, 0xffffffff).r(m_scc, FUNC(cdi68070_device::iack_r)).umask16(0x00ff);
+}
+
/*************************
* Input ports *
*************************/
@@ -752,9 +758,12 @@ void cdi_state::cdimono1_base(machine_config &config)
{
SCC68070(config, m_maincpu, CLOCK_A/2);
m_maincpu->set_addrmap(AS_PROGRAM, &cdi_state::cdimono1_mem);
+ m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &cdi_state::cdi070_cpuspace);
MCD212(config, m_mcd212, 0);
m_mcd212->set_screen("screen");
+ m_mcd212->int1_callback().set(m_scc, FUNC(cdi68070_device::int1_w));
+ m_mcd212->int2_callback().set(m_scc, FUNC(cdi68070_device::int2_w));
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
screen.set_refresh_hz(60);
@@ -775,9 +784,13 @@ void cdi_state::cdimono1_base(machine_config &config)
config.set_default_layout(layout_cdi);
CDI_68070(config, m_scc, 0, "maincpu");
+ m_scc->iack4_callback().set_constant(0x80);
CDI_CDIC(config, m_cdic, 0);
+ m_cdic->int_callback().set(m_scc, FUNC(cdi68070_device::in4_w));
+
CDI_SLAVE(config, m_slave_hle, 0);
+ m_slave_hle->int_callback().set(m_scc, FUNC(cdi68070_device::in2_w));
/* sound hardware */
SPEAKER(config, "lspeaker").front_left();
@@ -801,9 +814,12 @@ void cdi_state::cdimono2(machine_config &config)
{
SCC68070(config, m_maincpu, CLOCK_A/2);
m_maincpu->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_mem);
+ m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &cdi_state::cdi070_cpuspace);
MCD212(config, m_mcd212, 0);
m_mcd212->set_screen("screen");
+ m_mcd212->int1_callback().set(m_scc, FUNC(cdi68070_device::int1_w));
+ m_mcd212->int2_callback().set(m_scc, FUNC(cdi68070_device::int2_w));
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
screen.set_refresh_hz(60);
@@ -826,9 +842,9 @@ void cdi_state::cdimono2(machine_config &config)
MCFG_MACHINE_RESET_OVERRIDE( cdi_state, cdimono2 )
CDI_68070(config, m_scc, 0, "maincpu");
- M68HC05EG(config, m_servo, 2000000); /* Unknown clock speed, docs say 2MHz internal clock */
+ M68HC05EG(config, m_servo, XTAL(4'000'000));
m_servo->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_servo_mem);
- M68HC05EG(config, m_slave, 2000000); /* Unknown clock speed, docs say 2MHz internal clock */
+ M68HC05EG(config, m_slave, XTAL(4'000'000));
m_slave->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_slave_mem);
CDROM(config, "cdrom").set_interface("cdi_cdrom");
@@ -855,9 +871,12 @@ void cdi_state::cdi910(machine_config &config)
{
SCC68070(config, m_maincpu, CLOCK_A/2);
m_maincpu->set_addrmap(AS_PROGRAM, &cdi_state::cdi910_mem);
+ m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &cdi_state::cdi070_cpuspace);
MCD212(config, m_mcd212, 0);
m_mcd212->set_screen("screen");
+ m_mcd212->int1_callback().set(m_scc, FUNC(cdi68070_device::int1_w));
+ m_mcd212->int2_callback().set(m_scc, FUNC(cdi68070_device::int2_w));
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
screen.set_refresh_hz(60);
@@ -880,9 +899,9 @@ void cdi_state::cdi910(machine_config &config)
MCFG_MACHINE_RESET_OVERRIDE( cdi_state, cdimono2 )
CDI_68070(config, m_scc, 0, "maincpu");
- M68HC05EG(config, m_servo, 2000000); /* Unknown clock speed, docs say 2MHz internal clock */
+ M68HC05EG(config, m_servo, XTAL(4'000'000));
m_servo->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_servo_mem);
- M68HC05EG(config, m_slave, 2000000); /* Unknown clock speed, docs say 2MHz internal clock */
+ M68HC05EG(config, m_slave, XTAL(4'000'000));
m_slave->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_slave_mem);
CDROM(config, "cdrom").set_interface("cdi_cdrom");
diff --git a/src/mame/includes/cdi.h b/src/mame/includes/cdi.h
index 93aeb542e29..bce90f13ccc 100644
--- a/src/mame/includes/cdi.h
+++ b/src/mame/includes/cdi.h
@@ -134,6 +134,7 @@ public:
void cdimono2_mem(address_map &map);
void cdimono2_servo_mem(address_map &map);
void cdimono2_slave_mem(address_map &map);
+ void cdi070_cpuspace(address_map &map);
};
/*----------- debug defines -----------*/
diff --git a/src/mame/machine/cdi070.cpp b/src/mame/machine/cdi070.cpp
index 9387dcb2327..b2368a5d8bc 100644
--- a/src/mame/machine/cdi070.cpp
+++ b/src/mame/machine/cdi070.cpp
@@ -33,7 +33,7 @@ DEFINE_DEVICE_TYPE(CDI_68070, cdi68070_device, "cdi68070", "CDI68070")
#if ENABLE_VERBOSE_LOG
static inline void ATTR_PRINTF(3,4) verboselog(device_t& device, int n_level, const char *s_fmt, ...)
{
- if( VERBOSE_LEVEL >= n_level )
+ if ( VERBOSE_LEVEL >= n_level )
{
va_list v;
char buf[ 32768 ];
@@ -58,19 +58,57 @@ static inline void ATTR_PRINTF(3,4) verboselog(device_t& device, int n_level, co
cdi68070_device::cdi68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, CDI_68070, tag, owner, clock)
, m_maincpu(*this, finder_base::DUMMY_TAG)
+ , m_iack2_callback(*this)
+ , m_iack4_callback(*this)
+ , m_iack5_callback(*this)
+ , m_iack7_callback(*this)
+ , m_ipl(0)
+ , m_in2_line(CLEAR_LINE)
+ , m_in4_line(CLEAR_LINE)
+ , m_in5_line(CLEAR_LINE)
+ , m_nmi_line(CLEAR_LINE)
+ , m_int1_line(CLEAR_LINE)
+ , m_int2_line(CLEAR_LINE)
{
}
//-------------------------------------------------
+// device_resolve_objects - resolve objects that
+// may be needed for other devices to set
+// initial conditions at start time
+//-------------------------------------------------
+
+void cdi68070_device::device_resolve_objects()
+{
+ m_iack2_callback.resolve_safe(0x1a); // Level 2 external autovector
+ m_iack4_callback.resolve_safe(0x1c); // Level 4 external autovector
+ m_iack5_callback.resolve_safe(0x1d); // Level 5 external autovector
+ m_iack7_callback.resolve_safe(0x1f); // Level 7 external autovector
+}
+
+//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void cdi68070_device::device_start()
{
+ save_item(NAME(m_ipl));
+
+ save_item(NAME(m_in2_line));
+ save_item(NAME(m_in4_line));
+ save_item(NAME(m_in5_line));
+ save_item(NAME(m_nmi_line));
+
+ save_item(NAME(m_int1_line));
+ save_item(NAME(m_int2_line));
save_item(NAME(m_lir));
save_item(NAME(m_picr1));
save_item(NAME(m_picr2));
+ save_item(NAME(m_timer_int));
+ save_item(NAME(m_i2c_int));
+ save_item(NAME(m_uart_rx_int));
+ save_item(NAME(m_uart_tx_int));
save_item(NAME(m_i2c.data_register));
save_item(NAME(m_i2c.address_register));
@@ -166,6 +204,10 @@ void cdi68070_device::device_reset()
m_picr1 = 0;
m_picr2 = 0;
+ m_timer_int = false;
+ m_i2c_int = false;
+ m_uart_rx_int = false;
+ m_uart_tx_int = false;
m_i2c.data_register = 0;
m_i2c.address_register = 0;
@@ -216,11 +258,154 @@ void cdi68070_device::device_reset()
memset(m_state, 0, 8 * sizeof(uint8_t));
m_mcu_value = 0;
m_mcu_ack = 0;
+
+ update_ipl();
+}
+
+void cdi68070_device::update_ipl()
+{
+ const uint8_t external_level = (m_nmi_line == ASSERT_LINE) ? 7
+ : (m_in5_line == ASSERT_LINE) ? 5
+ : (m_in4_line == ASSERT_LINE) ? 4
+ : (m_in2_line == ASSERT_LINE) ? 2 : 0;
+ const uint8_t int1_level = BIT(m_lir, 7) ? (m_lir >> 4) & 7 : 0;
+ const uint8_t int2_level = BIT(m_lir, 3) ? m_lir & 7 : 0;
+ const uint8_t timer_level = m_timer_int ? m_picr1 & 7 : 0;
+ const uint8_t uart_rx_level = m_uart_rx_int ? (m_picr2 >> 4) & 7 : 0;
+ const uint8_t uart_tx_level = m_uart_tx_int ? m_picr2 & 7 : 0;
+ const uint8_t i2c_level = m_i2c_int ? (m_picr1 >> 4) & 7 : 0;
+ const uint8_t dma_ch1_level = (m_dma.channel[0].channel_status & CSR_COC) && (m_dma.channel[0].channel_control & CCR_INE) ? m_dma.channel[0].channel_control & CCR_IPL : 0;
+ const uint8_t dma_ch2_level = (m_dma.channel[1].channel_status & CSR_COC) && (m_dma.channel[1].channel_control & CCR_INE) ? m_dma.channel[1].channel_control & CCR_IPL : 0;
+
+ const uint8_t new_ipl = std::max({external_level, int1_level, int2_level, timer_level, uart_rx_level, uart_tx_level, i2c_level, dma_ch1_level, dma_ch2_level});
+
+ if (m_ipl != new_ipl)
+ {
+ if (m_ipl != 0)
+ m_maincpu->set_input_line(m_ipl, CLEAR_LINE);
+ if (new_ipl != 0)
+ m_maincpu->set_input_line(new_ipl, ASSERT_LINE);
+ m_ipl = new_ipl;
+ }
+}
+
+WRITE_LINE_MEMBER(cdi68070_device::in2_w)
+{
+ m_in2_line = state;
+ update_ipl();
+}
+
+WRITE_LINE_MEMBER(cdi68070_device::in4_w)
+{
+ m_in4_line = state;
+ update_ipl();
+}
+
+WRITE_LINE_MEMBER(cdi68070_device::in5_w)
+{
+ m_in5_line = state;
+ update_ipl();
+}
+
+WRITE_LINE_MEMBER(cdi68070_device::nmi_w)
+{
+ m_nmi_line = state;
+ update_ipl();
+}
+
+WRITE_LINE_MEMBER(cdi68070_device::int1_w)
+{
+ if (m_int1_line != state)
+ {
+ if (state == ASSERT_LINE && !BIT(m_lir, 7))
+ {
+ m_lir |= 0x80;
+ update_ipl();
+ }
+
+ m_int1_line = state;
+ }
+}
+
+WRITE_LINE_MEMBER(cdi68070_device::int2_w)
+{
+ if (m_int2_line != state)
+ {
+ if (state == ASSERT_LINE && !BIT(m_lir, 3))
+ {
+ m_lir |= 0x08;
+ update_ipl();
+ }
+
+ m_int1_line = state;
+ }
+}
+
+uint8_t cdi68070_device::iack_r(offs_t offset)
+{
+ switch (offset)
+ {
+ case 2:
+ if (m_in2_line == ASSERT_LINE)
+ return m_iack2_callback();
+ break;
+
+ case 4:
+ if (m_in4_line == ASSERT_LINE)
+ return m_iack4_callback();
+ break;
+
+ case 5:
+ if (m_in5_line == ASSERT_LINE)
+ return m_iack5_callback();
+ break;
+
+ case 7:
+ if (m_nmi_line == ASSERT_LINE)
+ return m_iack7_callback();
+ break;
+ }
+
+ if (!machine().side_effects_disabled())
+ {
+ if (BIT(m_lir, 7) && offset == ((m_lir >> 4) & 7))
+ {
+ m_lir &= 0x7f;
+ update_ipl();
+ }
+ else if (BIT(m_lir, 3) && offset == (m_lir & 7))
+ {
+ m_lir &= 0xf7;
+ update_ipl();
+ }
+ else if (m_timer_int && offset == (m_picr1 & 7))
+ {
+ m_timer_int = false;
+ update_ipl();
+ }
+ else if (m_uart_rx_int && offset == ((m_picr2 >> 4) & 7))
+ {
+ m_uart_rx_int = false;
+ update_ipl();
+ }
+ else if (m_uart_tx_int && offset == (m_picr2 & 7))
+ {
+ m_uart_tx_int = false;
+ update_ipl();
+ }
+ else if (m_i2c_int && offset == ((m_picr2 >> 4) & 7))
+ {
+ m_i2c_int = false;
+ update_ipl();
+ }
+ }
+
+ return 0x38 + offset;
}
void cdi68070_device::set_timer_callback(int channel)
{
- switch(channel)
+ switch (channel)
{
case 0:
{
@@ -250,15 +435,10 @@ TIMER_CALLBACK_MEMBER( cdi68070_device::timer0_callback )
{
m_timers.timer0 = m_timers.reload_register;
m_timers.timer_status_register |= TSR_OV0;
- if(m_picr1 & 7)
+ if (!m_timer_int)
{
- uint8_t interrupt = m_picr1 & 7;
- m_timers.timer_status_register |= TSR_OV0;
- if(interrupt)
- {
- m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
- m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
- }
+ m_timer_int = true;
+ update_ipl();
}
set_timer_callback(0);
@@ -266,7 +446,7 @@ TIMER_CALLBACK_MEMBER( cdi68070_device::timer0_callback )
void cdi68070_device::uart_rx_check()
{
- if((m_uart.command_register & 3) == 1)
+ if ((m_uart.command_register & 3) == 1)
{
uint32_t div = 0x10000 >> ((m_uart.clock_select >> 4) & 7);
m_uart.rx_timer->adjust(attotime::from_hz((49152000 / div) / 8));
@@ -280,9 +460,9 @@ void cdi68070_device::uart_rx_check()
void cdi68070_device::uart_tx_check()
{
- if(((m_uart.command_register >> 2) & 3) == 1)
+ if (((m_uart.command_register >> 2) & 3) == 1)
{
- if(m_uart.transmit_pointer >= 0)
+ if (m_uart.transmit_pointer >= 0)
{
m_uart.status_register &= ~USR_TXRDY;
}
@@ -291,7 +471,7 @@ void cdi68070_device::uart_tx_check()
m_uart.status_register |= USR_TXRDY;
}
- if(m_uart.tx_timer->remaining() == attotime::never)
+ if (m_uart.tx_timer->remaining() == attotime::never)
{
uint32_t div = 0x10000 >> (m_uart.clock_select & 7);
m_uart.tx_timer->adjust(attotime::from_hz((49152000 / div) / 8));
@@ -319,9 +499,9 @@ void cdi68070_device::uart_tx(uint8_t data)
TIMER_CALLBACK_MEMBER( cdi68070_device::rx_callback )
{
- if((m_uart.command_register & 3) == 1)
+ if ((m_uart.command_register & 3) == 1)
{
- if(m_uart.receive_pointer >= 0)
+ if (m_uart.receive_pointer >= 0)
{
m_uart.status_register |= USR_RXRDY;
}
@@ -332,16 +512,12 @@ TIMER_CALLBACK_MEMBER( cdi68070_device::rx_callback )
m_uart.receive_holding_register = m_uart.receive_buffer[0];
- if(m_uart.receive_pointer > -1)
+ if (m_uart.receive_pointer > -1)
{
verboselog(*this, 2, "scc68070_rx_callback: Receiving %02x\n", m_uart.receive_holding_register);
- uint8_t interrupt = (m_picr2 >> 4) & 7;
- if(interrupt)
- {
- m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
- m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
- }
+ m_uart_rx_int = true;
+ update_ipl();
m_uart.status_register |= USR_RXRDY;
uint32_t div = 0x10000 >> ((m_uart.clock_select >> 4) & 7);
@@ -391,11 +567,11 @@ void cdi68070_device::quizard_calculate_state()
for(int index = 0; index < 10; index++)
{
- if(field0 & (1 << index))
+ if (field0 & (1 << index))
{
total0 += m_seeds[index];
}
- if(field1 & (1 << index))
+ if (field1 & (1 << index))
{
total1 += m_seeds[index];
}
@@ -420,7 +596,7 @@ void cdi68070_device::quizard_calculate_state()
void cdi68070_device::mcu_frame()
{
- if(0)//mcu_active)
+ if (0)//mcu_active)
{
quizard_calculate_state();
uart_rx(0x5a);
@@ -438,17 +614,17 @@ void cdi68070_device::quizard_handle_byte_tx()
static uint8_t rx_ptr = 0xff;
uint8_t tx = m_uart.transmit_holding_register;
- switch(state)
+ switch (state)
{
case 0: // Waiting for a leadoff byte
- if(tx == m_mcu_ack) // Sequence end
+ if (tx == m_mcu_ack) // Sequence end
{
//scc68070_uart_rx(machine, scc68070, 0x5a);
//scc68070_uart_rx(machine, scc68070, 0x42);
}
else
{
- switch(tx)
+ switch (tx)
{
case 0x44: // DATABASEPATH = **_DATABASE/
rx[0] = 0x44;
@@ -471,7 +647,7 @@ void cdi68070_device::quizard_handle_byte_tx()
case 1: // Receiving the seed
rx[rx_ptr] = tx;
rx_ptr++;
- if(rx_ptr == 20)
+ if (rx_ptr == 20)
{
//printf("Calculating seeds\n");
quizard_set_seeds(rx);
@@ -482,9 +658,9 @@ void cdi68070_device::quizard_handle_byte_tx()
case 2: // Receiving the seed acknowledge
case 4:
- if(tx == m_mcu_ack)
+ if (tx == m_mcu_ack)
{
- if(state == 2)
+ if (state == 2)
{
state = 4;
}
@@ -508,7 +684,7 @@ void cdi68070_device::quizard_handle_byte_tx()
case 3: // Receiving the database path
rx[rx_ptr] = tx;
rx_ptr++;
- if(tx == 0x0a)
+ if (tx == 0x0a)
{
/*rx[rx_ptr] = 0;
//printf("Database path: %s\n", rx);
@@ -529,16 +705,12 @@ void cdi68070_device::quizard_handle_byte_tx()
TIMER_CALLBACK_MEMBER( cdi68070_device::tx_callback )
{
- if(((m_uart.command_register >> 2) & 3) == 1)
+ if (((m_uart.command_register >> 2) & 3) == 1)
{
- uint8_t interrupt = m_picr2 & 7;
- if(interrupt)
- {
- m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
- m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
- }
+ m_uart_tx_int = true;
+ update_ipl();
- if(m_uart.transmit_pointer > -1)
+ if (m_uart.transmit_pointer > -1)
{
m_uart.transmit_holding_register = m_uart.transmit_buffer[0];
quizard_handle_byte_tx();
@@ -568,7 +740,7 @@ TIMER_CALLBACK_MEMBER( cdi68070_device::tx_callback )
READ16_MEMBER( cdi68070_device::periphs_r )
{
- switch(offset)
+ switch (offset)
{
// Interrupts: 80001001
case 0x1000/2: // LIR priority level
@@ -576,31 +748,31 @@ READ16_MEMBER( cdi68070_device::periphs_r )
// I2C interface: 80002001 to 80002009
case 0x2000/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: I2C Data Register: %04x & %04x\n", m_i2c.data_register, mem_mask);
}
return m_i2c.data_register;
case 0x2002/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: I2C Address Register: %04x & %04x\n", m_i2c.address_register, mem_mask);
}
return m_i2c.address_register;
case 0x2004/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: I2C Status Register: %04x & %04x\n", m_i2c.status_register, mem_mask);
}
return m_i2c.status_register;
case 0x2006/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: I2C Control Register: %04x & %04x\n", m_i2c.control_register, mem_mask);
}
return m_i2c.control_register;
case 0x2008/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: I2C Clock Control Register: %04x & %04x\n", m_i2c.clock_control_register, mem_mask);
}
@@ -608,7 +780,7 @@ READ16_MEMBER( cdi68070_device::periphs_r )
// UART interface: 80002011 to 8000201b
case 0x2010/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: UART Mode Register: %04x & %04x\n", m_uart.mode_register, mem_mask);
}
@@ -619,7 +791,7 @@ READ16_MEMBER( cdi68070_device::periphs_r )
return m_uart.mode_register | 0x20;
case 0x2012/2:
m_uart.status_register |= (1 << 1);
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: UART Status Register: %04x & %04x\n", m_uart.status_register, mem_mask);
}
@@ -628,20 +800,10 @@ READ16_MEMBER( cdi68070_device::periphs_r )
verboselog(*this, 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
}
- if((m_picr2 >> 4) & 7)
- {
- m_maincpu->set_input_line(M68K_IRQ_1 + (((m_picr2 >> 4) & 7) - 1), ASSERT_LINE);
- }
-
- if(m_picr2 & 7)
- {
- m_maincpu->set_input_line(M68K_IRQ_1 + ((m_picr2 & 7) - 1), ASSERT_LINE);
- }
-
return m_uart.status_register;
case 0x2014/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: UART Clock Select: %04x & %04x\n", m_uart.clock_select, mem_mask);
}
@@ -651,7 +813,7 @@ READ16_MEMBER( cdi68070_device::periphs_r )
}
return m_uart.clock_select | 0x08;
case 0x2016/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: UART Command Register: %02x & %04x\n", m_uart.command_register, mem_mask);
}
@@ -661,7 +823,7 @@ READ16_MEMBER( cdi68070_device::periphs_r )
}
return m_uart.command_register | 0x80;
case 0x2018/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: UART Transmit Holding Register: %02x & %04x\n", m_uart.transmit_holding_register, mem_mask);
}
@@ -671,7 +833,7 @@ READ16_MEMBER( cdi68070_device::periphs_r )
}
return m_uart.transmit_holding_register;
case 0x201a/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: UART Receive Holding Register: %02x & %04x\n", m_uart.receive_holding_register, mem_mask);
}
@@ -679,13 +841,14 @@ READ16_MEMBER( cdi68070_device::periphs_r )
{
verboselog(*this, 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask);
}
- if((m_picr2 >> 4) & 7)
+ if (m_uart_rx_int)
{
- m_maincpu->set_input_line(M68K_IRQ_1 + (((m_picr2 >> 4) & 7) - 1), CLEAR_LINE);
+ m_uart_rx_int = false;
+ update_ipl();
}
m_uart.receive_holding_register = m_uart.receive_buffer[0];
- if(m_uart.receive_pointer >= 0)
+ if (m_uart.receive_pointer >= 0)
{
for(int index = 0; index < m_uart.receive_pointer; index++)
{
@@ -698,11 +861,11 @@ READ16_MEMBER( cdi68070_device::periphs_r )
// Timers: 80002020 to 80002029
case 0x2020/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: Timer Control Register: %02x & %04x\n", m_timers.timer_control_register, mem_mask);
}
- if(ACCESSING_BITS_8_15)
+ if (ACCESSING_BITS_8_15)
{
verboselog(*this, 12, "cdi68070_periphs_r: Timer Status Register: %02x & %04x\n", m_timers.timer_status_register, mem_mask);
}
@@ -722,15 +885,15 @@ READ16_MEMBER( cdi68070_device::periphs_r )
// PICR1: 80002045
case 0x2044/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: Peripheral Interrupt Control Register 1: %02x & %04x\n", m_picr1, mem_mask);
}
- return m_picr1;
+ return m_picr1 & 0x77;
// PICR2: 80002047
case 0x2046/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: Peripheral Interrupt Control Register 2: %02x & %04x\n", m_picr2, mem_mask);
}
@@ -739,33 +902,33 @@ READ16_MEMBER( cdi68070_device::periphs_r )
// DMA controller: 80004000 to 8000406d
case 0x4000/2:
case 0x4040/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Error Register: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_error, mem_mask);
}
- if(ACCESSING_BITS_8_15)
+ if (ACCESSING_BITS_8_15)
{
verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Status Register: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_status, mem_mask);
}
return (m_dma.channel[(offset - 0x2000) / 32].channel_status << 8) | m_dma.channel[(offset - 0x2000) / 32].channel_error;
case 0x4004/2:
case 0x4044/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Operation Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].operation_control, mem_mask);
}
- if(ACCESSING_BITS_8_15)
+ if (ACCESSING_BITS_8_15)
{
verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Device Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_control, mem_mask);
}
return (m_dma.channel[(offset - 0x2000) / 32].device_control << 8) | m_dma.channel[(offset - 0x2000) / 32].operation_control;
case 0x4006/2:
case 0x4046/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Channel Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_control, mem_mask);
}
- if(ACCESSING_BITS_8_15)
+ if (ACCESSING_BITS_8_15)
{
verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Sequence Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].sequence_control, mem_mask);
}
@@ -792,7 +955,7 @@ READ16_MEMBER( cdi68070_device::periphs_r )
// MMU: 80008000 to 8000807f
case 0x8000/2: // Status / Control register
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{ // Control
verboselog(*this, 2, "cdi68070_periphs_r: MMU Control: %02x & %04x\n", m_mmu.control, mem_mask);
return m_mmu.control;
@@ -830,7 +993,7 @@ READ16_MEMBER( cdi68070_device::periphs_r )
case 0x806c/2:
case 0x8074/2:
case 0x807c/2: // Segment Number (SD0-7, A0=1 only)
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_r: MMU descriptor %d segment: %02x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].segment, mem_mask);
return m_mmu.desc[(offset - 0x4020) / 4].segment;
@@ -856,7 +1019,7 @@ READ16_MEMBER( cdi68070_device::periphs_r )
WRITE16_MEMBER( cdi68070_device::periphs_w )
{
- switch(offset)
+ switch (offset)
{
// Interrupts: 80001001
case 0x1000/2: // LIR priority level
@@ -866,35 +1029,35 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
// I2C interface: 80002001 to 80002009
case 0x2000/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: I2C Data Register: %04x & %04x\n", data, mem_mask);
m_i2c.data_register = data & 0x00ff;
}
break;
case 0x2002/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: I2C Address Register: %04x & %04x\n", data, mem_mask);
m_i2c.address_register = data & 0x00ff;
}
break;
case 0x2004/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: I2C Status Register: %04x & %04x\n", data, mem_mask);
m_i2c.status_register = data & 0x00ff;
}
break;
case 0x2006/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: I2C Control Register: %04x & %04x\n", data, mem_mask);
m_i2c.control_register = data & 0x00ff;
}
break;
case 0x2008/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: I2C Clock Control Register: %04x & %04x\n", data, mem_mask);
m_i2c.clock_control_register = data & 0x00ff;
@@ -903,7 +1066,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
// UART interface: 80002011 to 8000201b
case 0x2010/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: UART Mode Register: %04x & %04x\n", data, mem_mask);
m_uart.mode_register = data & 0x00ff;
@@ -914,7 +1077,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
}
break;
case 0x2012/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: UART Status Register: %04x & %04x\n", data, mem_mask);
m_uart.status_register = data & 0x00ff;
@@ -925,7 +1088,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
}
break;
case 0x2014/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: UART Clock Select: %04x & %04x\n", data, mem_mask);
m_uart.clock_select = data & 0x00ff;
@@ -936,7 +1099,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
}
break;
case 0x2016/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: UART Command Register: %04x & %04x\n", data, mem_mask);
m_uart.command_register = data & 0x00ff;
@@ -949,7 +1112,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
}
break;
case 0x2018/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: UART Transmit Holding Register: %04x & %04x: %c\n", data, mem_mask, (data >= 0x20 && data < 0x7f) ? (data & 0x00ff) : ' ');
uart_tx(data & 0x00ff);
@@ -961,7 +1124,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
}
break;
case 0x201a/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: UART Receive Holding Register: %04x & %04x\n", data, mem_mask);
m_uart.receive_holding_register = data & 0x00ff;
@@ -974,20 +1137,15 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
// Timers: 80002020 to 80002029
case 0x2020/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: Timer Control Register: %04x & %04x\n", data, mem_mask);
m_timers.timer_control_register = data & 0x00ff;
}
- if(ACCESSING_BITS_8_15)
+ if (ACCESSING_BITS_8_15)
{
verboselog(*this, 12, "cdi68070_periphs_w: Timer Status Register: %04x & %04x\n", data, mem_mask);
m_timers.timer_status_register &= ~(data >> 8);
- if(!m_timers.timer_status_register)
- {
- uint8_t interrupt = m_picr1 & 7;
- m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), CLEAR_LINE);
- }
}
break;
case 0x2022/2:
@@ -1010,43 +1168,98 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
// PICR1: 80002045
case 0x2044/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: Peripheral Interrupt Control Register 1: %04x & %04x\n", data, mem_mask);
- m_picr1 = data & 0x00ff;
+ m_picr1 = data & 0x0077;
+ switch (data & 0x0088)
+ {
+ case 0x08:
+ if (m_timer_int)
+ {
+ m_timer_int = false;
+ update_ipl();
+ }
+ break;
+
+ case 0x80:
+ if (m_i2c_int)
+ {
+ m_i2c_int = false;
+ update_ipl();
+ }
+ break;
+
+ case 0x88:
+ if (m_timer_int || m_i2c_int)
+ {
+ m_timer_int = false;
+ m_i2c_int = false;
+ update_ipl();
+ }
+ break;
+ }
}
break;
// PICR2: 80002047
case 0x2046/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: Peripheral Interrupt Control Register 2: %04x & %04x\n", data, mem_mask);
- m_picr2 = data & 0x00ff;
+ m_picr2 = data & 0x0077;
+ switch (data & 0x0088)
+ {
+ case 0x08:
+ if (m_uart_tx_int)
+ {
+ m_uart_tx_int = false;
+ update_ipl();
+ }
+ break;
+
+ case 0x80:
+ if (m_uart_rx_int)
+ {
+ m_uart_rx_int = false;
+ update_ipl();
+ }
+ break;
+
+ case 0x88:
+ if (m_uart_tx_int || m_uart_rx_int)
+ {
+ m_uart_tx_int = false;
+ m_uart_rx_int = false;
+ update_ipl();
+ }
+ break;
+ }
}
break;
// DMA controller: 80004000 to 8000406d
case 0x4000/2:
case 0x4040/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Error (invalid): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
}
- if(ACCESSING_BITS_8_15)
+ if (ACCESSING_BITS_8_15)
{
verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Status: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
- m_dma.channel[(offset - 0x2000) / 32].channel_status &= ~(data & 0xb0);
+ m_dma.channel[(offset - 0x2000) / 32].channel_status &= ~((data >> 8) & 0xb0);
+ update_ipl();
}
break;
case 0x4004/2:
case 0x4044/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Operation Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].operation_control = data & 0x00ff;
}
- if(ACCESSING_BITS_8_15)
+ if (ACCESSING_BITS_8_15)
{
verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Device Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].device_control = data >> 8;
@@ -1054,16 +1267,17 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
break;
case 0x4006/2:
case 0x4046/2:
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Channel Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].channel_control = data & 0x007f;
- if(data & CCR_SO)
+ if (data & CCR_SO)
{
m_dma.channel[(offset - 0x2000) / 32].channel_status |= CSR_COC;
}
+ update_ipl();
}
- if(ACCESSING_BITS_8_15)
+ if (ACCESSING_BITS_8_15)
{
verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Sequence Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask);
m_dma.channel[(offset - 0x2000) / 32].sequence_control = data >> 8;
@@ -1100,7 +1314,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
// MMU: 80008000 to 8000807f
case 0x8000/2: // Status / Control register
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{ // Control
verboselog(*this, 2, "cdi68070_periphs_w: MMU Control: %04x & %04x\n", data, mem_mask);
m_mmu.control = data & 0x00ff;
@@ -1140,7 +1354,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w )
case 0x806c/2:
case 0x8074/2:
case 0x807c/2: // Segment Number (SD0-7, A0=1 only)
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
verboselog(*this, 2, "cdi68070_periphs_w: MMU descriptor %d segment: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask);
m_mmu.desc[(offset - 0x4020) / 4].segment = data & 0x00ff;
diff --git a/src/mame/machine/cdi070.h b/src/mame/machine/cdi070.h
index 56ac7c1751a..1f63cca4452 100644
--- a/src/mame/machine/cdi070.h
+++ b/src/mame/machine/cdi070.h
@@ -142,6 +142,18 @@ public:
cdi68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ auto iack2_callback() { return m_iack2_callback.bind(); }
+ auto iack4_callback() { return m_iack4_callback.bind(); }
+ auto iack5_callback() { return m_iack5_callback.bind(); }
+ auto iack7_callback() { return m_iack7_callback.bind(); }
+
+ DECLARE_WRITE_LINE_MEMBER(in2_w);
+ DECLARE_WRITE_LINE_MEMBER(in4_w);
+ DECLARE_WRITE_LINE_MEMBER(in5_w);
+ DECLARE_WRITE_LINE_MEMBER(nmi_w);
+ DECLARE_WRITE_LINE_MEMBER(int1_w);
+ DECLARE_WRITE_LINE_MEMBER(int2_w);
+
// external callbacks
void uart_rx(uint8_t data);
void uart_tx(uint8_t data);
@@ -261,20 +273,29 @@ public:
dma_regs_t& dma() { return m_dma; }
- uint16_t get_lir() { return m_lir; }
+ uint8_t iack_r(offs_t offset);
protected:
// device-level overrides
+ virtual void device_resolve_objects() override;
virtual void device_start() override;
virtual void device_reset() override;
private:
required_device<cpu_device> m_maincpu;
+ void update_ipl();
+
void uart_rx_check();
void uart_tx_check();
void set_timer_callback(int channel);
+ // callbacks
+ devcb_read8 m_iack2_callback;
+ devcb_read8 m_iack4_callback;
+ devcb_read8 m_iack5_callback;
+ devcb_read8 m_iack7_callback;
+
// internal state
uint16_t m_seeds[10];
uint8_t m_state[8];
@@ -282,9 +303,21 @@ private:
uint16_t m_mcu_value;
uint8_t m_mcu_ack;
+ uint8_t m_ipl;
+ int m_in2_line;
+ int m_in4_line;
+ int m_in5_line;
+ int m_nmi_line;
+ int m_int1_line;
+ int m_int2_line;
+
uint16_t m_lir;
uint8_t m_picr1;
uint8_t m_picr2;
+ bool m_timer_int;
+ bool m_i2c_int;
+ bool m_uart_rx_int;
+ bool m_uart_tx_int;
i2c_regs_t m_i2c;
uart_regs_t m_uart;
diff --git a/src/mame/machine/cdicdic.cpp b/src/mame/machine/cdicdic.cpp
index 4b371e8f78a..6e13ef53dec 100644
--- a/src/mame/machine/cdicdic.cpp
+++ b/src/mame/machine/cdicdic.cpp
@@ -560,8 +560,7 @@ void cdicdic_device::sample_trigger()
// Set the CDIC interrupt line
verboselog(*this, 0, "%s", "Setting CDIC interrupt line for soundmap decode\n" );
- m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
- m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
+ m_int_callback(ASSERT_LINE);
}
else
{
@@ -713,8 +712,7 @@ void cdicdic_device::process_delayed_command()
//printf( "Setting CDIC interrupt line\n" );
verboselog(*this, 0, "%s", "Setting CDIC interrupt line for audio sector\n" );
- m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
- m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
+ m_int_callback(ASSERT_LINE);
}
else if((buffer[CDIC_SECTOR_SUBMODE2] & (CDIC_SUBMODE_DATA | CDIC_SUBMODE_AUDIO | CDIC_SUBMODE_VIDEO)) == 0x00)
{
@@ -732,8 +730,7 @@ void cdicdic_device::process_delayed_command()
{
//printf( "Setting CDIC interrupt line\n" );
verboselog(*this, 0, "%s", "Setting CDIC interrupt line for message sector\n" );
- m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
- m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
+ m_int_callback(ASSERT_LINE);
}
else
{
@@ -752,8 +749,7 @@ void cdicdic_device::process_delayed_command()
//printf( "Setting CDIC interrupt line\n" );
verboselog(*this, 0, "%s", "Setting CDIC interrupt line for data sector\n" );
- m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
- m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
+ m_int_callback(ASSERT_LINE);
}
if((buffer[CDIC_SECTOR_SUBMODE2] & CDIC_SUBMODE_EOF) == 0 && m_command != 0x23)
@@ -847,8 +843,7 @@ void cdicdic_device::process_delayed_command()
}
verboselog(*this, 0, "%s", "Setting CDIC interrupt line for CDDA sector\n" );
- m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
- m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
+ m_int_callback(ASSERT_LINE);
break;
}
case 0x2c: // Seek
@@ -898,8 +893,7 @@ void cdicdic_device::process_delayed_command()
m_time = next_msf << 8;
verboselog(*this, 0, "%s", "Setting CDIC interrupt line for Seek sector\n" );
- m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
- m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
+ m_int_callback(ASSERT_LINE);
break;
}
}
@@ -945,7 +939,7 @@ READ16_MEMBER( cdicdic_device::regs_r )
m_audio_buffer &= 0x7fff;
if(!((m_audio_buffer | m_x_buffer) & 0x8000))
{
- m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
+ m_int_callback(CLEAR_LINE);
verboselog(*this, 0, "%s", "Clearing CDIC interrupt line\n" );
////printf("Clearing CDIC interrupt line\n" );
}
@@ -959,7 +953,7 @@ READ16_MEMBER( cdicdic_device::regs_r )
m_x_buffer &= 0x7fff;
if(!((m_audio_buffer | m_x_buffer) & 0x8000))
{
- m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
+ m_int_callback(CLEAR_LINE);
verboselog(*this, 0, "%s", "Clearing CDIC interrupt line\n" );
////printf("Clearing CDIC interrupt line\n" );
}
@@ -1049,7 +1043,6 @@ WRITE16_MEMBER( cdicdic_device::regs_w )
uint32_t count = m_scc->dma().channel[0].transfer_counter;
uint32_t index = 0;
uint32_t device_index = (data & 0x3fff) >> 1;
- address_space &memory_space = m_maincpu->space(AS_PROGRAM);
verboselog(*this, 0, "memory address counter: %08x\n", m_scc->dma().channel[0].memory_address_counter);
verboselog(*this, 0, "cdic_w: DMA Control Register = %04x & %04x\n", data, mem_mask);
verboselog(*this, 0, "Doing copy, transferring %04x bytes\n", count * 2 );
@@ -1058,11 +1051,11 @@ WRITE16_MEMBER( cdicdic_device::regs_w )
{
if(m_scc->dma().channel[0].operation_control & OCR_D)
{
- memory_space.write_word(index * 2, m_ram[device_index++]);
+ m_memory_space->write_word(index * 2, m_ram[device_index++]);
}
else
{
- m_ram[device_index++] = memory_space.read_word(index * 2);
+ m_ram[device_index++] = m_memory_space->read_word(index * 2);
}
}
m_scc->dma().channel[0].memory_address_counter += m_scc->dma().channel[0].transfer_counter * 2;
@@ -1159,7 +1152,8 @@ WRITE16_MEMBER( cdicdic_device::regs_w )
cdicdic_device::cdicdic_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, CDI_CDIC, tag, owner, clock)
- , m_maincpu(*this, ":maincpu")
+ , m_int_callback(*this)
+ , m_memory_space(*this, ":maincpu", AS_PROGRAM)
, m_dmadac(*this, ":dac%u", 1U)
, m_scc(*this, ":scc68070")
, m_cdda(*this, ":cdda")
@@ -1168,6 +1162,17 @@ cdicdic_device::cdicdic_device(const machine_config &mconfig, const char *tag, d
}
//-------------------------------------------------
+// device_resolve_objects - resolve objects that
+// may be needed for other devices to set
+// initial conditions at start time
+//-------------------------------------------------
+
+void cdicdic_device::device_resolve_objects()
+{
+ m_int_callback.resolve_safe();
+}
+
+//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
@@ -1233,6 +1238,8 @@ void cdicdic_device::device_reset()
m_cd = cdrom_open(machine().rom_load().get_disk_handle(":cdrom"));
m_cdda->set_cdrom(m_cd);
}
+
+ m_int_callback(CLEAR_LINE);
}
WRITE16_MEMBER( cdicdic_device::ram_w )
diff --git a/src/mame/machine/cdicdic.h b/src/mame/machine/cdicdic.h
index 745f8bcbcec..e16bdf5150a 100644
--- a/src/mame/machine/cdicdic.h
+++ b/src/mame/machine/cdicdic.h
@@ -45,6 +45,8 @@ public:
// construction/destruction
cdicdic_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ auto int_callback() { return m_int_callback.bind(); }
+
// non-static internal members
void sample_trigger();
void process_delayed_command();
@@ -57,6 +59,7 @@ public:
protected:
// device-level overrides
+ virtual void device_resolve_objects() override;
virtual void device_start() override;
virtual void device_reset() override;
@@ -65,7 +68,9 @@ protected:
TIMER_CALLBACK_MEMBER( trigger_readback_int );
private:
- required_device<cpu_device> m_maincpu;
+ devcb_write_line m_int_callback;
+
+ required_address_space m_memory_space;
required_device_array<dmadac_sound_device, 2> m_dmadac;
required_device<cdi68070_device> m_scc;
required_device<cdda_device> m_cdda;
diff --git a/src/mame/machine/cdislave.cpp b/src/mame/machine/cdislave.cpp
index aac788e34e4..fca7fd059be 100644
--- a/src/mame/machine/cdislave.cpp
+++ b/src/mame/machine/cdislave.cpp
@@ -57,8 +57,7 @@ static inline void ATTR_PRINTF(3,4) verboselog(device_t& device, int n_level, co
TIMER_CALLBACK_MEMBER( cdislave_device::trigger_readback_int )
{
verboselog(*this, 0, "%s", "Asserting IRQ2\n" );
- m_maincpu->set_input_line_vector(M68K_IRQ_2, 26);
- m_maincpu->set_input_line(M68K_IRQ_2, ASSERT_LINE);
+ m_int_callback(ASSERT_LINE);
m_interrupt_timer->adjust(attotime::never);
}
@@ -155,8 +154,7 @@ READ16_MEMBER( cdislave_device::slave_r )
case 0xf4:
case 0xf7:
verboselog(*this, 0, "%s", "slave_r: De-asserting IRQ2\n" );
- m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
- break;
+ m_int_callback(CLEAR_LINE); break;
}
}
m_channel[offset].m_out_index++;
@@ -434,7 +432,7 @@ WRITE16_MEMBER( cdislave_device::slave_w )
cdislave_device::cdislave_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, CDI_SLAVE, tag, owner, clock)
- , m_maincpu(*this, ":maincpu")
+ , m_int_callback(*this)
, m_dmadac(*this, ":dac%u", 1U)
, m_mousex(*this, "MOUSEX")
, m_mousey(*this, "MOUSEY")
@@ -443,6 +441,17 @@ cdislave_device::cdislave_device(const machine_config &mconfig, const char *tag,
}
//-------------------------------------------------
+// device_resolve_objects - resolve objects that
+// may be needed for other devices to set
+// initial conditions at start time
+//-------------------------------------------------
+
+void cdislave_device::device_resolve_objects()
+{
+ m_int_callback.resolve_safe();
+}
+
+//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
@@ -529,4 +538,6 @@ void cdislave_device::device_reset()
m_fake_mouse_x = 0;
m_fake_mouse_y = 0;
+
+ m_int_callback(CLEAR_LINE);
}
diff --git a/src/mame/machine/cdislave.h b/src/mame/machine/cdislave.h
index 1a38b50afed..9f35ea35cdd 100644
--- a/src/mame/machine/cdislave.h
+++ b/src/mame/machine/cdislave.h
@@ -40,6 +40,8 @@ public:
// construction/destruction
cdislave_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ auto int_callback() { return m_int_callback.bind(); }
+
// external callbacks
DECLARE_INPUT_CHANGED_MEMBER( mouse_update );
@@ -50,6 +52,7 @@ public:
protected:
// device-level overrides
+ virtual void device_resolve_objects() override;
virtual void device_start() override;
virtual void device_reset() override;
virtual ioport_constructor device_input_ports() const override;
@@ -58,7 +61,8 @@ protected:
TIMER_CALLBACK_MEMBER( trigger_readback_int );
private:
- required_device<cpu_device> m_maincpu;
+ devcb_write_line m_int_callback;
+
required_device_array<dmadac_sound_device, 2> m_dmadac;
required_ioport m_mousex;
diff --git a/src/mame/video/mcd212.cpp b/src/mame/video/mcd212.cpp
index 8d7e65b9ba4..76a63403e03 100644
--- a/src/mame/video/mcd212.cpp
+++ b/src/mame/video/mcd212.cpp
@@ -603,24 +603,10 @@ void mcd212_device::process_ica(int channel)
verboselog(*this, 11, "%08x: %08x: ICA %d: INTERRUPT\n", addr * 2 + channel * 0x200000, cmd, channel );
m_channel[1].csrr |= 1 << (2 - channel);
if(m_channel[1].csrr & (MCD212_CSR2R_IT1 | MCD212_CSR2R_IT2))
- {
- uint8_t interrupt = (state->m_scc->get_lir() >> 4) & 7;
- if(interrupt)
- {
- state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
- state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
- }
- }
+ m_int1_callback(ASSERT_LINE);
#if 0
if(m_channel[1].csrr & MCD212_CSR2R_IT2)
- {
- uint8_t interrupt = state->m_scc68070_regs.lir & 7;
- if(interrupt)
- {
- state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 24 + interrupt);
- state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
- }
- }
+ m_int2_callback(ASSERT_LINE);
#endif
break;
case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: // RELOAD DISPLAY PARAMETERS
@@ -693,24 +679,10 @@ void mcd212_device::process_dca(int channel)
verboselog(*this, 11, "%08x: %08x: DCA %d: INTERRUPT\n", addr * 2 + channel * 0x200000, cmd, channel );
m_channel[1].csrr |= 1 << (2 - channel);
if(m_channel[1].csrr & (MCD212_CSR2R_IT1 | MCD212_CSR2R_IT2))
- {
- uint8_t interrupt = (state->m_scc->get_lir() >> 4) & 7;
- if(interrupt)
- {
- state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 56 + interrupt);
- state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
- }
- }
+ m_int1_callback(ASSERT_LINE);
#if 0
if(m_channel[1].csrr & MCD212_CSR2R_IT2)
- {
- uint8_t interrupt = state->m_scc68070_regs.lir & 7;
- if(interrupt)
- {
- state->m_maincpu->set_input_line_vector(M68K_IRQ_1 + (interrupt - 1), 24 + interrupt);
- state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt - 1), ASSERT_LINE);
- }
- }
+ m_int2_callback(ASSERT_LINE);
#endif
break;
case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: // RELOAD DISPLAY PARAMETERS
@@ -1328,7 +1300,6 @@ void mcd212_device::draw_scanline(int y)
READ16_MEMBER( mcd212_device::regs_r )
{
- cdi_state *state = machine().driver_data<cdi_state>();
uint8_t channel = 1 - (offset / 8);
switch(offset)
@@ -1342,20 +1313,14 @@ READ16_MEMBER( mcd212_device::regs_r )
{
return m_channel[0].csrr;
}
- else
+ else if (!machine().side_effects_disabled())
{
uint8_t old_csr = m_channel[1].csrr;
- uint8_t interrupt1 = (state->m_scc->get_lir() >> 4) & 7;
- //uint8_t interrupt2 = state->m_scc68070_regs.lir & 7;
m_channel[1].csrr &= ~(MCD212_CSR2R_IT1 | MCD212_CSR2R_IT2);
- if(interrupt1)
- {
- state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt1 - 1), CLEAR_LINE);
- }
- //if(interrupt2)
- //{
- // state->m_maincpu->set_input_line(M68K_IRQ_1 + (interrupt2 - 1), CLEAR_LINE);
- //}
+ if (old_csr & MCD212_CSR2R_IT1)
+ m_int1_callback(CLEAR_LINE);
+ if (old_csr & MCD212_CSR2R_IT2)
+ m_int2_callback(CLEAR_LINE);
return old_csr;
}
}
@@ -1511,6 +1476,9 @@ void mcd212_device::device_reset()
}
memset(m_region_flag_0, 0, 768);
memset(m_region_flag_1, 0, 768);
+
+ m_int1_callback(CLEAR_LINE);
+ m_int2_callback(CLEAR_LINE);
}
//-------------------------------------------------
@@ -1520,11 +1488,25 @@ void mcd212_device::device_reset()
mcd212_device::mcd212_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, MCD212, tag, owner, clock)
, device_video_interface(mconfig, *this)
+ , m_int1_callback(*this)
+ , m_int2_callback(*this)
, m_lcd(*this, ":lcd")
{
}
//-------------------------------------------------
+// device_resolve_objects - resolve objects that
+// may be needed for other devices to set
+// initial conditions at start time
+//-------------------------------------------------
+
+void mcd212_device::device_resolve_objects()
+{
+ m_int1_callback.resolve_safe();
+ m_int2_callback.resolve_safe();
+}
+
+//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
diff --git a/src/mame/video/mcd212.h b/src/mame/video/mcd212.h
index e903609de65..4169bf901f3 100644
--- a/src/mame/video/mcd212.h
+++ b/src/mame/video/mcd212.h
@@ -122,6 +122,9 @@ public:
// construction/destruction
mcd212_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ auto int1_callback() { return m_int1_callback.bind(); }
+ auto int2_callback() { return m_int2_callback.bind(); }
+
// device members
DECLARE_READ16_MEMBER( regs_r );
DECLARE_WRITE16_MEMBER( regs_w );
@@ -196,10 +199,15 @@ public:
protected:
// device-level overrides
+ virtual void device_resolve_objects() override;
virtual void device_start() override;
virtual void device_reset() override;
private:
+ // interrupt callbacks
+ devcb_write_line m_int1_callback;
+ devcb_write_line m_int2_callback;
+
required_device<screen_device> m_lcd;
// internal state