diff options
Diffstat (limited to 'src/devices/machine/vrc5074.cpp')
-rw-r--r-- | src/devices/machine/vrc5074.cpp | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/devices/machine/vrc5074.cpp b/src/devices/machine/vrc5074.cpp index 927030477e8..30df10a20f6 100644 --- a/src/devices/machine/vrc5074.cpp +++ b/src/devices/machine/vrc5074.cpp @@ -673,6 +673,8 @@ void vrc5074_device::update_pci_irq(const int index, const int state) { m_nile_irq_state &= ~(1 << (index + 8)); m_nile_irq_state |= state << (index + 8); + if (LOG_NILE_IRQS) + logerror("update_pci_irq: m_nile_irq_state: %04x index=%d state=%d\n", m_nile_irq_state, index, state); update_nile_irqs(); } @@ -725,15 +727,14 @@ void vrc5074_device::update_nile_irqs() if (LOG_NILE_IRQS) logerror("NILE IRQs:"); for (i = 0; i < 6; i++) { + if (LOG_NILE_IRQS) logerror(" %d", (irq & (1 << i)) ? 1 : 0); if (change & (1 << i)) { if (irq & (1 << i)) { - if (LOG_NILE_IRQS) logerror(" 1"); m_cpu->set_input_line(MIPS3_IRQ0 + i, ASSERT_LINE); } else { - if (LOG_NILE_IRQS) logerror(" 0"); m_cpu->set_input_line(MIPS3_IRQ0 + i, CLEAR_LINE); } } @@ -747,7 +748,7 @@ TIMER_CALLBACK_MEMBER(vrc5074_device::nile_timer_callback) { int which = param; - if (LOG_TIMERS) logerror("timer %d fired\n", which); + if (LOG_TIMERS | LOG_NILE_IRQS) logerror("timer %d fired period: %e\n", which, m_timer_period[which]); /* adjust the timer to fire again */ { @@ -787,7 +788,7 @@ READ32_MEMBER(vrc5074_device::cpu_reg_r) case NREG_INTCTRL + 0: /* Interrupt control */ case NREG_INTCTRL + 1: /* Interrupt control */ - if (LOG_NILE) logerror("%s NILE READ: interrupt control(%03X) = %08X\n", machine().describe_context(), offset * 4, result); + if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE READ: interrupt control(%03X) = %08X\n", machine().describe_context(), offset * 4, result); update_nile_irqs(); logit = 0; break; @@ -891,28 +892,28 @@ WRITE32_MEMBER(vrc5074_device::cpu_reg_w) case NREG_INTCTRL + 0: /* Interrupt control */ case NREG_INTCTRL + 1: /* Interrupt control */ - if (LOG_NILE) logerror("%s NILE WRITE: interrupt control(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); + if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE WRITE: interrupt control(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); logit = 0; update_nile_irqs(); break; case NREG_INTSTAT0 + 0: /* Interrupt status 0 */ case NREG_INTSTAT0 + 1: /* Interrupt status 0 */ - if (LOG_NILE) logerror("%s NILE WRITE: interrupt status 0(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); + if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE WRITE: interrupt status 0(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); logit = 0; update_nile_irqs(); break; case NREG_INTSTAT1 + 0: /* Interrupt status 1 */ case NREG_INTSTAT1 + 1: /* Interrupt status 1 */ - if (LOG_NILE) logerror("%s NILE WRITE: interrupt status 1/enable(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); + if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE WRITE: interrupt status 1/enable(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); logit = 0; update_nile_irqs(); break; case NREG_INTCLR + 0: /* Interrupt clear */ //case NREG_INTCLR + 1: /* Interrupt clear */ - if (LOG_NILE) logerror("%s NILE WRITE: interrupt clear(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); + if (LOG_NILE | LOG_NILE_IRQS) logerror("%s NILE WRITE: interrupt clear(%03X) = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); logit = 0; //m_nile_irq_state &= ~(m_cpu_regs[offset] & ~0xf00); m_nile_irq_state &= ~(data); @@ -1001,7 +1002,7 @@ WRITE_LINE_MEMBER(vrc5074_device::uart_irq_callback) if (state ^ m_uart_irq) { m_uart_irq = state; update_nile_irqs(); - if (LOG_NILE) + if (LOG_NILE | LOG_NILE_IRQS) logerror("uart_irq_callback: state = %d\n", state); } } |