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author Ivan Vangelista <mesgnet@yahoo.it>2020-05-30 17:27:25 +0200
committer Ivan Vangelista <mesgnet@yahoo.it>2020-05-30 17:27:25 +0200
commitbd329bc16a7be9c0eec1c17edb3ecfdb410ca960 (patch)
tree607bf46bb92ab8981bc5d60d2036980ef0dc7d11
parentcddd9181b05b9945c8b76579464d552f8dd368c9 (diff)
drivers with m, n: some macro removal (nw)
-rw-r--r--src/devices/bus/neogeo/boot_svc.h8
-rw-r--r--src/devices/bus/neogeo/prot_pvc.cpp4
-rw-r--r--src/devices/bus/neogeo/prot_pvc.h4
-rw-r--r--src/devices/bus/neogeo/pvc.h4
-rw-r--r--src/mame/drivers/maygayv1.cpp28
-rw-r--r--src/mame/drivers/mazerbla.cpp60
-rw-r--r--src/mame/drivers/mediagx.cpp50
-rw-r--r--src/mame/drivers/menghong.cpp44
-rw-r--r--src/mame/drivers/meritm.cpp34
-rw-r--r--src/mame/drivers/microterm_f8.cpp36
-rw-r--r--src/mame/drivers/midas.cpp32
-rw-r--r--src/mame/drivers/midqslvr.cpp28
-rw-r--r--src/mame/drivers/mil4000.cpp40
-rw-r--r--src/mame/drivers/mirax.cpp16
-rw-r--r--src/mame/drivers/missile.cpp16
-rw-r--r--src/mame/drivers/mjsenpu.cpp42
-rw-r--r--src/mame/drivers/mjsister.cpp20
-rw-r--r--src/mame/drivers/mmd1.cpp20
-rw-r--r--src/mame/drivers/mmd2.cpp4
-rw-r--r--src/mame/drivers/mpu4vid.cpp32
-rw-r--r--src/mame/drivers/mrgame.cpp36
-rw-r--r--src/mame/drivers/mstation.cpp68
-rw-r--r--src/mame/drivers/multi8.cpp40
-rw-r--r--src/mame/drivers/multigam.cpp98
-rw-r--r--src/mame/drivers/mvme147.cpp58
-rw-r--r--src/mame/drivers/mz2000.cpp86
-rw-r--r--src/mame/drivers/mz3500.cpp238
-rw-r--r--src/mame/drivers/n64.cpp4
-rw-r--r--src/mame/drivers/nakajies.cpp64
-rw-r--r--src/mame/drivers/namcos10.cpp82
-rw-r--r--src/mame/drivers/namcos11.cpp39
-rw-r--r--src/mame/drivers/namcos12.cpp97
-rw-r--r--src/mame/drivers/namcos21.cpp55
-rw-r--r--src/mame/drivers/namcos21_c67.cpp28
-rw-r--r--src/mame/drivers/namcos21_de.cpp28
-rw-r--r--src/mame/drivers/namcos23.cpp192
-rw-r--r--src/mame/drivers/nanos.cpp4
-rw-r--r--src/mame/drivers/nascom1.cpp20
-rw-r--r--src/mame/drivers/ncdmips.cpp8
-rw-r--r--src/mame/drivers/ncdppc.cpp8
-rw-r--r--src/mame/drivers/neogeocd.cpp28
-rw-r--r--src/mame/drivers/neopcb.cpp9
-rw-r--r--src/mame/drivers/neoprint.cpp46
-rw-r--r--src/mame/drivers/neptunp2.cpp4
-rw-r--r--src/mame/drivers/nexus3d.cpp64
-rw-r--r--src/mame/drivers/ngen.cpp52
-rw-r--r--src/mame/drivers/nibble.cpp4
-rw-r--r--src/mame/drivers/nightgal.cpp64
-rw-r--r--src/mame/drivers/nightmare.cpp4
-rw-r--r--src/mame/drivers/nmg5.cpp36
-rw-r--r--src/mame/drivers/nokia_3310.cpp36
-rw-r--r--src/mame/drivers/notechan.cpp16
-rw-r--r--src/mame/drivers/notetaker.cpp52
-rw-r--r--src/mame/drivers/novag_cforte.cpp16
-rw-r--r--src/mame/drivers/novag_const.cpp16
-rw-r--r--src/mame/drivers/novag_diablo.cpp20
-rw-r--r--src/mame/drivers/novag_savant.cpp38
-rw-r--r--src/mame/drivers/novag_sexpert.cpp38
-rw-r--r--src/mame/drivers/nsm.cpp12
-rw-r--r--src/mame/drivers/nsmpoker.cpp14
-rw-r--r--src/mame/drivers/nss.cpp46
-rw-r--r--src/mame/drivers/nwk-tr.cpp52
-rw-r--r--src/mame/drivers/nyny.cpp16
-rw-r--r--src/mame/machine/megacd.cpp2
-rw-r--r--src/mame/machine/megacdcd.cpp86
-rw-r--r--src/mame/machine/megacdcd.h58
66 files changed, 1299 insertions, 1305 deletions
diff --git a/src/devices/bus/neogeo/boot_svc.h b/src/devices/bus/neogeo/boot_svc.h
index 57c68c29afd..3204a170267 100644
--- a/src/devices/bus/neogeo/boot_svc.h
+++ b/src/devices/bus/neogeo/boot_svc.h
@@ -20,8 +20,8 @@ public:
neogeo_svcboot_cart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual uint32_t get_bank_base(uint16_t sel) override { return m_pvc_prot->get_bank_base(); }
- virtual DECLARE_READ16_MEMBER(protection_r) override { return m_pvc_prot->protection_r(space, offset, mem_mask); }
- virtual DECLARE_WRITE16_MEMBER(protection_w) override { m_pvc_prot->protection_w(space, offset, data, mem_mask); }
+ virtual DECLARE_READ16_MEMBER(protection_r) override { return m_pvc_prot->protection_r(offset); }
+ virtual DECLARE_WRITE16_MEMBER(protection_w) override { m_pvc_prot->protection_w(offset, data, mem_mask); }
virtual void decrypt_all(DECRYPT_ALL_PARAMS) override;
virtual int get_fixed_bank_type() override { return 0; }
@@ -74,8 +74,8 @@ public:
neogeo_svcsplus_cart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual uint32_t get_bank_base(uint16_t sel) override { return m_pvc_prot->get_bank_base(); }
- virtual DECLARE_READ16_MEMBER(protection_r) override { return m_pvc_prot->protection_r(space, offset, mem_mask); }
- virtual DECLARE_WRITE16_MEMBER(protection_w) override { m_pvc_prot->protection_w(space, offset, data, mem_mask); }
+ virtual DECLARE_READ16_MEMBER(protection_r) override { return m_pvc_prot->protection_r(offset); }
+ virtual DECLARE_WRITE16_MEMBER(protection_w) override { m_pvc_prot->protection_w(offset, data, mem_mask); }
virtual void decrypt_all(DECRYPT_ALL_PARAMS) override;
virtual int get_fixed_bank_type() override { return 0; }
diff --git a/src/devices/bus/neogeo/prot_pvc.cpp b/src/devices/bus/neogeo/prot_pvc.cpp
index 8e290596576..1f0d734e732 100644
--- a/src/devices/bus/neogeo/prot_pvc.cpp
+++ b/src/devices/bus/neogeo/prot_pvc.cpp
@@ -75,12 +75,12 @@ uint32_t pvc_prot_device::get_bank_base()
return bankaddress + 0x100000;
}
-READ16_MEMBER( pvc_prot_device::protection_r )
+uint16_t pvc_prot_device::protection_r(offs_t offset)
{
return m_cart_ram[offset];
}
-WRITE16_MEMBER( pvc_prot_device::protection_w )
+void pvc_prot_device::protection_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_cart_ram[offset]);
if (offset == 0xff0)
diff --git a/src/devices/bus/neogeo/prot_pvc.h b/src/devices/bus/neogeo/prot_pvc.h
index d2855808331..f133424c2fa 100644
--- a/src/devices/bus/neogeo/prot_pvc.h
+++ b/src/devices/bus/neogeo/prot_pvc.h
@@ -19,8 +19,8 @@ public:
void pvc_write_pack_color();
// void pvc_write_bankswitch(address_space &space);
uint32_t get_bank_base();
- DECLARE_READ16_MEMBER(protection_r);
- DECLARE_WRITE16_MEMBER(protection_w);
+ uint16_t protection_r(offs_t offset);
+ void protection_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t m_cart_ram[0x1000];
diff --git a/src/devices/bus/neogeo/pvc.h b/src/devices/bus/neogeo/pvc.h
index 0b3f9c6ce75..00be5322f59 100644
--- a/src/devices/bus/neogeo/pvc.h
+++ b/src/devices/bus/neogeo/pvc.h
@@ -21,8 +21,8 @@ public:
// reading and writing
virtual uint32_t get_bank_base(uint16_t sel) override { return m_pvc_prot->get_bank_base(); }
- virtual DECLARE_READ16_MEMBER(protection_r) override { return m_pvc_prot->protection_r(space, offset, mem_mask); }
- virtual DECLARE_WRITE16_MEMBER(protection_w) override { m_pvc_prot->protection_w(space, offset, data, mem_mask); }
+ virtual DECLARE_READ16_MEMBER(protection_r) override { return m_pvc_prot->protection_r(offset); }
+ virtual DECLARE_WRITE16_MEMBER(protection_w) override { m_pvc_prot->protection_w(offset, data, mem_mask); }
virtual void decrypt_all(DECRYPT_ALL_PARAMS) override { }
virtual int get_fixed_bank_type() override { return 0; }
diff --git a/src/mame/drivers/maygayv1.cpp b/src/mame/drivers/maygayv1.cpp
index 558d9fd2892..d3e0999bd22 100644
--- a/src/mame/drivers/maygayv1.cpp
+++ b/src/mame/drivers/maygayv1.cpp
@@ -229,13 +229,13 @@ public:
void init_screenpl();
private:
- DECLARE_WRITE16_MEMBER(i82716_w);
- DECLARE_READ16_MEMBER(i82716_r);
- DECLARE_WRITE16_MEMBER(write_odd);
- DECLARE_READ16_MEMBER(read_odd);
- DECLARE_WRITE16_MEMBER(vsync_int_ctrl);
- DECLARE_READ8_MEMBER(mcu_r);
- DECLARE_WRITE8_MEMBER(mcu_w);
+ void i82716_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t i82716_r(offs_t offset);
+ void write_odd(uint16_t data);
+ uint16_t read_odd();
+ void vsync_int_ctrl(uint16_t data);
+ uint8_t mcu_r(offs_t offset);
+ void mcu_w(offs_t offset, uint8_t data);
uint8_t b_read();
void b_writ(uint8_t data);
void strobe_w(uint8_t data);
@@ -277,7 +277,7 @@ private:
-WRITE16_MEMBER(maygayv1_state::i82716_w)
+void maygayv1_state::i82716_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
i82716_t &i82716 = m_i82716;
// Accessing register window?
@@ -296,7 +296,7 @@ WRITE16_MEMBER(maygayv1_state::i82716_w)
}
}
-READ16_MEMBER(maygayv1_state::i82716_r)
+uint16_t maygayv1_state::i82716_r(offs_t offset)
{
i82716_t &i82716 = m_i82716;
// Accessing register window?
@@ -513,12 +513,12 @@ WRITE_LINE_MEMBER(maygayv1_state::screen_vblank_maygayv1)
-WRITE16_MEMBER(maygayv1_state::write_odd)
+void maygayv1_state::write_odd(uint16_t data)
{
}
//;860008 is a latch of some sort
-READ16_MEMBER(maygayv1_state::read_odd)
+uint16_t maygayv1_state::read_odd()
{
return 0;
}
@@ -558,7 +558,7 @@ uint8_t maygayv1_state::kbd_r()
return m_kbd_ports[m_lamp_strobe & 0x07]->read();
}
-WRITE16_MEMBER(maygayv1_state::vsync_int_ctrl)
+void maygayv1_state::vsync_int_ctrl(uint16_t data)
{
m_vsync_latch_preset = data & 0x0100;
@@ -618,7 +618,7 @@ void maygayv1_state::main_map(address_map &map)
*/
-READ8_MEMBER(maygayv1_state::mcu_r)
+uint8_t maygayv1_state::mcu_r(offs_t offset)
{
switch (offset)
{
@@ -635,7 +635,7 @@ READ8_MEMBER(maygayv1_state::mcu_r)
return 0;
}
-WRITE8_MEMBER(maygayv1_state::mcu_w)
+void maygayv1_state::mcu_w(offs_t offset, uint8_t data)
{
logerror("O %x D %x",offset,data);
diff --git a/src/mame/drivers/mazerbla.cpp b/src/mame/drivers/mazerbla.cpp
index 269ee0e52ae..6eda5e0cf7c 100644
--- a/src/mame/drivers/mazerbla.cpp
+++ b/src/mame/drivers/mazerbla.cpp
@@ -141,21 +141,21 @@ public:
void init_greatgun();
private:
- DECLARE_WRITE8_MEMBER(cfb_rom_bank_sel_w);
- DECLARE_WRITE8_MEMBER(cfb_zpu_int_req_set_w);
- DECLARE_READ8_MEMBER(cfb_zpu_int_req_clr);
- DECLARE_READ8_MEMBER(ls670_0_r);
- DECLARE_WRITE8_MEMBER(ls670_0_w);
- DECLARE_READ8_MEMBER(ls670_1_r);
- DECLARE_WRITE8_MEMBER(ls670_1_w);
- DECLARE_WRITE8_MEMBER(zpu_bcd_decoder_w);
- DECLARE_READ8_MEMBER(zpu_inputs_r);
- DECLARE_WRITE8_MEMBER(zpu_led_w);
- DECLARE_WRITE8_MEMBER(zpu_lamps_w);
- DECLARE_WRITE8_MEMBER(zpu_coin_counter_w);
- DECLARE_WRITE8_MEMBER(cfb_led_w);
- DECLARE_WRITE8_MEMBER(vsb_ls273_audio_control_w);
- DECLARE_WRITE8_MEMBER(sound_int_clear_w);
+ void cfb_rom_bank_sel_w(uint8_t data);
+ void cfb_zpu_int_req_set_w(uint8_t data);
+ uint8_t cfb_zpu_int_req_clr();
+ uint8_t ls670_0_r(offs_t offset);
+ void ls670_0_w(offs_t offset, uint8_t data);
+ uint8_t ls670_1_r(offs_t offset);
+ void ls670_1_w(offs_t offset, uint8_t data);
+ void zpu_bcd_decoder_w(uint8_t data);
+ uint8_t zpu_inputs_r();
+ void zpu_led_w(offs_t offset, uint8_t data);
+ void zpu_lamps_w(uint8_t data);
+ void zpu_coin_counter_w(offs_t offset, uint8_t data);
+ void cfb_led_w(uint8_t data);
+ void vsb_ls273_audio_control_w(uint8_t data);
+ void sound_int_clear_w(uint8_t data);
void gg_led_ctrl_w(uint8_t data);
void mazerbla_palette(palette_device &palette);
uint32_t screen_update_mazerbla(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
@@ -257,7 +257,7 @@ WRITE_LINE_MEMBER(mazerbla_state::screen_vblank)
}
}
-WRITE8_MEMBER(mazerbla_state::cfb_rom_bank_sel_w)
+void mazerbla_state::cfb_rom_bank_sel_w(uint8_t data)
{
m_gfx_rom_bank = data;
@@ -270,14 +270,14 @@ WRITE8_MEMBER(mazerbla_state::cfb_rom_bank_sel_w)
*
*************************************/
-WRITE8_MEMBER(mazerbla_state::cfb_zpu_int_req_set_w)
+void mazerbla_state::cfb_zpu_int_req_set_w(uint8_t data)
{
m_zpu_int_vector &= ~2; /* clear D1 on INTA (interrupt acknowledge) */
m_maincpu->set_input_line(0, ASSERT_LINE); /* main cpu interrupt (comes from CFB (generated at the start of INT routine on CFB) - vblank?) */
}
-READ8_MEMBER(mazerbla_state::cfb_zpu_int_req_clr)
+uint8_t mazerbla_state::cfb_zpu_int_req_clr()
{
// this clears all interrupts
m_zpu_int_vector = 0xff;
@@ -286,7 +286,7 @@ READ8_MEMBER(mazerbla_state::cfb_zpu_int_req_clr)
return 0;
}
-READ8_MEMBER(mazerbla_state::ls670_0_r)
+uint8_t mazerbla_state::ls670_0_r(offs_t offset)
{
/* set a timer to force synchronization after the read */
machine().scheduler().synchronize();
@@ -302,13 +302,13 @@ TIMER_CALLBACK_MEMBER(mazerbla_state::deferred_ls670_0_w)
m_ls670_0[offset] = data;
}
-WRITE8_MEMBER(mazerbla_state::ls670_0_w)
+void mazerbla_state::ls670_0_w(offs_t offset, uint8_t data)
{
/* do this on a timer to let the CPUs synchronize */
machine().scheduler().synchronize(timer_expired_delegate(FUNC(mazerbla_state::deferred_ls670_0_w),this), (offset << 8) | data);
}
-READ8_MEMBER(mazerbla_state::ls670_1_r)
+uint8_t mazerbla_state::ls670_1_r(offs_t offset)
{
/* set a timer to force synchronization after the read */
machine().scheduler().synchronize();
@@ -324,7 +324,7 @@ TIMER_CALLBACK_MEMBER(mazerbla_state::deferred_ls670_1_w)
m_ls670_1[offset] = data;
}
-WRITE8_MEMBER(mazerbla_state::ls670_1_w)
+void mazerbla_state::ls670_1_w(offs_t offset, uint8_t data)
{
/* do this on a timer to let the CPUs synchronize */
machine().scheduler().synchronize(timer_expired_delegate(FUNC(mazerbla_state::deferred_ls670_1_w),this), (offset << 8) | data);
@@ -383,13 +383,13 @@ Vertical movement of gun is Strobe 9, Bits 0-7.
*/
-WRITE8_MEMBER(mazerbla_state::zpu_bcd_decoder_w)
+void mazerbla_state::zpu_bcd_decoder_w(uint8_t data)
{
/* bcd decoder used a input select (a mux) for reads from port 0x62 */
m_bcd_7445 = data & 0xf;
}
-READ8_MEMBER(mazerbla_state::zpu_inputs_r)
+uint8_t mazerbla_state::zpu_inputs_r()
{
static const char *const strobenames[] = { "ZPU", "DSW0", "DSW1", "DSW2", "DSW3", "BUTTONS", "STICK0_X", "STICK0_Y",
"STICK1_X", "STICK1_Y", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED" };
@@ -401,14 +401,14 @@ READ8_MEMBER(mazerbla_state::zpu_inputs_r)
return ret;
}
-WRITE8_MEMBER(mazerbla_state::zpu_led_w)
+void mazerbla_state::zpu_led_w(offs_t offset, uint8_t data)
{
/* 0x6e - reset (offset = 0)*/
/* 0x6f - set */
m_leds[0] = BIT(offset, 0);
}
-WRITE8_MEMBER(mazerbla_state::zpu_lamps_w)
+void mazerbla_state::zpu_lamps_w(uint8_t data)
{
/* bit 4 = /LAMP0 */
/* bit 5 = /LAMP1 */
@@ -417,13 +417,13 @@ WRITE8_MEMBER(mazerbla_state::zpu_lamps_w)
/*m_lamps[1] = BIT(data, 5);*/
}
-WRITE8_MEMBER(mazerbla_state::zpu_coin_counter_w)
+void mazerbla_state::zpu_coin_counter_w(offs_t offset, uint8_t data)
{
/* bit 6 = coin counter */
machine().bookkeeping().coin_counter_w(offset, BIT(data, 6));
}
-WRITE8_MEMBER(mazerbla_state::cfb_led_w)
+void mazerbla_state::cfb_led_w(uint8_t data)
{
/* bit 7 - led on */
m_leds[2] = BIT(data, 7);
@@ -442,7 +442,7 @@ void mazerbla_state::gg_led_ctrl_w(uint8_t data)
*
*************************************/
-WRITE8_MEMBER(mazerbla_state::vsb_ls273_audio_control_w)
+void mazerbla_state::vsb_ls273_audio_control_w(uint8_t data)
{
m_vsb_ls273 = data;
@@ -450,7 +450,7 @@ WRITE8_MEMBER(mazerbla_state::vsb_ls273_audio_control_w)
m_leds[1] = BIT(data, 5);
}
-WRITE8_MEMBER(mazerbla_state::sound_int_clear_w)
+void mazerbla_state::sound_int_clear_w(uint8_t data)
{
m_subcpu->set_input_line(0, CLEAR_LINE);
}
diff --git a/src/mame/drivers/mediagx.cpp b/src/mame/drivers/mediagx.cpp
index 2d8633ec598..353f25ab02d 100644
--- a/src/mame/drivers/mediagx.cpp
+++ b/src/mame/drivers/mediagx.cpp
@@ -114,18 +114,18 @@ private:
uint32_t pc;
};
- DECLARE_READ32_MEMBER(disp_ctrl_r);
- DECLARE_WRITE32_MEMBER(disp_ctrl_w);
- DECLARE_READ32_MEMBER(memory_ctrl_r);
- DECLARE_WRITE32_MEMBER(memory_ctrl_w);
- DECLARE_READ32_MEMBER(biu_ctrl_r);
- DECLARE_WRITE32_MEMBER(biu_ctrl_w);
- DECLARE_READ32_MEMBER(parallel_port_r);
- DECLARE_WRITE32_MEMBER(parallel_port_w);
- DECLARE_READ32_MEMBER(ad1847_r);
- DECLARE_WRITE32_MEMBER(ad1847_w);
- DECLARE_READ8_MEMBER(io20_r);
- DECLARE_WRITE8_MEMBER(io20_w);
+ uint32_t disp_ctrl_r(offs_t offset);
+ void disp_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t memory_ctrl_r(offs_t offset);
+ void memory_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t biu_ctrl_r(offs_t offset);
+ void biu_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t parallel_port_r(offs_t offset, uint32_t mem_mask = ~0);
+ void parallel_port_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t ad1847_r(offs_t offset);
+ void ad1847_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint8_t io20_r(offs_t offset);
+ void io20_w(offs_t offset, uint8_t data);
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
template <offs_t N> uint32_t speedup_r(address_space &space) { return generic_speedup(space, N); }
TIMER_DEVICE_CALLBACK_MEMBER(sound_timer_callback);
@@ -415,7 +415,7 @@ uint32_t mediagx_state::screen_update(screen_device &screen, bitmap_rgb32 &bitma
return 0;
}
-READ32_MEMBER(mediagx_state::disp_ctrl_r)
+uint32_t mediagx_state::disp_ctrl_r(offs_t offset)
{
uint32_t r = m_disp_ctrl_reg[offset];
@@ -437,19 +437,19 @@ READ32_MEMBER(mediagx_state::disp_ctrl_r)
return r;
}
-WRITE32_MEMBER(mediagx_state::disp_ctrl_w)
+void mediagx_state::disp_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// printf("disp_ctrl_w %08X, %08X, %08X\n", data, offset*4, mem_mask);
COMBINE_DATA(m_disp_ctrl_reg + offset);
}
-READ32_MEMBER(mediagx_state::memory_ctrl_r)
+uint32_t mediagx_state::memory_ctrl_r(offs_t offset)
{
return m_memory_ctrl_reg[offset];
}
-WRITE32_MEMBER(mediagx_state::memory_ctrl_w)
+void mediagx_state::memory_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// printf("memory_ctrl_w %08X, %08X, %08X\n", data, offset*4, mem_mask);
if (offset == 0x20/4)
@@ -482,7 +482,7 @@ WRITE32_MEMBER(mediagx_state::memory_ctrl_w)
-READ32_MEMBER(mediagx_state::biu_ctrl_r)
+uint32_t mediagx_state::biu_ctrl_r(offs_t offset)
{
if (offset == 0)
{
@@ -491,7 +491,7 @@ READ32_MEMBER(mediagx_state::biu_ctrl_r)
return m_biu_ctrl_reg[offset];
}
-WRITE32_MEMBER(mediagx_state::biu_ctrl_w)
+void mediagx_state::biu_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
//osd_printf_debug("biu_ctrl_w %08X, %08X, %08X\n", data, offset, mem_mask);
COMBINE_DATA(m_biu_ctrl_reg + offset);
@@ -503,12 +503,12 @@ WRITE32_MEMBER(mediagx_state::biu_ctrl_w)
}
#ifdef UNUSED_FUNCTION
-WRITE32_MEMBER(mediagx_state::bios_ram_w)
+void mediagx_state::bios_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
}
#endif
-READ8_MEMBER(mediagx_state::io20_r)
+uint8_t mediagx_state::io20_r(offs_t offset)
{
uint8_t r = 0;
@@ -523,7 +523,7 @@ READ8_MEMBER(mediagx_state::io20_r)
return r;
}
-WRITE8_MEMBER(mediagx_state::io20_w)
+void mediagx_state::io20_w(offs_t offset, uint8_t data)
{
// 0x22, 0x23, Cyrix configuration registers
if (offset == 0x00)
@@ -536,7 +536,7 @@ WRITE8_MEMBER(mediagx_state::io20_w)
}
}
-READ32_MEMBER(mediagx_state::parallel_port_r)
+uint32_t mediagx_state::parallel_port_r(offs_t offset, uint32_t mem_mask)
{
uint32_t r = 0;
@@ -570,7 +570,7 @@ READ32_MEMBER(mediagx_state::parallel_port_r)
return r;
}
-WRITE32_MEMBER(mediagx_state::parallel_port_w)
+void mediagx_state::parallel_port_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA( &m_parport );
@@ -704,7 +704,7 @@ void mediagx_state::ad1847_reg_write(int reg, uint8_t data)
}
}
-READ32_MEMBER(mediagx_state::ad1847_r)
+uint32_t mediagx_state::ad1847_r(offs_t offset)
{
switch (offset)
{
@@ -714,7 +714,7 @@ READ32_MEMBER(mediagx_state::ad1847_r)
return 0;
}
-WRITE32_MEMBER(mediagx_state::ad1847_w)
+void mediagx_state::ad1847_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (offset == 0)
{
diff --git a/src/mame/drivers/menghong.cpp b/src/mame/drivers/menghong.cpp
index cdef9694275..557172cc87c 100644
--- a/src/mame/drivers/menghong.cpp
+++ b/src/mame/drivers/menghong.cpp
@@ -116,11 +116,11 @@ private:
uint32_t m_maxbank;
uint32_t m_FlashCmd;
- DECLARE_WRITE32_MEMBER(Banksw_w);
- DECLARE_READ32_MEMBER(FlashCmd_r);
- DECLARE_WRITE32_MEMBER(FlashCmd_w);
+ void Banksw_w(uint32_t data);
+ uint32_t FlashCmd_r();
+ void FlashCmd_w(uint32_t data);
- DECLARE_READ32_MEMBER(crzyddz2_key_r);
+ uint32_t crzyddz2_key_r();
virtual void machine_start() override;
virtual void machine_reset() override;
@@ -128,28 +128,28 @@ private:
void crzyddz2_mem(address_map &map);
// PIO
- DECLARE_READ32_MEMBER(PIOldat_r);
+ uint32_t PIOldat_r();
uint32_t m_PIO;
- DECLARE_WRITE32_MEMBER(crzyddz2_PIOldat_w);
- DECLARE_READ32_MEMBER(crzyddz2_PIOedat_r);
+ void crzyddz2_PIOldat_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t crzyddz2_PIOedat_r();
uint8_t m_crzyddz2_prot;
- DECLARE_READ8_MEMBER(menghong_shared_r);
- DECLARE_WRITE8_MEMBER(menghong_shared_w);
- DECLARE_READ8_MEMBER(crzyddz2_shared_r);
- DECLARE_WRITE8_MEMBER(crzyddz2_shared_w);
+ uint8_t menghong_shared_r(offs_t offset);
+ void menghong_shared_w(offs_t offset, uint8_t data);
+ uint8_t crzyddz2_shared_r(offs_t offset);
+ void crzyddz2_shared_w(offs_t offset, uint8_t data);
uint8_t *m_sharedram;
};
-WRITE32_MEMBER(menghong_state::Banksw_w)
+void menghong_state::Banksw_w(uint32_t data)
{
m_Bank = (data >> 1) & 7;
m_mainbank->set_entry(m_Bank);
}
-READ32_MEMBER(menghong_state::FlashCmd_r)
+uint32_t menghong_state::FlashCmd_r()
{
if ((m_FlashCmd & 0xff) == 0xff)
{
@@ -171,7 +171,7 @@ READ32_MEMBER(menghong_state::FlashCmd_r)
return 0;
}
-WRITE32_MEMBER(menghong_state::FlashCmd_w)
+void menghong_state::FlashCmd_w(uint32_t data)
{
m_FlashCmd = data;
}
@@ -181,12 +181,12 @@ WRITE32_MEMBER(menghong_state::FlashCmd_w)
// Crazy Dou Di Zhu II
// To do: HY04 (pic?) protection, 93C46 hookup
-READ8_MEMBER(menghong_state::menghong_shared_r)
+uint8_t menghong_state::menghong_shared_r(offs_t offset)
{
return m_sharedram[offset];
}
-WRITE8_MEMBER(menghong_state::menghong_shared_w)
+void menghong_state::menghong_shared_w(offs_t offset, uint8_t data)
{
m_sharedram[offset] = data;
@@ -215,12 +215,12 @@ WRITE8_MEMBER(menghong_state::menghong_shared_w)
}
}
-READ8_MEMBER(menghong_state::crzyddz2_shared_r)
+uint8_t menghong_state::crzyddz2_shared_r(offs_t offset)
{
return m_sharedram[offset];
}
-WRITE8_MEMBER(menghong_state::crzyddz2_shared_w)
+void menghong_state::crzyddz2_shared_w(offs_t offset, uint8_t data)
{
m_sharedram[offset] = data;
@@ -248,12 +248,12 @@ WRITE8_MEMBER(menghong_state::crzyddz2_shared_w)
}
}
-READ32_MEMBER(menghong_state::PIOldat_r)
+uint32_t menghong_state::PIOldat_r()
{
return m_PIO;
}
-WRITE32_MEMBER(menghong_state::crzyddz2_PIOldat_w)
+void menghong_state::crzyddz2_PIOldat_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_PIO);
//uint32_t RST = data & 0x01000000;
@@ -275,12 +275,12 @@ WRITE32_MEMBER(menghong_state::crzyddz2_PIOldat_w)
}
}
-READ32_MEMBER(menghong_state::crzyddz2_PIOedat_r)
+uint32_t menghong_state::crzyddz2_PIOedat_r()
{
return 0;//m_eeprom->do_read();
}
-READ32_MEMBER(menghong_state::crzyddz2_key_r)
+uint32_t menghong_state::crzyddz2_key_r()
{
static const char *const key_names[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4" };
diff --git a/src/mame/drivers/meritm.cpp b/src/mame/drivers/meritm.cpp
index 7fd77bcf074..c16573ec081 100644
--- a/src/mame/drivers/meritm.cpp
+++ b/src/mame/drivers/meritm.cpp
@@ -240,14 +240,14 @@ private:
int m_psd_a15;
uint16_t m_questions_loword_address;
- DECLARE_WRITE8_MEMBER(crt250_bank_w);
- DECLARE_WRITE8_MEMBER(psd_a15_w);
- DECLARE_WRITE8_MEMBER(bank_w);
- DECLARE_WRITE8_MEMBER(crt250_questions_lo_w);
- DECLARE_WRITE8_MEMBER(crt250_questions_hi_w);
- DECLARE_WRITE8_MEMBER(crt250_questions_bank_w);
- DECLARE_WRITE8_MEMBER(ds1644_w);
- DECLARE_READ8_MEMBER(ds1644_r);
+ void crt250_bank_w(uint8_t data);
+ void psd_a15_w(uint8_t data);
+ void bank_w(uint8_t data);
+ void crt250_questions_lo_w(uint8_t data);
+ void crt250_questions_hi_w(uint8_t data);
+ void crt250_questions_bank_w(uint8_t data);
+ void ds1644_w(offs_t offset, uint8_t data);
+ uint8_t ds1644_r(offs_t offset);
uint8_t _8255_port_c_r();
void crt250_port_b_w(uint8_t data);
void ay8930_port_b_w(uint8_t data);
@@ -386,7 +386,7 @@ void meritm_state::crt250_switch_banks( )
m_banks[0]->set_entry(rombank );
}
-WRITE8_MEMBER(meritm_state::crt250_bank_w)
+void meritm_state::crt250_bank_w(uint8_t data)
{
crt250_switch_banks();
}
@@ -405,14 +405,14 @@ void meritm_state::switch_banks( )
m_banks[2]->set_entry(rambank);
}
-WRITE8_MEMBER(meritm_state::psd_a15_w)
+void meritm_state::psd_a15_w(uint8_t data)
{
m_psd_a15 = data;
//logerror( "Writing PSD_A15 with %02x at PC=%04X\n", data, m_maincpu->pc() );
switch_banks();
}
-WRITE8_MEMBER(meritm_state::bank_w)
+void meritm_state::bank_w(uint8_t data)
{
switch_banks();
}
@@ -424,19 +424,19 @@ WRITE8_MEMBER(meritm_state::bank_w)
*************************************/
-WRITE8_MEMBER(meritm_state::crt250_questions_lo_w)
+void meritm_state::crt250_questions_lo_w(uint8_t data)
{
m_questions_loword_address &= 0xff00;
m_questions_loword_address |= data;
}
-WRITE8_MEMBER(meritm_state::crt250_questions_hi_w)
+void meritm_state::crt250_questions_hi_w(uint8_t data)
{
m_questions_loword_address &= 0x00ff;
m_questions_loword_address |= (data << 8);
}
-WRITE8_MEMBER(meritm_state::crt250_questions_bank_w)
+void meritm_state::crt250_questions_bank_w(uint8_t data)
{
uint32_t questions_address;
@@ -486,7 +486,7 @@ WRITE8_MEMBER(meritm_state::crt250_questions_bank_w)
*
*************************************/
-WRITE8_MEMBER(meritm_state::ds1644_w)
+void meritm_state::ds1644_w(offs_t offset, uint8_t data)
{
int rambank = (m_psd_a15 >> 2) & 0x3;
if (rambank < 3)
@@ -510,7 +510,7 @@ uint8_t meritm_state::binary_to_BCD(uint8_t data)
return ((data / 10) << 4) | (data %10);
}
-READ8_MEMBER(meritm_state::ds1644_r)
+uint8_t meritm_state::ds1644_r(offs_t offset)
{
system_time systime;
int rambank = (m_psd_a15 >> 2) & 0x3;
@@ -2423,7 +2423,7 @@ ROM_END
void meritm_state::init_megat3te()
{
- m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfff8, 0xffff, read8_delegate(*this, FUNC(meritm_state::ds1644_r)), write8_delegate(*this, FUNC(meritm_state::ds1644_w)));
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfff8, 0xffff, read8sm_delegate(*this, FUNC(meritm_state::ds1644_r)), write8sm_delegate(*this, FUNC(meritm_state::ds1644_w)));
}
/* CRT-250 */
diff --git a/src/mame/drivers/microterm_f8.cpp b/src/mame/drivers/microterm_f8.cpp
index be9068af4e0..9d476def400 100644
--- a/src/mame/drivers/microterm_f8.cpp
+++ b/src/mame/drivers/microterm_f8.cpp
@@ -49,16 +49,16 @@ private:
DECLARE_WRITE_LINE_MEMBER(vblank_w);
- DECLARE_READ8_MEMBER(bell_r);
- DECLARE_WRITE8_MEMBER(scroll_w);
- DECLARE_READ8_MEMBER(vram_r);
- DECLARE_WRITE8_MEMBER(vram_w);
- DECLARE_WRITE8_MEMBER(uart_transmit_w);
+ u8 bell_r();
+ void scroll_w(u8 data);
+ u8 vram_r(offs_t offset);
+ void vram_w(offs_t offset, u8 data);
+ void uart_transmit_w(u8 data);
bool poll_keyboard();
- DECLARE_READ8_MEMBER(key_r);
- DECLARE_READ8_MEMBER(port00_r);
- DECLARE_WRITE8_MEMBER(port00_w);
- DECLARE_READ8_MEMBER(port01_r);
+ u8 key_r();
+ u8 port00_r();
+ void port00_w(u8 data);
+ u8 port01_r();
void f8_mem(address_map &map);
void f8_io(address_map &map);
@@ -188,21 +188,21 @@ WRITE_LINE_MEMBER(microterm_f8_state::vblank_w)
m_bell->set_state(0);
}
-READ8_MEMBER(microterm_f8_state::bell_r)
+u8 microterm_f8_state::bell_r()
{
if (!machine().side_effects_disabled())
m_bell->set_state(1);
return 0;
}
-WRITE8_MEMBER(microterm_f8_state::scroll_w)
+void microterm_f8_state::scroll_w(u8 data)
{
m_scroll++;
if (m_scroll == 24)
m_scroll = 0;
}
-READ8_MEMBER(microterm_f8_state::vram_r)
+u8 microterm_f8_state::vram_r(offs_t offset)
{
offs_t vaddr = (offset >> 8) * 80 + (offset & 0x007f);
assert(vaddr < 0x800);
@@ -218,7 +218,7 @@ READ8_MEMBER(microterm_f8_state::vram_r)
return vdata & 0x7f;
}
-WRITE8_MEMBER(microterm_f8_state::vram_w)
+void microterm_f8_state::vram_w(offs_t offset, u8 data)
{
offs_t vaddr = (offset >> 8) * 80 + (offset & 0x007f);
assert(vaddr < 0x800);
@@ -228,7 +228,7 @@ WRITE8_MEMBER(microterm_f8_state::vram_w)
m_vram[vaddr] |= u16(m_attrlatch) << 4;
}
-WRITE8_MEMBER(microterm_f8_state::uart_transmit_w)
+void microterm_f8_state::uart_transmit_w(u8 data)
{
m_uart->transmit((data & 0x7f) | (m_dsw[2]->read() & 0x10) << 3);
}
@@ -254,7 +254,7 @@ bool microterm_f8_state::poll_keyboard()
return false;
}
-READ8_MEMBER(microterm_f8_state::key_r)
+u8 microterm_f8_state::key_r()
{
// Cursor is supposed to stop blinking temporarily when keys are depressed
// This implementation suspends cursor blinking when keys are actually read
@@ -268,7 +268,7 @@ READ8_MEMBER(microterm_f8_state::key_r)
return m_keylatch;
}
-READ8_MEMBER(microterm_f8_state::port00_r)
+u8 microterm_f8_state::port00_r()
{
u8 flags = m_port00;
@@ -282,12 +282,12 @@ READ8_MEMBER(microterm_f8_state::port00_r)
return flags;
}
-WRITE8_MEMBER(microterm_f8_state::port00_w)
+void microterm_f8_state::port00_w(u8 data)
{
m_port00 = data;
}
-READ8_MEMBER(microterm_f8_state::port01_r)
+u8 microterm_f8_state::port01_r()
{
u8 flags = 0;
diff --git a/src/mame/drivers/midas.cpp b/src/mame/drivers/midas.cpp
index 1120a125a73..c8c86d209bd 100644
--- a/src/mame/drivers/midas.cpp
+++ b/src/mame/drivers/midas.cpp
@@ -92,14 +92,14 @@ protected:
virtual void machine_reset() override;
private:
- DECLARE_READ16_MEMBER(ret_ffff);
- DECLARE_WRITE16_MEMBER(gfxregs_w);
- DECLARE_WRITE8_MEMBER(livequiz_coin_w);
- DECLARE_READ16_MEMBER(hammer_sensor_r);
- DECLARE_WRITE8_MEMBER(hammer_coin_w);
- DECLARE_WRITE8_MEMBER(hammer_motor_w);
- DECLARE_WRITE8_MEMBER(eeprom_w);
- DECLARE_WRITE16_MEMBER(zoomtable_w);
+ uint16_t ret_ffff();
+ void gfxregs_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ void livequiz_coin_w(uint8_t data);
+ uint16_t hammer_sensor_r();
+ void hammer_coin_w(uint8_t data);
+ void hammer_motor_w(uint8_t data);
+ void eeprom_w(uint8_t data);
+ void zoomtable_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
required_device<cpu_device> m_maincpu;
@@ -138,7 +138,7 @@ uint32_t midas_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap,
return 0;
}
-WRITE8_MEMBER(midas_state::eeprom_w)
+void midas_state::eeprom_w(uint8_t data)
{
// latch the bit
m_eeprom->di_write((data & 0x04) >> 2);
@@ -150,12 +150,12 @@ WRITE8_MEMBER(midas_state::eeprom_w)
m_eeprom->clk_write((data & 0x02) ? ASSERT_LINE : CLEAR_LINE );
}
-READ16_MEMBER(midas_state::ret_ffff)
+uint16_t midas_state::ret_ffff()
{
return 0xffff;
}
-WRITE16_MEMBER(midas_state::gfxregs_w)
+void midas_state::gfxregs_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
/* accessing the LSB only is not mapped */
if (mem_mask != 0x00ff)
@@ -173,7 +173,7 @@ WRITE16_MEMBER(midas_state::gfxregs_w)
}
}
-WRITE16_MEMBER(midas_state::zoomtable_w)
+void midas_state::zoomtable_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_zoomram[offset]);
@@ -188,7 +188,7 @@ WRITE16_MEMBER(midas_state::zoomtable_w)
Live Quiz Show
***************************************************************************************/
-WRITE8_MEMBER(midas_state::livequiz_coin_w)
+void midas_state::livequiz_coin_w(uint8_t data)
{
machine().bookkeeping().coin_counter_w(0, data & 0x0001);
#ifdef MAME_DEBUG
@@ -234,7 +234,7 @@ void midas_state::livequiz_map(address_map &map)
Hammer
***************************************************************************************/
-READ16_MEMBER(midas_state::hammer_sensor_r)
+uint16_t midas_state::hammer_sensor_r()
{
if (ioport("HAMMER")->read() & 0x80)
return 0xffff;
@@ -242,7 +242,7 @@ READ16_MEMBER(midas_state::hammer_sensor_r)
return (ioport("SENSORY")->read() << 8) | ioport("SENSORX")->read();
}
-WRITE8_MEMBER(midas_state::hammer_coin_w)
+void midas_state::hammer_coin_w(uint8_t data)
{
machine().bookkeeping().coin_counter_w(0, BIT(data, 0));
machine().bookkeeping().coin_counter_w(1, BIT(data, 1));
@@ -251,7 +251,7 @@ WRITE8_MEMBER(midas_state::hammer_coin_w)
#endif
}
-WRITE8_MEMBER(midas_state::hammer_motor_w)
+void midas_state::hammer_motor_w(uint8_t data)
{
m_prize[0]->motor_w(BIT(data, 0));
m_prize[1]->motor_w(BIT(data, 1));
diff --git a/src/mame/drivers/midqslvr.cpp b/src/mame/drivers/midqslvr.cpp
index 032c0bd7065..261937e8525 100644
--- a/src/mame/drivers/midqslvr.cpp
+++ b/src/mame/drivers/midqslvr.cpp
@@ -276,15 +276,15 @@ private:
uint8_t m_mtxc_config_reg[256];
uint8_t m_piix4_config_reg[4][256];
- DECLARE_WRITE32_MEMBER( isa_ram1_w );
- DECLARE_WRITE32_MEMBER( isa_ram2_w );
+ void isa_ram1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ void isa_ram2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
- DECLARE_WRITE32_MEMBER( bios_ext1_ram_w );
- DECLARE_WRITE32_MEMBER( bios_ext2_ram_w );
- DECLARE_WRITE32_MEMBER( bios_ext3_ram_w );
- DECLARE_WRITE32_MEMBER( bios_ext4_ram_w );
+ void bios_ext1_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ void bios_ext2_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ void bios_ext3_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ void bios_ext4_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
- DECLARE_WRITE32_MEMBER( bios_ram_w );
+ void bios_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
virtual void machine_start() override;
virtual void machine_reset() override;
void intel82439tx_init();
@@ -527,7 +527,7 @@ void midqslvr_state::intel82371ab_pci_w(int function, int reg, uint32_t data, ui
}
-WRITE32_MEMBER(midqslvr_state::isa_ram1_w)
+void midqslvr_state::isa_ram1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (m_mtxc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
{
@@ -535,7 +535,7 @@ WRITE32_MEMBER(midqslvr_state::isa_ram1_w)
}
}
-WRITE32_MEMBER(midqslvr_state::isa_ram2_w)
+void midqslvr_state::isa_ram2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (m_mtxc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
{
@@ -543,7 +543,7 @@ WRITE32_MEMBER(midqslvr_state::isa_ram2_w)
}
}
-WRITE32_MEMBER(midqslvr_state::bios_ext1_ram_w)
+void midqslvr_state::bios_ext1_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (m_mtxc_config_reg[0x5e] & 0x2) // write to RAM if this region is write-enabled
{
@@ -552,7 +552,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext1_ram_w)
}
-WRITE32_MEMBER(midqslvr_state::bios_ext2_ram_w)
+void midqslvr_state::bios_ext2_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (m_mtxc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled
{
@@ -561,7 +561,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext2_ram_w)
}
-WRITE32_MEMBER(midqslvr_state::bios_ext3_ram_w)
+void midqslvr_state::bios_ext3_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (m_mtxc_config_reg[0x5f] & 0x2) // write to RAM if this region is write-enabled
{
@@ -570,7 +570,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext3_ram_w)
}
-WRITE32_MEMBER(midqslvr_state::bios_ext4_ram_w)
+void midqslvr_state::bios_ext4_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (m_mtxc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled
{
@@ -579,7 +579,7 @@ WRITE32_MEMBER(midqslvr_state::bios_ext4_ram_w)
}
-WRITE32_MEMBER(midqslvr_state::bios_ram_w)
+void midqslvr_state::bios_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (m_mtxc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
{
diff --git a/src/mame/drivers/mil4000.cpp b/src/mame/drivers/mil4000.cpp
index dae480b375d..93db37c1e1e 100644
--- a/src/mame/drivers/mil4000.cpp
+++ b/src/mame/drivers/mil4000.cpp
@@ -164,16 +164,16 @@ private:
uint8_t m_mcucomm;
uint8_t m_mcudata;
- DECLARE_READ16_MEMBER(hvretrace_r);
- DECLARE_READ16_MEMBER(unk_r);
- DECLARE_READ16_MEMBER(chewheel_mcu_r);
- DECLARE_WRITE16_MEMBER(unk_w);
- DECLARE_WRITE16_MEMBER(chewheel_mcu_w);
- DECLARE_WRITE16_MEMBER(sc0_vram_w);
- DECLARE_WRITE16_MEMBER(sc1_vram_w);
- DECLARE_WRITE16_MEMBER(sc2_vram_w);
- DECLARE_WRITE16_MEMBER(sc3_vram_w);
- DECLARE_WRITE16_MEMBER(output_w);
+ uint16_t hvretrace_r();
+ uint16_t unk_r();
+ uint16_t chewheel_mcu_r();
+ void unk_w(offs_t offset, uint16_t data);
+ void chewheel_mcu_w(uint16_t data);
+ void sc0_vram_w(offs_t offset, uint16_t data);
+ void sc1_vram_w(offs_t offset, uint16_t data);
+ void sc2_vram_w(offs_t offset, uint16_t data);
+ void sc3_vram_w(offs_t offset, uint16_t data);
+ void output_w(uint16_t data);
TILE_GET_INFO_MEMBER(get_sc0_tile_info);
TILE_GET_INFO_MEMBER(get_sc1_tile_info);
@@ -268,7 +268,7 @@ uint32_t mil4000_state::screen_update(screen_device &screen, bitmap_ind16 &bitma
}
/*TODO*/
-READ16_MEMBER(mil4000_state::hvretrace_r)
+uint16_t mil4000_state::hvretrace_r()
{
uint16_t res;
@@ -289,25 +289,25 @@ READ16_MEMBER(mil4000_state::hvretrace_r)
}
-WRITE16_MEMBER(mil4000_state::sc0_vram_w)
+void mil4000_state::sc0_vram_w(offs_t offset, uint16_t data)
{
m_sc0_vram[offset] = data;
m_sc0_tilemap->mark_tile_dirty(offset/2);
}
-WRITE16_MEMBER(mil4000_state::sc1_vram_w)
+void mil4000_state::sc1_vram_w(offs_t offset, uint16_t data)
{
m_sc1_vram[offset] = data;
m_sc1_tilemap->mark_tile_dirty(offset/2);
}
-WRITE16_MEMBER(mil4000_state::sc2_vram_w)
+void mil4000_state::sc2_vram_w(offs_t offset, uint16_t data)
{
m_sc2_vram[offset] = data;
m_sc2_tilemap->mark_tile_dirty(offset/2);
}
-WRITE16_MEMBER(mil4000_state::sc3_vram_w)
+void mil4000_state::sc3_vram_w(offs_t offset, uint16_t data)
{
m_sc3_vram[offset] = data;
m_sc3_tilemap->mark_tile_dirty(offset/2);
@@ -325,7 +325,7 @@ WRITE16_MEMBER(mil4000_state::sc3_vram_w)
---- ---- ---- --x- Hold 2
---- ---- ---- ---x Hold 1
*/
-WRITE16_MEMBER(mil4000_state::output_w)
+void mil4000_state::output_w(uint16_t data)
{
for(int i = 0; i < 3; i++)
machine().bookkeeping().coin_counter_w(i, data & 0x2000);
@@ -336,7 +336,7 @@ WRITE16_MEMBER(mil4000_state::output_w)
// popmessage("%04x\n",data);
}
-READ16_MEMBER(mil4000_state::chewheel_mcu_r)
+uint16_t mil4000_state::chewheel_mcu_r()
{
/* Damn thing!
708010-708011 communicate with the MCU.
@@ -416,7 +416,7 @@ READ16_MEMBER(mil4000_state::chewheel_mcu_r)
return (machine().rand() & 0x0b); // otherwise got corrupt gfx...
}
-WRITE16_MEMBER(mil4000_state::chewheel_mcu_w)
+void mil4000_state::chewheel_mcu_w(uint16_t data)
{
if ((data == 0x11)||(data == 0x1a)||(data == 0x1b)||(data == 0x1c)||(data == 0x1d)||(data == 0x1e))
{
@@ -431,13 +431,13 @@ WRITE16_MEMBER(mil4000_state::chewheel_mcu_w)
}
-READ16_MEMBER(mil4000_state::unk_r)
+uint16_t mil4000_state::unk_r()
{
// reads: 51000C-0E. touch screen?
return 0xff;
}
-WRITE16_MEMBER(mil4000_state::unk_w)
+void mil4000_state::unk_w(offs_t offset, uint16_t data)
{
// writes: 510000-02-04-06-08-0A-0C-0E
// logerror("unknown writes from address %04x\n", offset);
diff --git a/src/mame/drivers/mirax.cpp b/src/mame/drivers/mirax.cpp
index 3c420db9e69..e92f71cf7ef 100644
--- a/src/mame/drivers/mirax.cpp
+++ b/src/mame/drivers/mirax.cpp
@@ -150,15 +150,15 @@ private:
uint8_t m_flipscreen_x;
uint8_t m_flipscreen_y;
- DECLARE_WRITE8_MEMBER(audio_w);
+ void audio_w(offs_t offset, uint8_t data);
DECLARE_WRITE_LINE_MEMBER(nmi_mask_w);
- DECLARE_WRITE8_MEMBER(sound_cmd_w);
+ void sound_cmd_w(uint8_t data);
DECLARE_WRITE_LINE_MEMBER(coin_counter0_w);
DECLARE_WRITE_LINE_MEMBER(coin_counter1_w);
DECLARE_WRITE_LINE_MEMBER(flip_screen_x_w);
DECLARE_WRITE_LINE_MEMBER(flip_screen_y_w);
- DECLARE_WRITE8_MEMBER(ay1_sel);
- DECLARE_WRITE8_MEMBER(ay2_sel);
+ void ay1_sel(uint8_t data);
+ void ay2_sel(uint8_t data);
void mirax_palette(palette_device &palette) const;
@@ -270,18 +270,18 @@ void mirax_state::machine_start()
save_item(NAME(m_flipscreen_y));
}
-WRITE8_MEMBER(mirax_state::audio_w)
+void mirax_state::audio_w(offs_t offset, uint8_t data)
{
m_nAyCtrl=offset;
}
-WRITE8_MEMBER(mirax_state::ay1_sel)
+void mirax_state::ay1_sel(uint8_t data)
{
m_ay[0]->address_w(m_nAyCtrl);
m_ay[0]->data_w(data);
}
-WRITE8_MEMBER(mirax_state::ay2_sel)
+void mirax_state::ay2_sel(uint8_t data)
{
m_ay[1]->address_w(m_nAyCtrl);
m_ay[1]->data_w(data);
@@ -294,7 +294,7 @@ WRITE_LINE_MEMBER(mirax_state::nmi_mask_w)
m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
}
-WRITE8_MEMBER(mirax_state::sound_cmd_w)
+void mirax_state::sound_cmd_w(uint8_t data)
{
m_soundlatch->write(data & 0xff);
m_audiocpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
diff --git a/src/mame/drivers/missile.cpp b/src/mame/drivers/missile.cpp
index 51729fe4949..ca2f756d1c4 100644
--- a/src/mame/drivers/missile.cpp
+++ b/src/mame/drivers/missile.cpp
@@ -391,10 +391,10 @@ public:
DECLARE_READ_LINE_MEMBER(vblank_r);
private:
- DECLARE_WRITE8_MEMBER(missile_w);
- DECLARE_READ8_MEMBER(missile_r);
- DECLARE_WRITE8_MEMBER(bootleg_w);
- DECLARE_READ8_MEMBER(bootleg_r);
+ void missile_w(address_space &space, offs_t offset, uint8_t data);
+ uint8_t missile_r(address_space &space, offs_t offset);
+ void bootleg_w(address_space &space, offs_t offset, uint8_t data);
+ uint8_t bootleg_r(address_space &space, offs_t offset);
uint32_t screen_update_missile(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
inline int scanline_to_v(int scanline);
@@ -723,7 +723,7 @@ uint32_t missile_state::screen_update_missile(screen_device &screen, bitmap_ind1
*
*************************************/
-WRITE8_MEMBER(missile_state::missile_w)
+void missile_state::missile_w(address_space &space, offs_t offset, uint8_t data)
{
/* if this is a MADSEL cycle, write to video RAM */
if (get_madsel())
@@ -782,7 +782,7 @@ WRITE8_MEMBER(missile_state::missile_w)
}
-READ8_MEMBER(missile_state::missile_r)
+uint8_t missile_state::missile_r(address_space &space, offs_t offset)
{
uint8_t result = 0xff;
@@ -843,7 +843,7 @@ READ8_MEMBER(missile_state::missile_r)
}
-WRITE8_MEMBER(missile_state::bootleg_w)
+void missile_state::bootleg_w(address_space &space, offs_t offset, uint8_t data)
{
/* if this is a MADSEL cycle, write to video RAM */
if (get_madsel())
@@ -895,7 +895,7 @@ WRITE8_MEMBER(missile_state::bootleg_w)
}
-READ8_MEMBER(missile_state::bootleg_r)
+uint8_t missile_state::bootleg_r(address_space &space, offs_t offset)
{
uint8_t result = 0xff;
diff --git a/src/mame/drivers/mjsenpu.cpp b/src/mame/drivers/mjsenpu.cpp
index 697afbaa279..f38ca081012 100644
--- a/src/mame/drivers/mjsenpu.cpp
+++ b/src/mame/drivers/mjsenpu.cpp
@@ -83,21 +83,21 @@ private:
uint8_t m_control;
uint8_t m_mux;
- DECLARE_READ8_MEMBER(palette_low_r);
- DECLARE_READ8_MEMBER(palette_high_r);
- DECLARE_WRITE8_MEMBER(palette_low_w);
- DECLARE_WRITE8_MEMBER(palette_high_w);
+ uint8_t palette_low_r(offs_t offset);
+ uint8_t palette_high_r(offs_t offset);
+ void palette_low_w(offs_t offset, uint8_t data);
+ void palette_high_w(offs_t offset, uint8_t data);
void set_palette(int offset);
- DECLARE_WRITE8_MEMBER(control_w);
- DECLARE_WRITE8_MEMBER(mux_w);
+ void control_w(uint8_t data);
+ void mux_w(uint8_t data);
- DECLARE_READ32_MEMBER(muxed_inputs_r);
+ uint32_t muxed_inputs_r();
- DECLARE_READ32_MEMBER(mjsenpu_speedup_r);
+ uint32_t mjsenpu_speedup_r();
- DECLARE_READ32_MEMBER(vram_r);
- DECLARE_WRITE32_MEMBER(vram_w);
+ uint32_t vram_r(offs_t offset);
+ void vram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
virtual void machine_start() override;
virtual void machine_reset() override;
@@ -110,13 +110,13 @@ private:
};
-READ8_MEMBER(mjsenpu_state::palette_low_r)
+uint8_t mjsenpu_state::palette_low_r(offs_t offset)
{
return m_pal[(offset * 2) + 0];
}
-READ8_MEMBER(mjsenpu_state::palette_high_r)
+uint8_t mjsenpu_state::palette_high_r(offs_t offset)
{
return m_pal[(offset * 2) + 1];
}
@@ -127,32 +127,32 @@ void mjsenpu_state::set_palette(int offset)
m_palette->set_pen_color(offset, pal5bit(paldata >> 0), pal5bit(paldata >> 5), pal6bit(paldata >> 10));
}
-WRITE8_MEMBER(mjsenpu_state::palette_low_w)
+void mjsenpu_state::palette_low_w(offs_t offset, uint8_t data)
{
m_pal[(offset * 2)+0] = data;
set_palette(offset);
}
-WRITE8_MEMBER(mjsenpu_state::palette_high_w)
+void mjsenpu_state::palette_high_w(offs_t offset, uint8_t data)
{
m_pal[(offset * 2)+1] = data;
set_palette(offset);
}
-READ32_MEMBER(mjsenpu_state::vram_r)
+uint32_t mjsenpu_state::vram_r(offs_t offset)
{
if (m_control & 0x01) return m_vram1[offset];
else return m_vram0[offset];
}
-WRITE32_MEMBER(mjsenpu_state::vram_w)
+void mjsenpu_state::vram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (m_control & 0x01) COMBINE_DATA(&m_vram1[offset]);
else COMBINE_DATA(&m_vram0[offset]);
}
-WRITE8_MEMBER(mjsenpu_state::control_w)
+void mjsenpu_state::control_w(uint8_t data)
{
// bit 0x80 is always set? (sometimes disabled during screen transitions briefly, could be display enable?)
@@ -177,7 +177,7 @@ WRITE8_MEMBER(mjsenpu_state::control_w)
// printf("control_w %02x\n", data);
}
-WRITE8_MEMBER(mjsenpu_state::mux_w)
+void mjsenpu_state::mux_w(uint8_t data)
{
if ((data != 0x80) &&
(data != 0x9e) &&
@@ -190,7 +190,7 @@ WRITE8_MEMBER(mjsenpu_state::mux_w)
m_mux = data;
}
-READ32_MEMBER(mjsenpu_state::muxed_inputs_r)
+uint32_t mjsenpu_state::muxed_inputs_r()
{
switch (m_mux)
{
@@ -506,7 +506,7 @@ ROM_END
-READ32_MEMBER(mjsenpu_state::mjsenpu_speedup_r)
+uint32_t mjsenpu_state::mjsenpu_speedup_r()
{
int pc = m_maincpu->pc();
@@ -538,7 +538,7 @@ void mjsenpu_state::init_mjsenpu()
(loops for 744256 instructions)
*/
// not especially effective, might be wrong.
- m_maincpu->space(AS_PROGRAM).install_read_handler(0x23468, 0x2346b, read32_delegate(*this, FUNC(mjsenpu_state::mjsenpu_speedup_r)));
+ m_maincpu->space(AS_PROGRAM).install_read_handler(0x23468, 0x2346b, read32smo_delegate(*this, FUNC(mjsenpu_state::mjsenpu_speedup_r)));
}
diff --git a/src/mame/drivers/mjsister.cpp b/src/mame/drivers/mjsister.cpp
index b9eabf8fbac..79ea31be2ae 100644
--- a/src/mame/drivers/mjsister.cpp
+++ b/src/mame/drivers/mjsister.cpp
@@ -76,8 +76,8 @@ private:
required_memory_bank m_rombank;
required_memory_bank m_vrambank;
std::unique_ptr<uint8_t[]> m_vram;
- DECLARE_WRITE8_MEMBER(dac_adr_s_w);
- DECLARE_WRITE8_MEMBER(dac_adr_e_w);
+ void dac_adr_s_w(uint8_t data);
+ void dac_adr_e_w(uint8_t data);
DECLARE_WRITE_LINE_MEMBER(rombank_w);
DECLARE_WRITE_LINE_MEMBER(flip_screen_w);
DECLARE_WRITE_LINE_MEMBER(colorbank_w);
@@ -86,9 +86,9 @@ private:
DECLARE_WRITE_LINE_MEMBER(vrambank_w);
DECLARE_WRITE_LINE_MEMBER(dac_bank_w);
DECLARE_WRITE_LINE_MEMBER(coin_counter_w);
- DECLARE_WRITE8_MEMBER(input_sel1_w);
- DECLARE_WRITE8_MEMBER(input_sel2_w);
- DECLARE_READ8_MEMBER(keys_r);
+ void input_sel1_w(uint8_t data);
+ void input_sel2_w(uint8_t data);
+ uint8_t keys_r();
TIMER_CALLBACK_MEMBER(dac_callback);
INTERRUPT_GEN_MEMBER(interrupt);
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
@@ -185,12 +185,12 @@ TIMER_CALLBACK_MEMBER(mjsister_state::dac_callback)
m_dac_busy = 0;
}
-WRITE8_MEMBER(mjsister_state::dac_adr_s_w)
+void mjsister_state::dac_adr_s_w(uint8_t data)
{
m_dac_adr_s = data;
}
-WRITE8_MEMBER(mjsister_state::dac_adr_e_w)
+void mjsister_state::dac_adr_e_w(uint8_t data)
{
m_dac_adr_e = data;
m_dac_adr = m_dac_adr_s << 8;
@@ -243,17 +243,17 @@ WRITE_LINE_MEMBER(mjsister_state::coin_counter_w)
machine().bookkeeping().coin_counter_w(0, state);
}
-WRITE8_MEMBER(mjsister_state::input_sel1_w)
+void mjsister_state::input_sel1_w(uint8_t data)
{
m_input_sel1 = data;
}
-WRITE8_MEMBER(mjsister_state::input_sel2_w)
+void mjsister_state::input_sel2_w(uint8_t data)
{
m_input_sel2 = data;
}
-READ8_MEMBER(mjsister_state::keys_r)
+uint8_t mjsister_state::keys_r()
{
int p, i, ret = 0;
static const char *const keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4", "KEY5" };
diff --git a/src/mame/drivers/mmd1.cpp b/src/mame/drivers/mmd1.cpp
index 72516511c82..c04f6967165 100644
--- a/src/mame/drivers/mmd1.cpp
+++ b/src/mame/drivers/mmd1.cpp
@@ -103,11 +103,11 @@ protected:
virtual void machine_reset() override;
private:
- DECLARE_WRITE8_MEMBER(port00_w);
- DECLARE_WRITE8_MEMBER(port01_w);
- DECLARE_WRITE8_MEMBER(port02_w);
- DECLARE_READ8_MEMBER(keyboard_r);
- DECLARE_READ8_MEMBER(port13_r);
+ void port00_w(uint8_t data);
+ void port01_w(uint8_t data);
+ void port02_w(uint8_t data);
+ uint8_t keyboard_r();
+ uint8_t port13_r();
DECLARE_READ_LINE_MEMBER(si);
DECLARE_WRITE_LINE_MEMBER(so);
TIMER_DEVICE_CALLBACK_MEMBER(kansas_r);
@@ -128,7 +128,7 @@ private:
};
-WRITE8_MEMBER( mmd1_state::port00_w )
+void mmd1_state::port00_w(uint8_t data)
{
m_p[0][7] = BIT(data,7) ? 0 : 1;
m_p[0][6] = BIT(data,6) ? 0 : 1;
@@ -140,7 +140,7 @@ WRITE8_MEMBER( mmd1_state::port00_w )
m_p[0][0] = BIT(data,0) ? 0 : 1;
}
-WRITE8_MEMBER( mmd1_state::port01_w )
+void mmd1_state::port01_w(uint8_t data)
{
m_p[1][7] = BIT(data,7) ? 0 : 1;
m_p[1][6] = BIT(data,6) ? 0 : 1;
@@ -152,7 +152,7 @@ WRITE8_MEMBER( mmd1_state::port01_w )
m_p[1][0] = BIT(data,0) ? 0 : 1;
}
-WRITE8_MEMBER( mmd1_state::port02_w )
+void mmd1_state::port02_w(uint8_t data)
{
m_p[2][7] = BIT(data,7) ? 0 : 1;
m_p[2][6] = BIT(data,6) ? 0 : 1;
@@ -165,7 +165,7 @@ WRITE8_MEMBER( mmd1_state::port02_w )
}
// keyboard has a keydown and a keyup code. Keyup = last keydown + bit 7 set
-READ8_MEMBER( mmd1_state::keyboard_r )
+uint8_t mmd1_state::keyboard_r()
{
uint8_t line1 = ioport("LINE1")->read();
uint8_t line2 = ioport("LINE2")->read();
@@ -193,7 +193,7 @@ READ8_MEMBER( mmd1_state::keyboard_r )
return m_return_code;
}
-READ8_MEMBER(mmd1_state::port13_r)
+uint8_t mmd1_state::port13_r()
{
u8 data = 0xfa;
data |= m_uart->dav_r() ? 1 : 0;
diff --git a/src/mame/drivers/mmd2.cpp b/src/mame/drivers/mmd2.cpp
index 6f2f8254b01..ad8d50189c2 100644
--- a/src/mame/drivers/mmd2.cpp
+++ b/src/mame/drivers/mmd2.cpp
@@ -133,7 +133,7 @@ private:
void port05_w(uint8_t data);
uint8_t port01_r();
uint8_t port13_r();
- DECLARE_READ8_MEMBER(bank_r);
+ uint8_t bank_r(address_space &space, offs_t offset);
uint8_t keyboard_r();
void scanlines_w(uint8_t data);
void digit_w(uint8_t data);
@@ -288,7 +288,7 @@ C D E F MEM REGS AUX CANCEL
*/
-READ8_MEMBER( mmd2_state::bank_r )
+uint8_t mmd2_state::bank_r(address_space &space, offs_t offset)
{
for (auto &bank : m_banks)
bank->set_entry(offset);
diff --git a/src/mame/drivers/mpu4vid.cpp b/src/mame/drivers/mpu4vid.cpp
index abe00bc44b4..9f493fa7131 100644
--- a/src/mame/drivers/mpu4vid.cpp
+++ b/src/mame/drivers/mpu4vid.cpp
@@ -293,16 +293,16 @@ private:
uint8_t pia_ic5_porta_track_r();
void mpu4vid_char_cheat( int address);
DECLARE_WRITE_LINE_MEMBER(update_mpu68_interrupts);
- DECLARE_READ16_MEMBER( mpu4_vid_vidram_r );
- DECLARE_WRITE16_MEMBER( mpu4_vid_vidram_w );
+ uint16_t mpu4_vid_vidram_r(offs_t offset);
+ void mpu4_vid_vidram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
EF9369_COLOR_UPDATE(ef9369_color_update);
- DECLARE_WRITE8_MEMBER( bt471_w );
- DECLARE_READ8_MEMBER( bt471_r );
- DECLARE_WRITE8_MEMBER( vidcharacteriser_w );
- DECLARE_READ8_MEMBER( vidcharacteriser_r );
+ void bt471_w(offs_t offset, uint8_t data);
+ uint8_t bt471_r(offs_t offset);
+ void vidcharacteriser_w(offs_t offset, uint8_t data);
+ uint8_t vidcharacteriser_r(offs_t offset);
DECLARE_WRITE_LINE_MEMBER(mpu_video_reset);
- DECLARE_WRITE8_MEMBER( vram_w );
- DECLARE_READ8_MEMBER( vram_r );
+ void vram_w(offs_t offset, uint8_t data);
+ uint8_t vram_r(offs_t offset);
void bwbvid5_68k_map(address_map &map);
void bwbvid_68k_map(address_map &map);
@@ -395,12 +395,12 @@ static const gfx_layout mpu4_vid_char_8x8_layout =
8*32
};
-WRITE8_MEMBER(mpu4vid_state::vram_w)
+void mpu4vid_state::vram_w(offs_t offset, uint8_t data)
{
m_vid_mainram[offset] = data | (m_vid_mainram[offset] & 0xff00);
}
-READ8_MEMBER(mpu4vid_state::vram_r)
+uint8_t mpu4vid_state::vram_r(offs_t offset)
{
return m_vid_mainram[offset];
}
@@ -423,13 +423,13 @@ SCN2674_DRAW_CHARACTER_MEMBER(mpu4vid_state::display_pixels)
}
-READ16_MEMBER(mpu4vid_state::mpu4_vid_vidram_r )
+uint16_t mpu4vid_state::mpu4_vid_vidram_r(offs_t offset)
{
return m_vid_vidram[offset];
}
-WRITE16_MEMBER(mpu4vid_state::mpu4_vid_vidram_w )
+void mpu4vid_state::mpu4_vid_vidram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_vid_vidram[offset]);
offset <<= 1;
@@ -476,7 +476,7 @@ EF9369_COLOR_UPDATE( mpu4vid_state::ef9369_color_update )
* 1 0 1 Overlay register
*/
-WRITE8_MEMBER(mpu4vid_state::bt471_w )
+void mpu4vid_state::bt471_w(offs_t offset, uint8_t data)
{
struct bt471_t &bt471 = m_bt471;
@@ -518,7 +518,7 @@ WRITE8_MEMBER(mpu4vid_state::bt471_w )
}
}
-READ8_MEMBER(mpu4vid_state::bt471_r )
+uint8_t mpu4vid_state::bt471_r(offs_t offset)
{
popmessage("Bt471: Unhandled read access (offset:%x)", offset);
return 0;
@@ -1385,7 +1385,7 @@ Characteriser (CHR)
the 'challenge' part of the startup check is always the same
*/
-WRITE8_MEMBER(mpu4vid_state::vidcharacteriser_w )
+void mpu4vid_state::vidcharacteriser_w(offs_t offset, uint8_t data)
{
int x;
int call=(data&0xff);
@@ -1416,7 +1416,7 @@ WRITE8_MEMBER(mpu4vid_state::vidcharacteriser_w )
}
-READ8_MEMBER(mpu4vid_state::vidcharacteriser_r )
+uint8_t mpu4vid_state::vidcharacteriser_r(offs_t offset)
{
LOG_CHR_FULL(("%04x Characteriser read offset %02X,data %02X", m_videocpu->pcbase(),offset,m_current_chr_table[m_prot_col].response));
LOG_CHR(("Characteriser read offset %02X \n",offset));
diff --git a/src/mame/drivers/mrgame.cpp b/src/mame/drivers/mrgame.cpp
index 3b85d3b7066..fb8a41e647b 100644
--- a/src/mame/drivers/mrgame.cpp
+++ b/src/mame/drivers/mrgame.cpp
@@ -78,24 +78,24 @@ protected:
private:
void mrgame_palette(palette_device &palette) const;
- DECLARE_WRITE8_MEMBER(ack1_w);
- DECLARE_WRITE8_MEMBER(ack2_w);
+ void ack1_w(uint8_t data);
+ void ack2_w(uint8_t data);
void portb_w(uint8_t data);
- DECLARE_WRITE8_MEMBER(row_w);
- DECLARE_WRITE8_MEMBER(sound_w);
- DECLARE_WRITE8_MEMBER(triple_w);
- DECLARE_WRITE8_MEMBER(video_w);
+ void row_w(uint8_t data);
+ void sound_w(uint8_t data);
+ void triple_w(uint8_t data);
+ void video_w(uint8_t data);
DECLARE_WRITE_LINE_MEMBER(video_a11_w);
DECLARE_WRITE_LINE_MEMBER(video_a12_w);
DECLARE_WRITE_LINE_MEMBER(video_a13_w);
DECLARE_WRITE_LINE_MEMBER(intst_w);
DECLARE_WRITE_LINE_MEMBER(nmi_intst_w);
DECLARE_WRITE_LINE_MEMBER(flip_w);
- DECLARE_READ8_MEMBER(col_r);
- DECLARE_READ8_MEMBER(sound_r);
+ uint8_t col_r();
+ uint8_t sound_r();
uint8_t porta_r();
uint8_t portc_r();
- DECLARE_READ8_MEMBER(rsw_r);
+ uint8_t rsw_r();
DECLARE_WRITE_LINE_MEMBER(vblank_int_w);
DECLARE_WRITE_LINE_MEMBER(vblank_nmi_w);
TIMER_DEVICE_CALLBACK_MEMBER(irq_timer);
@@ -255,13 +255,13 @@ static INPUT_PORTS_START( mrgame )
PORT_BIT( 0xe9, IP_ACTIVE_LOW, IPT_UNUSED )
INPUT_PORTS_END
-READ8_MEMBER(mrgame_state::rsw_r)
+uint8_t mrgame_state::rsw_r()
{
return m_io_dsw0->read() | ((uint8_t)m_ack1 << 5) | ((uint8_t)m_ack2 << 4);
}
// this is like a keyboard, energise a row and read the column data
-READ8_MEMBER(mrgame_state::col_r)
+uint8_t mrgame_state::col_r()
{
if (m_row_data == 0)
return m_io_x0->read();
@@ -276,17 +276,17 @@ READ8_MEMBER(mrgame_state::col_r)
return 0xff;
}
-WRITE8_MEMBER(mrgame_state::row_w)
+void mrgame_state::row_w(uint8_t data)
{
m_row_data = data & 7;
}
-READ8_MEMBER(mrgame_state::sound_r)
+uint8_t mrgame_state::sound_r()
{
return m_sound_data;
}
-WRITE8_MEMBER(mrgame_state::sound_w)
+void mrgame_state::sound_w(uint8_t data)
{
m_sound_data = data;
m_audiocpu1->set_input_line(INPUT_LINE_NMI, BIT(data, 7) ? CLEAR_LINE : ASSERT_LINE);
@@ -294,13 +294,13 @@ WRITE8_MEMBER(mrgame_state::sound_w)
}
// this produces 24 outputs from three driver chips to drive lamps & solenoids
-WRITE8_MEMBER(mrgame_state::triple_w)
+void mrgame_state::triple_w(uint8_t data)
{
if ((data & 0x18)==0)
m_ackv = BIT(data, 7);
}
-WRITE8_MEMBER(mrgame_state::video_w)
+void mrgame_state::video_w(uint8_t data)
{
m_video_data = data;
}
@@ -339,12 +339,12 @@ WRITE_LINE_MEMBER(mrgame_state::flip_w)
m_flip = state;
}
-WRITE8_MEMBER(mrgame_state::ack1_w)
+void mrgame_state::ack1_w(uint8_t data)
{
m_ack1 = BIT(data, 0);
}
-WRITE8_MEMBER(mrgame_state::ack2_w)
+void mrgame_state::ack2_w(uint8_t data)
{
m_ack2 = BIT(data, 0);
}
diff --git a/src/mame/drivers/mstation.cpp b/src/mame/drivers/mstation.cpp
index 6b94979380b..b23bffee035 100644
--- a/src/mame/drivers/mstation.cpp
+++ b/src/mame/drivers/mstation.cpp
@@ -73,27 +73,27 @@ private:
uint8_t m_irq;
uint16_t m_kb_matrix;
- DECLARE_READ8_MEMBER( modem_r );
- DECLARE_WRITE8_MEMBER( modem_w );
+ uint8_t modem_r();
+ void modem_w(uint8_t data);
void lcd_w(uint16_t offset, int column, uint8_t data);
uint8_t lcd_r(uint16_t offset, int column);
- DECLARE_READ8_MEMBER( lcd_right_r );
- DECLARE_WRITE8_MEMBER( lcd_right_w );
- DECLARE_READ8_MEMBER( lcd_left_r );
- DECLARE_WRITE8_MEMBER( lcd_left_w );
-
- DECLARE_READ8_MEMBER( bank1_r );
- DECLARE_WRITE8_MEMBER( bank1_w );
- DECLARE_READ8_MEMBER( bank2_r );
- DECLARE_WRITE8_MEMBER( bank2_w );
-
- DECLARE_READ8_MEMBER( battery_status_r );
- DECLARE_WRITE8_MEMBER( port2_w );
- DECLARE_READ8_MEMBER( kb_r );
- DECLARE_WRITE8_MEMBER( kb_w );
- DECLARE_READ8_MEMBER( irq_r );
- DECLARE_WRITE8_MEMBER( irq_w );
+ uint8_t lcd_right_r(offs_t offset);
+ void lcd_right_w(offs_t offset, uint8_t data);
+ uint8_t lcd_left_r(offs_t offset);
+ void lcd_left_w(offs_t offset, uint8_t data);
+
+ uint8_t bank1_r(offs_t offset);
+ void bank1_w(offs_t offset, uint8_t data);
+ uint8_t bank2_r(offs_t offset);
+ void bank2_w(offs_t offset, uint8_t data);
+
+ uint8_t battery_status_r();
+ void port2_w(uint8_t data);
+ uint8_t kb_r();
+ void kb_w(uint8_t data);
+ uint8_t irq_r();
+ void irq_w(uint8_t data);
void refresh_ints();
DECLARE_WRITE_LINE_MEMBER( rtc_irq );
@@ -108,12 +108,12 @@ private:
};
-READ8_MEMBER( mstation_state::modem_r )
+uint8_t mstation_state::modem_r()
{
return 0xff;
}
-WRITE8_MEMBER( mstation_state::modem_w )
+void mstation_state::modem_w(uint8_t data)
{
}
@@ -138,10 +138,10 @@ uint8_t mstation_state::lcd_r(uint16_t offset, int column)
return m_screen_column % 20;
}
-READ8_MEMBER ( mstation_state::lcd_left_r ) { return lcd_r(offset, m_screen_column); }
-WRITE8_MEMBER( mstation_state::lcd_left_w ) { lcd_w(offset, m_screen_column, data); }
-READ8_MEMBER ( mstation_state::lcd_right_r ) { return lcd_r(offset, m_screen_column + 20); }
-WRITE8_MEMBER( mstation_state::lcd_right_w ) { lcd_w(offset, m_screen_column + 20, data); }
+uint8_t mstation_state::lcd_left_r(offs_t offset) { return lcd_r(offset, m_screen_column); }
+void mstation_state::lcd_left_w(offs_t offset, uint8_t data) { lcd_w(offset, m_screen_column, data); }
+uint8_t mstation_state::lcd_right_r(offs_t offset) { return lcd_r(offset, m_screen_column + 20); }
+void mstation_state::lcd_right_w(offs_t offset, uint8_t data) { lcd_w(offset, m_screen_column + 20, data); }
uint32_t mstation_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
@@ -166,24 +166,24 @@ uint32_t mstation_state::screen_update(screen_device &screen, bitmap_ind16 &bitm
// Bankswitch
//***************************************************************************/
-READ8_MEMBER( mstation_state::bank1_r )
+uint8_t mstation_state::bank1_r(offs_t offset)
{
return m_bank1[offset];
}
-READ8_MEMBER( mstation_state::bank2_r )
+uint8_t mstation_state::bank2_r(offs_t offset)
{
return m_bank2[offset];
}
-WRITE8_MEMBER( mstation_state::bank1_w )
+void mstation_state::bank1_w(offs_t offset, uint8_t data)
{
m_bank1[offset] = data;
m_bankdev1->set_bank(((m_bank1[1] & 0x07) << 8) | m_bank1[0]);
}
-WRITE8_MEMBER( mstation_state::bank2_w )
+void mstation_state::bank2_w(offs_t offset, uint8_t data)
{
m_bank2[offset] = data;
@@ -192,7 +192,7 @@ WRITE8_MEMBER( mstation_state::bank2_w )
-WRITE8_MEMBER( mstation_state::port2_w )
+void mstation_state::port2_w(uint8_t data)
{
m_port2 = data;
@@ -220,19 +220,19 @@ void mstation_state::refresh_ints()
m_maincpu->set_input_line(0, CLEAR_LINE);
}
-READ8_MEMBER( mstation_state::irq_r )
+uint8_t mstation_state::irq_r()
{
return m_irq;
}
-WRITE8_MEMBER( mstation_state::irq_w )
+void mstation_state::irq_w(uint8_t data)
{
m_irq &= data;
refresh_ints();
}
-READ8_MEMBER( mstation_state::battery_status_r )
+uint8_t mstation_state::battery_status_r()
{
/*
bit 0-3 - unknown
@@ -241,12 +241,12 @@ READ8_MEMBER( mstation_state::battery_status_r )
return 0xf0;
}
-WRITE8_MEMBER( mstation_state::kb_w )
+void mstation_state::kb_w(uint8_t data)
{
m_kb_matrix = (m_kb_matrix & 0x300) | data;
}
-READ8_MEMBER( mstation_state::kb_r )
+uint8_t mstation_state::kb_r()
{
uint8_t data = 0xff;
diff --git a/src/mame/drivers/multi8.cpp b/src/mame/drivers/multi8.cpp
index fb3cc491f37..05609efb6ec 100644
--- a/src/mame/drivers/multi8.cpp
+++ b/src/mame/drivers/multi8.cpp
@@ -52,20 +52,20 @@ public:
void multi8(machine_config &config);
private:
- DECLARE_READ8_MEMBER(key_input_r);
- DECLARE_READ8_MEMBER(key_status_r);
- DECLARE_READ8_MEMBER(vram_r);
- DECLARE_WRITE8_MEMBER(vram_w);
- DECLARE_READ8_MEMBER(pal_r);
- DECLARE_WRITE8_MEMBER(pal_w);
- DECLARE_READ8_MEMBER(kanji_r);
- DECLARE_WRITE8_MEMBER(kanji_w);
+ uint8_t key_input_r();
+ uint8_t key_status_r();
+ uint8_t vram_r(offs_t offset);
+ void vram_w(offs_t offset, uint8_t data);
+ uint8_t pal_r(offs_t offset);
+ void pal_w(offs_t offset, uint8_t data);
+ uint8_t kanji_r(offs_t offset);
+ void kanji_w(offs_t offset, uint8_t data);
uint8_t porta_r();
void portb_w(uint8_t data);
void portc_w(uint8_t data);
void ym2203_porta_w(uint8_t data);
- DECLARE_READ8_MEMBER(ay8912_0_r);
- DECLARE_READ8_MEMBER(ay8912_1_r);
+ uint8_t ay8912_0_r();
+ uint8_t ay8912_1_r();
TIMER_DEVICE_CALLBACK_MEMBER(keyboard_callback);
TIMER_DEVICE_CALLBACK_MEMBER(kansas_r);
DECLARE_WRITE_LINE_MEMBER(kansas_w);
@@ -189,7 +189,7 @@ MC6845_UPDATE_ROW( multi8_state::crtc_update_row )
}
}
-READ8_MEMBER( multi8_state::key_input_r )
+uint8_t multi8_state::key_input_r()
{
if (m_mcu_init == 0)
{
@@ -202,7 +202,7 @@ READ8_MEMBER( multi8_state::key_input_r )
return m_keyb_press;
}
-READ8_MEMBER( multi8_state::key_status_r )
+uint8_t multi8_state::key_status_r()
{
if (m_mcu_init == 0)
return 1;
@@ -222,7 +222,7 @@ READ8_MEMBER( multi8_state::key_status_r )
return m_keyb_press_flag | (m_shift_press_flag << 7);
}
-READ8_MEMBER( multi8_state::vram_r )
+uint8_t multi8_state::vram_r(offs_t offset)
{
uint8_t res;
@@ -246,7 +246,7 @@ READ8_MEMBER( multi8_state::vram_r )
return res;
}
-WRITE8_MEMBER( multi8_state::vram_w )
+void multi8_state::vram_w(offs_t offset, uint8_t data)
{
if (!BIT(m_vram_bank, 4)) //select plain work ram
{
@@ -267,12 +267,12 @@ WRITE8_MEMBER( multi8_state::vram_w )
m_p_vram[offset | 0xc000] = data;
}
-READ8_MEMBER( multi8_state::pal_r )
+uint8_t multi8_state::pal_r(offs_t offset)
{
return m_pen_clut[offset];
}
-WRITE8_MEMBER( multi8_state::pal_w )
+void multi8_state::pal_w(offs_t offset, uint8_t data)
{
m_pen_clut[offset] = data;
@@ -288,15 +288,15 @@ WRITE8_MEMBER( multi8_state::pal_w )
}
}
-READ8_MEMBER(multi8_state::ay8912_0_r){ return m_aysnd->data_r(); }
-READ8_MEMBER(multi8_state::ay8912_1_r){ return m_aysnd->data_r(); }
+uint8_t multi8_state::ay8912_0_r(){ return m_aysnd->data_r(); }
+uint8_t multi8_state::ay8912_1_r(){ return m_aysnd->data_r(); }
-READ8_MEMBER( multi8_state::kanji_r )
+uint8_t multi8_state::kanji_r(offs_t offset)
{
return m_p_kanji[(m_knj_addr << 1) | (offset & 1)];
}
-WRITE8_MEMBER( multi8_state::kanji_w )
+void multi8_state::kanji_w(offs_t offset, uint8_t data)
{
m_knj_addr = (offset == 0) ? (m_knj_addr & 0xff00) | (data & 0xff) : (m_knj_addr & 0x00ff) | (data << 8);
}
diff --git a/src/mame/drivers/multigam.cpp b/src/mame/drivers/multigam.cpp
index cac9ad1c0e8..1c451b4033f 100644
--- a/src/mame/drivers/multigam.cpp
+++ b/src/mame/drivers/multigam.cpp
@@ -184,23 +184,23 @@ private:
uint8_t m_supergm3_prg_bank;
uint8_t m_supergm3_chr_bank;
- DECLARE_WRITE8_MEMBER(multigam_nt_w);
- DECLARE_READ8_MEMBER(multigam_nt_r);
- DECLARE_WRITE8_MEMBER(sprite_dma_w);
- DECLARE_READ8_MEMBER(multigam_IN0_r);
- DECLARE_WRITE8_MEMBER(multigam_IN0_w);
- DECLARE_READ8_MEMBER(multigam_IN1_r);
- DECLARE_WRITE8_MEMBER(multigam_switch_prg_rom);
- DECLARE_WRITE8_MEMBER(multigam_switch_gfx_rom);
- DECLARE_WRITE8_MEMBER(multigam_mapper2_w);
- DECLARE_WRITE8_MEMBER(multigam3_mmc3_rom_switch_w);
- DECLARE_WRITE8_MEMBER(multigm3_mapper2_w);
- DECLARE_WRITE8_MEMBER(multigm3_switch_gfx_rom);
- DECLARE_WRITE8_MEMBER(multigm3_switch_prg_rom);
- DECLARE_WRITE8_MEMBER(multigam3_mapper02_rom_switch_w);
- DECLARE_WRITE8_MEMBER(mmc1_rom_switch_w);
- DECLARE_WRITE8_MEMBER(supergm3_prg_bank_w);
- DECLARE_WRITE8_MEMBER(supergm3_chr_bank_w);
+ void multigam_nt_w(offs_t offset, uint8_t data);
+ uint8_t multigam_nt_r(offs_t offset);
+ void sprite_dma_w(address_space &space, uint8_t data);
+ uint8_t multigam_IN0_r();
+ void multigam_IN0_w(uint8_t data);
+ uint8_t multigam_IN1_r();
+ void multigam_switch_prg_rom(uint8_t data);
+ void multigam_switch_gfx_rom(uint8_t data);
+ void multigam_mapper2_w(offs_t offset, uint8_t data);
+ void multigam3_mmc3_rom_switch_w(offs_t offset, uint8_t data);
+ void multigm3_mapper2_w(offs_t offset, uint8_t data);
+ void multigm3_switch_gfx_rom(uint8_t data);
+ void multigm3_switch_prg_rom(address_space &space, uint8_t data);
+ void multigam3_mapper02_rom_switch_w(uint8_t data);
+ void mmc1_rom_switch_w(offs_t offset, uint8_t data);
+ void supergm3_prg_bank_w(uint8_t data);
+ void supergm3_chr_bank_w(uint8_t data);
void set_mirroring(int mirroring);
DECLARE_MACHINE_START(multigm3);
DECLARE_MACHINE_RESET(multigm3);
@@ -260,14 +260,14 @@ void multigam_state::set_mirroring(int mirroring)
}
}
-WRITE8_MEMBER(multigam_state::multigam_nt_w)
+void multigam_state::multigam_nt_w(offs_t offset, uint8_t data)
{
int page = ((offset & 0xc00) >> 10);
m_nt_page[page][offset & 0x3ff] = data;
}
-READ8_MEMBER(multigam_state::multigam_nt_r)
+uint8_t multigam_state::multigam_nt_r(offs_t offset)
{
int page = ((offset & 0xc00) >> 10);
return m_nt_page[page][offset & 0x3ff];
@@ -305,7 +305,7 @@ void multigam_state::set_videoram_bank( int start, int count, int bank, int bank
*******************************************************/
-WRITE8_MEMBER(multigam_state::sprite_dma_w)
+void multigam_state::sprite_dma_w(address_space &space, uint8_t data)
{
int source = (data & 7);
m_ppu->spriteram_dma(space, source);
@@ -319,12 +319,12 @@ WRITE8_MEMBER(multigam_state::sprite_dma_w)
*******************************************************/
-READ8_MEMBER(multigam_state::multigam_IN0_r)
+uint8_t multigam_state::multigam_IN0_r()
{
return ((m_in_0 >> m_in_0_shift++) & 0x01) | 0x40;
}
-WRITE8_MEMBER(multigam_state::multigam_IN0_w)
+void multigam_state::multigam_IN0_w(uint8_t data)
{
if (data & 0x01)
{
@@ -341,7 +341,7 @@ WRITE8_MEMBER(multigam_state::multigam_IN0_w)
m_in_dsw = m_dsw.read_safe(0);
}
-READ8_MEMBER(multigam_state::multigam_IN1_r)
+uint8_t multigam_state::multigam_IN1_r()
{
return ((m_in_1 >> m_in_1_shift++) & 0x01) | 0x40;
}
@@ -361,7 +361,7 @@ READ_LINE_MEMBER(multigam_state::multigam_inputs_r)
*******************************************************/
-WRITE8_MEMBER(multigam_state::multigam_switch_prg_rom)
+void multigam_state::multigam_switch_prg_rom(uint8_t data)
{
/* switch PRG rom */
uint8_t* dst = memregion("maincpu")->base();
@@ -382,7 +382,7 @@ WRITE8_MEMBER(multigam_state::multigam_switch_prg_rom)
}
}
-WRITE8_MEMBER(multigam_state::multigam_switch_gfx_rom)
+void multigam_state::multigam_switch_gfx_rom(uint8_t data)
{
membank("bank1")->set_base(memregion("gfx1")->base() + (0x2000 * (data & 0x3f)));
set_mirroring(data & 0x40 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
@@ -390,7 +390,7 @@ WRITE8_MEMBER(multigam_state::multigam_switch_gfx_rom)
}
-WRITE8_MEMBER(multigam_state::multigam_mapper2_w)
+void multigam_state::multigam_mapper2_w(offs_t offset, uint8_t data)
{
if (m_game_gfx_bank & 0x80)
{
@@ -461,7 +461,7 @@ void multigam_state::multigam3_mmc3_scanline_cb( int scanline, int vblank, int b
}
}
-WRITE8_MEMBER(multigam_state::multigam3_mmc3_rom_switch_w)
+void multigam_state::multigam3_mmc3_rom_switch_w(offs_t offset, uint8_t data)
{
/* basically, a MMC3 mapper from the nes */
int bankmask = m_multigam3_mmc3_prg_size == 0x40000 ? 0x1f : 0x0f;
@@ -619,7 +619,7 @@ void multigam_state::multigam_init_mmc3(uint8_t *prg_base, int prg_size, int chr
memcpy(&dst[0x8000], prg_base + (prg_size - 0x4000), 0x4000);
memcpy(&dst[0xc000], prg_base + (prg_size - 0x4000), 0x4000);
- m_maincpu->space(AS_PROGRAM).install_write_handler(0x8000, 0xffff, write8_delegate(*this, FUNC(multigam_state::multigam3_mmc3_rom_switch_w)));
+ m_maincpu->space(AS_PROGRAM).install_write_handler(0x8000, 0xffff, write8sm_delegate(*this, FUNC(multigam_state::multigam3_mmc3_rom_switch_w)));
m_multigam3_mmc3_banks[0] = 0x1e;
m_multigam3_mmc3_banks[1] = 0x1f;
@@ -632,7 +632,7 @@ void multigam_state::multigam_init_mmc3(uint8_t *prg_base, int prg_size, int chr
m_multigam3_mmc3_prg_size = prg_size;
}
-WRITE8_MEMBER(multigam_state::multigm3_mapper2_w)
+void multigam_state::multigm3_mapper2_w(offs_t offset, uint8_t data)
{
if (m_game_gfx_bank & 0x80)
{
@@ -644,14 +644,14 @@ WRITE8_MEMBER(multigam_state::multigm3_mapper2_w)
}
}
-WRITE8_MEMBER(multigam_state::multigm3_switch_gfx_rom)
+void multigam_state::multigm3_switch_gfx_rom(uint8_t data)
{
set_videorom_bank(0, 8, data & 0x3f, 8);
set_mirroring(data & 0x40 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
m_game_gfx_bank = data;
}
-WRITE8_MEMBER(multigam_state::multigm3_switch_prg_rom)
+void multigam_state::multigm3_switch_prg_rom(address_space &space, uint8_t data)
{
/* switch PRG rom */
uint8_t* dst = memregion("maincpu")->base();
@@ -664,7 +664,7 @@ WRITE8_MEMBER(multigam_state::multigm3_switch_prg_rom)
}
else
{
- space.install_write_handler(0x8000, 0xffff, write8_delegate(*this, FUNC(multigam_state::multigm3_mapper2_w)) );
+ space.install_write_handler(0x8000, 0xffff, write8sm_delegate(*this, FUNC(multigam_state::multigm3_mapper2_w)) );
membank("bank10")->set_base(memregion("maincpu")->base() + 0x6000);
}
@@ -714,7 +714,7 @@ void multigam_state::multigm3_map(address_map &map)
*******************************************************/
-WRITE8_MEMBER(multigam_state::multigam3_mapper02_rom_switch_w)
+void multigam_state::multigam3_mapper02_rom_switch_w(uint8_t data)
{
uint8_t* mem = memregion("maincpu")->base();
int bankmask = (m_mapper02_prg_size/0x4000) - 1;
@@ -725,7 +725,7 @@ void multigam_state::multigam_init_mapper02(uint8_t* prg_base, int prg_size)
{
uint8_t* mem = memregion("maincpu")->base();
memcpy(mem + 0x8000, prg_base + prg_size - 0x8000, 0x8000);
- m_maincpu->space(AS_PROGRAM).install_write_handler(0x8000, 0xffff, write8_delegate(*this, FUNC(multigam_state::multigam3_mapper02_rom_switch_w)));
+ m_maincpu->space(AS_PROGRAM).install_write_handler(0x8000, 0xffff, write8smo_delegate(*this, FUNC(multigam_state::multigam3_mapper02_rom_switch_w)));
m_mapper02_prg_base = prg_base;
m_mapper02_prg_size = prg_size;
@@ -744,7 +744,7 @@ TIMER_CALLBACK_MEMBER(multigam_state::mmc1_resync_callback)
m_mmc1_reg_write_enable = 1;
}
-WRITE8_MEMBER(multigam_state::mmc1_rom_switch_w)
+void multigam_state::mmc1_rom_switch_w(offs_t offset, uint8_t data)
{
/* basically, a MMC1 mapper from the nes */
@@ -878,7 +878,7 @@ void multigam_state::multigam_init_mmc1(uint8_t *prg_base, int prg_size, int chr
memcpy(&dst[0x8000], prg_base + (prg_size - 0x8000), 0x8000);
- m_maincpu->space(AS_PROGRAM).install_write_handler(0x8000, 0xffff, write8_delegate(*this, FUNC(multigam_state::mmc1_rom_switch_w)));
+ m_maincpu->space(AS_PROGRAM).install_write_handler(0x8000, 0xffff, write8sm_delegate(*this, FUNC(multigam_state::mmc1_rom_switch_w)));
m_mmc1_reg_write_enable = 1;
m_mmc1_rom_mask = (prg_size / 0x4000) - 1;
@@ -973,12 +973,12 @@ void multigam_state::supergm3_set_bank()
}
}
-WRITE8_MEMBER(multigam_state::supergm3_prg_bank_w)
+void multigam_state::supergm3_prg_bank_w(uint8_t data)
{
m_supergm3_prg_bank = data;
}
-WRITE8_MEMBER(multigam_state::supergm3_chr_bank_w)
+void multigam_state::supergm3_chr_bank_w(uint8_t data)
{
m_supergm3_chr_bank = data;
supergm3_set_bank();
@@ -1157,7 +1157,7 @@ MACHINE_RESET_MEMBER(multigam_state,multigm3)
{
address_space &space = m_maincpu->space(AS_PROGRAM);
/* reset the ppu */
- multigm3_switch_prg_rom(space, 0, 0x01 );
+ multigm3_switch_prg_rom(space, 0x01 );
}
void multigam_state::machine_start()
@@ -1168,7 +1168,7 @@ void multigam_state::machine_start()
m_nt_page[2] = m_nt_ram.get() + 0x800;
m_nt_page[3] = m_nt_ram.get() + 0xc00;
- m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(*this, FUNC(multigam_state::multigam_nt_r)), write8_delegate(*this, FUNC(multigam_state::multigam_nt_w)));
+ m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8sm_delegate(*this, FUNC(multigam_state::multigam_nt_r)), write8sm_delegate(*this, FUNC(multigam_state::multigam_nt_w)));
m_ppu->space(AS_PROGRAM).install_read_bank(0x0000, 0x1fff, "bank1");
membank("bank1")->set_base(memregion("gfx1")->base());
}
@@ -1181,7 +1181,7 @@ MACHINE_START_MEMBER(multigam_state,multigm3)
m_nt_page[2] = m_nt_ram.get() + 0x800;
m_nt_page[3] = m_nt_ram.get() + 0xc00;
- m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(*this, FUNC(multigam_state::multigam_nt_r)), write8_delegate(*this, FUNC(multigam_state::multigam_nt_w)));
+ m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8sm_delegate(*this, FUNC(multigam_state::multigam_nt_r)), write8sm_delegate(*this, FUNC(multigam_state::multigam_nt_w)));
m_ppu->space(AS_PROGRAM).install_read_bank(0x0000, 0x03ff, "bank2");
m_ppu->space(AS_PROGRAM).install_read_bank(0x0400, 0x07ff, "bank3");
@@ -1203,7 +1203,7 @@ MACHINE_START_MEMBER(multigam_state,supergm3)
m_nt_page[2] = m_nt_ram.get() + 0x800;
m_nt_page[3] = m_nt_ram.get() + 0xc00;
- m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(*this, FUNC(multigam_state::multigam_nt_r)), write8_delegate(*this, FUNC(multigam_state::multigam_nt_w)));
+ m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8sm_delegate(*this, FUNC(multigam_state::multigam_nt_r)), write8sm_delegate(*this, FUNC(multigam_state::multigam_nt_w)));
m_vram = std::make_unique<uint8_t[]>(0x2000);
m_multigmc_mmc3_6000_ram = std::make_unique<uint8_t[]>(0x2000);
@@ -1387,14 +1387,12 @@ ROM_END
void multigam_state::init_multigam()
{
- address_space &space = m_maincpu->space(AS_PROGRAM);
- multigam_switch_prg_rom(space, 0x0, 0x01);
+ multigam_switch_prg_rom(0x01);
}
void multigam_state::multigm3_decrypt(uint8_t* mem, int memsize, const uint8_t* decode_nibble)
{
- int i;
- for (i = 0; i < memsize; i++)
+ for (int i = 0; i < memsize; i++)
{
mem[i] = decode_nibble[mem[i] & 0x0f] | (decode_nibble[mem[i] >> 4] << 4);
}
@@ -1402,8 +1400,6 @@ void multigam_state::multigm3_decrypt(uint8_t* mem, int memsize, const uint8_t*
void multigam_state::init_multigm3()
{
- address_space &space = m_maincpu->space(AS_PROGRAM);
-
const uint8_t decode[16] = { 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a };
multigm3_decrypt(memregion("maincpu")->base(), memregion("maincpu")->bytes(), decode );
@@ -1411,13 +1407,11 @@ void multigam_state::init_multigm3()
m_multigmc_mmc3_6000_ram = std::make_unique<uint8_t[]>(0x2000);
- multigam_switch_prg_rom(space, 0x0, 0x01);
+ multigam_switch_prg_rom(0x01);
}
void multigam_state::init_multigmt()
{
- address_space &space = m_maincpu->space(AS_PROGRAM);
-
std::vector<uint8_t> buf(0x80000);
uint8_t *rom = memregion("maincpu")->base();
@@ -1447,7 +1441,7 @@ void multigam_state::init_multigmt()
rom[i] = bitswap<8>(buf[addr], 4, 7, 3, 2, 5, 1, 6, 0);
}
- multigam_switch_prg_rom(space, 0x0, 0x01);
+ multigam_switch_prg_rom(0x01);
}
GAME( 1992, multigam, 0, multigam, multigam, multigam_state, init_multigam, ROT0, "<unknown>", "Multi Game (set 1)", 0 )
diff --git a/src/mame/drivers/mvme147.cpp b/src/mame/drivers/mvme147.cpp
index d261431a2cc..ee0b47a755a 100644
--- a/src/mame/drivers/mvme147.cpp
+++ b/src/mame/drivers/mvme147.cpp
@@ -201,21 +201,21 @@ mvme147_state(const machine_config &mconfig, device_type type, const char *tag)
void mvme147(machine_config &config);
private:
- DECLARE_READ32_MEMBER (bootvect_r);
- DECLARE_WRITE32_MEMBER (bootvect_w);
+ uint32_t bootvect_r(offs_t offset);
+ void bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
/* PCC - Peripheral Channel Controller */
- //DECLARE_READ32_MEMBER (pcc32_r);
- //DECLARE_WRITE32_MEMBER (pcc32_w);
- DECLARE_READ16_MEMBER (pcc16_r);
- DECLARE_WRITE16_MEMBER (pcc16_w);
- DECLARE_READ8_MEMBER (pcc8_r);
- DECLARE_WRITE8_MEMBER (pcc8_w);
- DECLARE_READ8_MEMBER (vmechip_r);
- DECLARE_WRITE8_MEMBER (vmechip_w);
- //DECLARE_READ16_MEMBER (vme_a24_r);
- //DECLARE_WRITE16_MEMBER (vme_a24_w);
- //DECLARE_READ16_MEMBER (vme_a16_r);
- //DECLARE_WRITE16_MEMBER (vme_a16_w);
+ //uint32_t pcc32_r(offs_t offset);
+ //void pcc32_w(offs_t offset, uint32_t data);
+ uint16_t pcc16_r(offs_t offset);
+ void pcc16_w(offs_t offset, uint16_t data);
+ uint8_t pcc8_r(offs_t offset);
+ void pcc8_w(offs_t offset, uint8_t data);
+ uint8_t vmechip_r(offs_t offset);
+ void vmechip_w(offs_t offset, uint8_t data);
+ //uint16_t vme_a24_r();
+ //void vme_a24_w(uint16_t data);
+ //uint16_t vme_a16_r();
+ //void vme_a16_w(uint16_t data);
virtual void machine_start () override;
virtual void machine_reset () override;
void mvme147_mem(address_map &map);
@@ -285,21 +285,21 @@ void mvme147_state::machine_reset ()
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
-READ32_MEMBER (mvme147_state::bootvect_r){
+uint32_t mvme147_state::bootvect_r(offs_t offset){
return m_sysrom[offset];
}
-WRITE32_MEMBER (mvme147_state::bootvect_w){
+void mvme147_state::bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask){
m_sysram[offset % ARRAY_LENGTH(m_sysram)] &= ~mem_mask;
m_sysram[offset % ARRAY_LENGTH(m_sysram)] |= (data & mem_mask);
m_sysrom = &m_sysram[0]; // redirect all upcoming accesses to masking RAM until reset.
}
/****
- * PCC - Periheral Channel Controller driver, might deserve its own driver but will rest here until another board wants it
+ * PCC - Peripheral Channel Controller driver, might deserve its own driver but will rest here until another board wants it
*/
#if 0 /* Doesn't compile atm */
-READ32_MEMBER (mvme147_state::pcc32_r){
+uint32_t mvme147_state::pcc32_r(offs_t offset){
LOG("%s[%04x]", FUNCNAME, offset);
switch(offset)
{
@@ -309,7 +309,7 @@ READ32_MEMBER (mvme147_state::pcc32_r){
return 0x00;
}
-WRITE32_MEMBER (mvme147_state::pcc32_w){
+void mvme147_state::pcc32_w(offs_t offset, uint32_t data){
LOG("%s[%04x]= %08lx", FUNCNAME, offset, data);
switch(offset)
{
@@ -325,7 +325,7 @@ WRITE32_MEMBER (mvme147_state::pcc32_w){
#define P16_TIMER2_PRELOAD (P16BASE + 4)
#define P16_TIMER2_COUNT (P16BASE + 6)
-READ16_MEMBER (mvme147_state::pcc16_r){
+uint16_t mvme147_state::pcc16_r(offs_t offset){
uint16_t ret = 0;
LOG("Call to %s[%04x]", FUNCNAME, offset);
@@ -341,7 +341,7 @@ READ16_MEMBER (mvme147_state::pcc16_r){
return ret;
}
-WRITE16_MEMBER (mvme147_state::pcc16_w){
+void mvme147_state::pcc16_w(offs_t offset, uint16_t data){
LOG("Call to %s[%04x] <- %04x - ", FUNCNAME, offset, data);
switch(offset)
{
@@ -382,7 +382,7 @@ WRITE16_MEMBER (mvme147_state::pcc16_w){
#define P8_PRINTER_DATA 0xfffe2800
#define P8_PRINTER_STATUS 0xfffe2800
-READ8_MEMBER (mvme147_state::pcc8_r){
+uint8_t mvme147_state::pcc8_r(offs_t offset){
uint8_t ret = 0;
LOG("Call to %s[%04x] ", FUNCNAME, offset);
@@ -429,7 +429,7 @@ READ8_MEMBER (mvme147_state::pcc8_r){
return ret;
}
-WRITE8_MEMBER (mvme147_state::pcc8_w){
+void mvme147_state::pcc8_w(offs_t offset, uint8_t data){
LOG("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data);
switch(offset + P8BASE)
{
@@ -505,7 +505,7 @@ WRITE8_MEMBER (mvme147_state::pcc8_w){
#define VC_GCSR_BASE_ADR 0xfffe201B
-READ8_MEMBER (mvme147_state::vmechip_r){
+uint8_t mvme147_state::vmechip_r(offs_t offset){
uint8_t ret = 0;
LOG("Call to %s[%04x] ", FUNCNAME, offset);
@@ -592,7 +592,7 @@ READ8_MEMBER (mvme147_state::vmechip_r){
return ret;
}
-WRITE8_MEMBER (mvme147_state::vmechip_w){
+void mvme147_state::vmechip_w(offs_t offset, uint8_t data){
LOG("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data);
switch(offset * 2 + VCBASE)
{
@@ -621,21 +621,21 @@ WRITE8_MEMBER (mvme147_state::vmechip_w){
#if 0
/* Dummy VME access methods until the VME bus device is ready for use */
-READ16_MEMBER (mvme147_state::vme_a24_r){
+uint16_t mvme147_state::vme_a24_r(){
LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
-WRITE16_MEMBER (mvme147_state::vme_a24_w){
+void mvme147_state::vme_a24_w(uint16_t data){
LOG("%s\n", FUNCNAME);
}
-READ16_MEMBER (mvme147_state::vme_a16_r){
+uint16_t mvme147_state::vme_a16_r(){
LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
-WRITE16_MEMBER (mvme147_state::vme_a16_w){
+void mvme147_state::vme_a16_w(uint16_t data){
LOG("%s\n", FUNCNAME);
}
#endif
diff --git a/src/mame/drivers/mz2000.cpp b/src/mame/drivers/mz2000.cpp
index 6f3f9a58c99..a963cd6ce9c 100644
--- a/src/mame/drivers/mz2000.cpp
+++ b/src/mame/drivers/mz2000.cpp
@@ -103,26 +103,26 @@ private:
uint8_t m_porta_latch;
uint8_t m_tape_ctrl;
- DECLARE_READ8_MEMBER(mz2000_ipl_r);
- DECLARE_READ8_MEMBER(mz2000_wram_r);
- DECLARE_WRITE8_MEMBER(mz2000_wram_w);
- DECLARE_READ8_MEMBER(mz2000_tvram_r);
- DECLARE_WRITE8_MEMBER(mz2000_tvram_w);
- DECLARE_READ8_MEMBER(mz2000_gvram_r);
- DECLARE_WRITE8_MEMBER(mz2000_gvram_w);
- DECLARE_READ8_MEMBER(mz2000_mem_r);
- DECLARE_WRITE8_MEMBER(mz2000_mem_w);
- DECLARE_WRITE8_MEMBER(mz2000_gvram_bank_w);
- DECLARE_WRITE8_MEMBER(floppy_select_w);
- DECLARE_WRITE8_MEMBER(floppy_side_w);
- DECLARE_WRITE8_MEMBER(timer_w);
- DECLARE_WRITE8_MEMBER(mz2000_tvram_attr_w);
- DECLARE_WRITE8_MEMBER(mz2000_gvram_mask_w);
+ uint8_t mz2000_ipl_r(offs_t offset);
+ uint8_t mz2000_wram_r(offs_t offset);
+ void mz2000_wram_w(offs_t offset, uint8_t data);
+ uint8_t mz2000_tvram_r(offs_t offset);
+ void mz2000_tvram_w(offs_t offset, uint8_t data);
+ uint8_t mz2000_gvram_r(offs_t offset);
+ void mz2000_gvram_w(offs_t offset, uint8_t data);
+ uint8_t mz2000_mem_r(offs_t offset);
+ void mz2000_mem_w(offs_t offset, uint8_t data);
+ void mz2000_gvram_bank_w(uint8_t data);
+ void floppy_select_w(uint8_t data);
+ void floppy_side_w(uint8_t data);
+ void timer_w(uint8_t data);
+ void mz2000_tvram_attr_w(uint8_t data);
+ void mz2000_gvram_mask_w(uint8_t data);
virtual void machine_reset() override;
virtual void video_start() override;
uint32_t screen_update_mz2000(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
- DECLARE_READ8_MEMBER(fdc_r);
- DECLARE_WRITE8_MEMBER(fdc_w);
+ uint8_t fdc_r(offs_t offset);
+ void fdc_w(offs_t offset, uint8_t data);
uint8_t mz2000_porta_r();
uint8_t mz2000_portb_r();
uint8_t mz2000_portc_r();
@@ -256,100 +256,100 @@ uint32_t mz2000_state::screen_update_mz2000(screen_device &screen, bitmap_ind16
return 0;
}
-READ8_MEMBER(mz2000_state::mz2000_ipl_r)
+uint8_t mz2000_state::mz2000_ipl_r(offs_t offset)
{
return m_region_ipl->base()[offset];
}
-READ8_MEMBER(mz2000_state::mz2000_wram_r)
+uint8_t mz2000_state::mz2000_wram_r(offs_t offset)
{
return m_region_wram->base()[offset];
}
-WRITE8_MEMBER(mz2000_state::mz2000_wram_w)
+void mz2000_state::mz2000_wram_w(offs_t offset, uint8_t data)
{
m_region_wram->base()[offset] = data;
}
-READ8_MEMBER(mz2000_state::mz2000_tvram_r)
+uint8_t mz2000_state::mz2000_tvram_r(offs_t offset)
{
return m_region_tvram->base()[offset];
}
-WRITE8_MEMBER(mz2000_state::mz2000_tvram_w)
+void mz2000_state::mz2000_tvram_w(offs_t offset, uint8_t data)
{
m_region_tvram->base()[offset] = data;
}
-READ8_MEMBER(mz2000_state::mz2000_gvram_r)
+uint8_t mz2000_state::mz2000_gvram_r(offs_t offset)
{
return m_region_gvram->base()[offset+m_gvram_bank*0x4000];
}
-WRITE8_MEMBER(mz2000_state::mz2000_gvram_w)
+void mz2000_state::mz2000_gvram_w(offs_t offset, uint8_t data)
{
m_region_gvram->base()[offset+m_gvram_bank*0x4000] = data;
}
-READ8_MEMBER(mz2000_state::mz2000_mem_r)
+uint8_t mz2000_state::mz2000_mem_r(offs_t offset)
{
uint8_t page_mem;
page_mem = (offset & 0xf000) >> 12;
if(page_mem == 0 && m_ipl_enable)
- return mz2000_ipl_r(space,offset & 0xfff);
+ return mz2000_ipl_r(offset & 0xfff);
if(((page_mem & 8) == 0) && m_ipl_enable == 0) // if ipl is enabled, 0x1000 - 0x7fff accesses to dummy region
- return mz2000_wram_r(space,offset);
+ return mz2000_wram_r(offset);
if(page_mem & 8)
{
if(page_mem == 0xd && m_tvram_enable)
- return mz2000_tvram_r(space,offset & 0xfff);
+ return mz2000_tvram_r(offset & 0xfff);
else if(page_mem >= 0xc && m_gvram_enable)
- return mz2000_gvram_r(space,offset & 0x3fff);
+ return mz2000_gvram_r(offset & 0x3fff);
else
{
uint16_t wram_mask = (m_ipl_enable) ? 0x7fff : 0xffff;
- return mz2000_wram_r(space,offset & wram_mask);
+ return mz2000_wram_r(offset & wram_mask);
}
}
return 0xff;
}
-WRITE8_MEMBER(mz2000_state::mz2000_mem_w)
+void mz2000_state::mz2000_mem_w(offs_t offset, uint8_t data)
{
uint8_t page_mem;
page_mem = (offset & 0xf000) >> 12;
if((page_mem & 8) == 0 && m_ipl_enable == 0)
- mz2000_wram_w(space,offset,data);
+ mz2000_wram_w(offset,data);
if(page_mem & 8)
{
if(page_mem == 0xd && m_tvram_enable)
- mz2000_tvram_w(space,offset & 0xfff,data);
+ mz2000_tvram_w(offset & 0xfff,data);
else if(page_mem >= 0xc && m_gvram_enable)
- mz2000_gvram_w(space,offset & 0x3fff,data);
+ mz2000_gvram_w(offset & 0x3fff,data);
else
{
uint16_t wram_mask = (m_ipl_enable) ? 0x7fff : 0xffff;
- mz2000_wram_w(space,offset & wram_mask,data);
+ mz2000_wram_w(offset & wram_mask,data);
}
}
}
-WRITE8_MEMBER(mz2000_state::mz2000_gvram_bank_w)
+void mz2000_state::mz2000_gvram_bank_w(uint8_t data)
{
m_gvram_bank = data & 3;
}
-READ8_MEMBER(mz2000_state::fdc_r)
+uint8_t mz2000_state::fdc_r(offs_t offset)
{
if(m_has_fdc)
return m_mb8877a->read(offset) ^ 0xff;
@@ -357,13 +357,13 @@ READ8_MEMBER(mz2000_state::fdc_r)
return 0xff;
}
-WRITE8_MEMBER(mz2000_state::fdc_w)
+void mz2000_state::fdc_w(offs_t offset, uint8_t data)
{
if(m_has_fdc)
m_mb8877a->write(offset, data ^ 0xff);
}
-WRITE8_MEMBER(mz2000_state::floppy_select_w)
+void mz2000_state::floppy_select_w(uint8_t data)
{
switch (data & 0x03)
{
@@ -381,13 +381,13 @@ WRITE8_MEMBER(mz2000_state::floppy_select_w)
m_floppy->mon_w(!BIT(data, 7));
}
-WRITE8_MEMBER(mz2000_state::floppy_side_w)
+void mz2000_state::floppy_side_w(uint8_t data)
{
if (m_floppy)
m_floppy->ss_w(BIT(data, 0));
}
-WRITE8_MEMBER(mz2000_state::timer_w)
+void mz2000_state::timer_w(uint8_t data)
{
m_pit8253->write_gate0(1);
m_pit8253->write_gate1(1);
@@ -397,12 +397,12 @@ WRITE8_MEMBER(mz2000_state::timer_w)
m_pit8253->write_gate1(1);
}
-WRITE8_MEMBER(mz2000_state::mz2000_tvram_attr_w)
+void mz2000_state::mz2000_tvram_attr_w(uint8_t data)
{
m_tvram_attr = data;
}
-WRITE8_MEMBER(mz2000_state::mz2000_gvram_mask_w)
+void mz2000_state::mz2000_gvram_mask_w(uint8_t data)
{
m_gvram_mask = data;
}
diff --git a/src/mame/drivers/mz3500.cpp b/src/mame/drivers/mz3500.cpp
index 029dace8484..0b9b537c340 100644
--- a/src/mame/drivers/mz3500.cpp
+++ b/src/mame/drivers/mz3500.cpp
@@ -86,20 +86,20 @@ private:
uint8_t m_fdd_sel;
- DECLARE_READ8_MEMBER(mz3500_master_mem_r);
- DECLARE_WRITE8_MEMBER(mz3500_master_mem_w);
- DECLARE_READ8_MEMBER(mz3500_ipl_r);
- DECLARE_READ8_MEMBER(mz3500_basic_r);
- DECLARE_READ8_MEMBER(mz3500_work_ram_r);
- DECLARE_WRITE8_MEMBER(mz3500_work_ram_w);
- DECLARE_READ8_MEMBER(mz3500_shared_ram_r);
- DECLARE_WRITE8_MEMBER(mz3500_shared_ram_w);
- DECLARE_READ8_MEMBER(mz3500_io_r);
- DECLARE_WRITE8_MEMBER(mz3500_io_w);
- DECLARE_WRITE8_MEMBER(mz3500_crtc_w);
- DECLARE_READ8_MEMBER(mz3500_fdc_r);
- DECLARE_WRITE8_MEMBER(mz3500_fdc_w);
- DECLARE_READ8_MEMBER(mz3500_fdc_dma_r);
+ uint8_t mz3500_master_mem_r(offs_t offset);
+ void mz3500_master_mem_w(offs_t offset, uint8_t data);
+ uint8_t mz3500_ipl_r(offs_t offset);
+ uint8_t mz3500_basic_r(offs_t offset);
+ uint8_t mz3500_work_ram_r(offs_t offset);
+ void mz3500_work_ram_w(offs_t offset, uint8_t data);
+ uint8_t mz3500_shared_ram_r(offs_t offset);
+ void mz3500_shared_ram_w(offs_t offset, uint8_t data);
+ uint8_t mz3500_io_r(offs_t offset);
+ void mz3500_io_w(offs_t offset, uint8_t data);
+ void mz3500_crtc_w(offs_t offset, uint8_t data);
+ uint8_t mz3500_fdc_r();
+ void mz3500_fdc_w(uint8_t data);
+ uint8_t mz3500_fdc_dma_r();
void mz3500_pa_w(uint8_t data);
void mz3500_pb_w(uint8_t data);
void mz3500_pc_w(uint8_t data);
@@ -256,81 +256,81 @@ uint32_t mz3500_state::screen_update( screen_device &screen, bitmap_rgb32 &bitma
return 0;
}
-READ8_MEMBER(mz3500_state::mz3500_ipl_r)
+uint8_t mz3500_state::mz3500_ipl_r(offs_t offset)
{
return m_ipl_rom[offset];
}
-READ8_MEMBER(mz3500_state::mz3500_basic_r)
+uint8_t mz3500_state::mz3500_basic_r(offs_t offset)
{
return m_basic_rom[offset];
}
-READ8_MEMBER(mz3500_state::mz3500_work_ram_r)
+uint8_t mz3500_state::mz3500_work_ram_r(offs_t offset)
{
return m_work_ram[offset];
}
-WRITE8_MEMBER(mz3500_state::mz3500_work_ram_w)
+void mz3500_state::mz3500_work_ram_w(offs_t offset, uint8_t data)
{
m_work_ram[offset] = data;
}
-READ8_MEMBER(mz3500_state::mz3500_master_mem_r)
+uint8_t mz3500_state::mz3500_master_mem_r(offs_t offset)
{
if(m_ms == 0)
{
- if((offset & 0xe000) == 0x0000) { return mz3500_ipl_r(space,(offset & 0xfff) | 0x1000); }
- if((offset & 0xe000) == 0x2000) { return mz3500_basic_r(space,(offset & 0x1fff) | 0x2000); }
- if((offset & 0xc000) == 0x4000) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x4000); }
- if((offset & 0xc000) == 0x8000) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x8000); }
+ if((offset & 0xe000) == 0x0000) { return mz3500_ipl_r((offset & 0xfff) | 0x1000); }
+ if((offset & 0xe000) == 0x2000) { return mz3500_basic_r((offset & 0x1fff) | 0x2000); }
+ if((offset & 0xc000) == 0x4000) { return mz3500_work_ram_r((offset & 0x3fff) | 0x4000); }
+ if((offset & 0xc000) == 0x8000) { return mz3500_work_ram_r((offset & 0x3fff) | 0x8000); }
if((offset & 0xc000) == 0xc000)
{
- if(m_ma == 0x0) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0xc000); }
- if(m_ma == 0x1) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x0000); }
- if(m_ma == 0xf) { return mz3500_shared_ram_r(space,(offset & 0x7ff)); }
+ if(m_ma == 0x0) { return mz3500_work_ram_r((offset & 0x3fff) | 0xc000); }
+ if(m_ma == 0x1) { return mz3500_work_ram_r((offset & 0x3fff) | 0x0000); }
+ if(m_ma == 0xf) { return mz3500_shared_ram_r((offset & 0x7ff)); }
}
printf("Read with unmapped memory bank offset %04x MS %02x MA %02x\n",offset,m_ms,m_ma);
}
else if(m_ms == 1)
{
- return ((offset & 0xf800) == 0xf800) ? mz3500_shared_ram_r(space,(offset & 0x7ff)) : mz3500_work_ram_r(space,offset);
+ return ((offset & 0xf800) == 0xf800) ? mz3500_shared_ram_r((offset & 0x7ff)) : mz3500_work_ram_r(offset);
}
else if(m_ms == 2) // ROM based BASIC
{
- if((offset & 0xe000) == 0x0000) { return mz3500_basic_r(space,offset & 0x1fff); }
+ if((offset & 0xe000) == 0x0000) { return mz3500_basic_r(offset & 0x1fff); }
if((offset & 0xe000) == 0x2000)
{
switch(m_mo)
{
- case 0x0: return mz3500_basic_r(space,(offset & 0x1fff) | 0x2000);
- case 0x1: return mz3500_basic_r(space,(offset & 0x1fff) | 0x4000);
- case 0x2: return mz3500_basic_r(space,(offset & 0x1fff) | 0x6000);
+ case 0x0: return mz3500_basic_r((offset & 0x1fff) | 0x2000);
+ case 0x1: return mz3500_basic_r((offset & 0x1fff) | 0x4000);
+ case 0x2: return mz3500_basic_r((offset & 0x1fff) | 0x6000);
}
}
- if((offset & 0xc000) == 0x4000) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x4000); }
- if((offset & 0xc000) == 0x8000) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x8000); }
+ if((offset & 0xc000) == 0x4000) { return mz3500_work_ram_r((offset & 0x3fff) | 0x4000); }
+ if((offset & 0xc000) == 0x8000) { return mz3500_work_ram_r((offset & 0x3fff) | 0x8000); }
if((offset & 0xc000) == 0xc000)
{
switch(m_ma)
{
- case 0x0: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x0c000);
- case 0x1: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x00000);
- case 0x2: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x10000);
- case 0x3: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x14000);
- case 0x4: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x18000);
- case 0x5: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x1c000);
- case 0x6: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x20000);
- case 0x7: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x24000);
- case 0x8: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x28000);
- case 0x9: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x2c000);
- case 0xa: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x30000);
- case 0xb: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x34000);
- case 0xc: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x38000);
- case 0xd: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x3c000);
- case 0xf: return mz3500_shared_ram_r(space,(offset & 0x7ff));
+ case 0x0: return mz3500_work_ram_r((offset & 0x3fff) | 0x0c000);
+ case 0x1: return mz3500_work_ram_r((offset & 0x3fff) | 0x00000);
+ case 0x2: return mz3500_work_ram_r((offset & 0x3fff) | 0x10000);
+ case 0x3: return mz3500_work_ram_r((offset & 0x3fff) | 0x14000);
+ case 0x4: return mz3500_work_ram_r((offset & 0x3fff) | 0x18000);
+ case 0x5: return mz3500_work_ram_r((offset & 0x3fff) | 0x1c000);
+ case 0x6: return mz3500_work_ram_r((offset & 0x3fff) | 0x20000);
+ case 0x7: return mz3500_work_ram_r((offset & 0x3fff) | 0x24000);
+ case 0x8: return mz3500_work_ram_r((offset & 0x3fff) | 0x28000);
+ case 0x9: return mz3500_work_ram_r((offset & 0x3fff) | 0x2c000);
+ case 0xa: return mz3500_work_ram_r((offset & 0x3fff) | 0x30000);
+ case 0xb: return mz3500_work_ram_r((offset & 0x3fff) | 0x34000);
+ case 0xc: return mz3500_work_ram_r((offset & 0x3fff) | 0x38000);
+ case 0xd: return mz3500_work_ram_r((offset & 0x3fff) | 0x3c000);
+ case 0xf: return mz3500_shared_ram_r((offset & 0x7ff));
}
}
@@ -338,37 +338,37 @@ READ8_MEMBER(mz3500_state::mz3500_master_mem_r)
}
else if (m_ms == 3) // RAM based BASIC
{
- if((offset & 0xe000) == 0x0000) { return mz3500_work_ram_r(space,offset & 0x1fff); }
+ if((offset & 0xe000) == 0x0000) { return mz3500_work_ram_r(offset & 0x1fff); }
if((offset & 0xe000) == 0x2000)
{
switch(m_mo)
{
- case 0x0: return mz3500_work_ram_r(space,(offset & 0x1fff) | 0x2000);
- case 0x1: return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xc000);
- case 0x2: return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xe000);
+ case 0x0: return mz3500_work_ram_r((offset & 0x1fff) | 0x2000);
+ case 0x1: return mz3500_work_ram_r((offset & 0x1fff) | 0xc000);
+ case 0x2: return mz3500_work_ram_r((offset & 0x1fff) | 0xe000);
}
printf("Read with unmapped memory bank offset %04x MS %02x MO %02x\n",offset,m_ms,m_mo);
}
- if((offset & 0xc000) == 0x4000) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x4000); }
- if((offset & 0xc000) == 0x8000) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x8000); }
+ if((offset & 0xc000) == 0x4000) { return mz3500_work_ram_r((offset & 0x3fff) | 0x4000); }
+ if((offset & 0xc000) == 0x8000) { return mz3500_work_ram_r((offset & 0x3fff) | 0x8000); }
if((offset & 0xc000) == 0xc000)
{
switch(m_ma)
{
- case 0x0: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x10000);
- case 0x1: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x14000);
- case 0x2: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x18000);
- case 0x3: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x1c000);
- case 0x4: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x20000);
- case 0x5: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x24000);
- case 0x6: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x28000);
- case 0x7: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x2c000);
- case 0x8: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x30000);
- case 0x9: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x34000);
- case 0xa: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x38000);
- case 0xb: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x3c000);
- case 0xf: return mz3500_shared_ram_r(space,(offset & 0x7ff));
+ case 0x0: return mz3500_work_ram_r((offset & 0x3fff) | 0x10000);
+ case 0x1: return mz3500_work_ram_r((offset & 0x3fff) | 0x14000);
+ case 0x2: return mz3500_work_ram_r((offset & 0x3fff) | 0x18000);
+ case 0x3: return mz3500_work_ram_r((offset & 0x3fff) | 0x1c000);
+ case 0x4: return mz3500_work_ram_r((offset & 0x3fff) | 0x20000);
+ case 0x5: return mz3500_work_ram_r((offset & 0x3fff) | 0x24000);
+ case 0x6: return mz3500_work_ram_r((offset & 0x3fff) | 0x28000);
+ case 0x7: return mz3500_work_ram_r((offset & 0x3fff) | 0x2c000);
+ case 0x8: return mz3500_work_ram_r((offset & 0x3fff) | 0x30000);
+ case 0x9: return mz3500_work_ram_r((offset & 0x3fff) | 0x34000);
+ case 0xa: return mz3500_work_ram_r((offset & 0x3fff) | 0x38000);
+ case 0xb: return mz3500_work_ram_r((offset & 0x3fff) | 0x3c000);
+ case 0xf: return mz3500_shared_ram_r((offset & 0x7ff));
}
}
}
@@ -377,17 +377,17 @@ READ8_MEMBER(mz3500_state::mz3500_master_mem_r)
return 0xff; // shouldn't happen
}
-WRITE8_MEMBER(mz3500_state::mz3500_master_mem_w)
+void mz3500_state::mz3500_master_mem_w(offs_t offset, uint8_t data)
{
if(m_ms == 0) // Initialize State
{
- if((offset & 0xc000) == 0x4000) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x4000,data); return; }
- if((offset & 0xc000) == 0x8000) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x8000,data); return; }
+ if((offset & 0xc000) == 0x4000) { mz3500_work_ram_w((offset & 0x3fff) | 0x4000,data); return; }
+ if((offset & 0xc000) == 0x8000) { mz3500_work_ram_w((offset & 0x3fff) | 0x8000,data); return; }
if((offset & 0xc000) == 0xc000)
{
- if(m_ma == 0x0) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0xc000,data); return; }
- if(m_ma == 0x1) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x0000,data); return; }
- if(m_ma == 0xf) { mz3500_shared_ram_w(space,(offset & 0x7ff),data); return; }
+ if(m_ma == 0x0) { mz3500_work_ram_w((offset & 0x3fff) | 0xc000,data); return; }
+ if(m_ma == 0x1) { mz3500_work_ram_w((offset & 0x3fff) | 0x0000,data); return; }
+ if(m_ma == 0xf) { mz3500_shared_ram_w((offset & 0x7ff),data); return; }
}
printf("Write with unmapped memory bank offset %04x data %02x MS %02x MA %02x\n",offset,data,m_ms,m_ma);
@@ -395,35 +395,35 @@ WRITE8_MEMBER(mz3500_state::mz3500_master_mem_w)
else if(m_ms == 1) // System Loading & CP/M
{
if((offset & 0xf800) == 0xf800)
- mz3500_shared_ram_w(space,(offset & 0x7ff),data);
+ mz3500_shared_ram_w((offset & 0x7ff),data);
else
- mz3500_work_ram_w(space,offset,data);
+ mz3500_work_ram_w(offset,data);
return;
}
else if(m_ms == 2) // ROM based BASIC
{
- if((offset & 0xc000) == 0x4000) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x4000,data); return; }
- if((offset & 0xc000) == 0x8000) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x8000,data); return; }
+ if((offset & 0xc000) == 0x4000) { mz3500_work_ram_w((offset & 0x3fff) | 0x4000,data); return; }
+ if((offset & 0xc000) == 0x8000) { mz3500_work_ram_w((offset & 0x3fff) | 0x8000,data); return; }
if((offset & 0xc000) == 0xc000)
{
switch(m_ma)
{
- case 0x0: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x0c000,data); return;
- case 0x1: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x00000,data); return;
- case 0x2: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x10000,data); return;
- case 0x3: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x14000,data); return;
- case 0x4: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x18000,data); return;
- case 0x5: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x1c000,data); return;
- case 0x6: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x20000,data); return;
- case 0x7: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x24000,data); return;
- case 0x8: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x28000,data); return;
- case 0x9: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x2c000,data); return;
- case 0xa: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x30000,data); return;
- case 0xb: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x34000,data); return;
- case 0xc: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x38000,data); return;
- case 0xd: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x3c000,data); return;
- case 0xf: mz3500_shared_ram_w(space,(offset & 0x7ff),data); return;
+ case 0x0: mz3500_work_ram_w((offset & 0x3fff) | 0x0c000,data); return;
+ case 0x1: mz3500_work_ram_w((offset & 0x3fff) | 0x00000,data); return;
+ case 0x2: mz3500_work_ram_w((offset & 0x3fff) | 0x10000,data); return;
+ case 0x3: mz3500_work_ram_w((offset & 0x3fff) | 0x14000,data); return;
+ case 0x4: mz3500_work_ram_w((offset & 0x3fff) | 0x18000,data); return;
+ case 0x5: mz3500_work_ram_w((offset & 0x3fff) | 0x1c000,data); return;
+ case 0x6: mz3500_work_ram_w((offset & 0x3fff) | 0x20000,data); return;
+ case 0x7: mz3500_work_ram_w((offset & 0x3fff) | 0x24000,data); return;
+ case 0x8: mz3500_work_ram_w((offset & 0x3fff) | 0x28000,data); return;
+ case 0x9: mz3500_work_ram_w((offset & 0x3fff) | 0x2c000,data); return;
+ case 0xa: mz3500_work_ram_w((offset & 0x3fff) | 0x30000,data); return;
+ case 0xb: mz3500_work_ram_w((offset & 0x3fff) | 0x34000,data); return;
+ case 0xc: mz3500_work_ram_w((offset & 0x3fff) | 0x38000,data); return;
+ case 0xd: mz3500_work_ram_w((offset & 0x3fff) | 0x3c000,data); return;
+ case 0xf: mz3500_shared_ram_w((offset & 0x7ff),data); return;
}
}
@@ -431,53 +431,53 @@ WRITE8_MEMBER(mz3500_state::mz3500_master_mem_w)
}
else if (m_ms == 3) // RAM based BASIC
{
- if((offset & 0xe000) == 0x0000) { mz3500_work_ram_w(space,offset & 0x1fff,data); return; }
+ if((offset & 0xe000) == 0x0000) { mz3500_work_ram_w(offset & 0x1fff,data); return; }
if((offset & 0xe000) == 0x2000)
{
switch(m_mo)
{
- case 0x0: mz3500_work_ram_w(space,(offset & 0x1fff) | 0x2000,data); return;
- case 0x1: mz3500_work_ram_w(space,(offset & 0x1fff) | 0xc000,data); return;
- case 0x2: mz3500_work_ram_w(space,(offset & 0x1fff) | 0xe000,data); return;
+ case 0x0: mz3500_work_ram_w((offset & 0x1fff) | 0x2000,data); return;
+ case 0x1: mz3500_work_ram_w((offset & 0x1fff) | 0xc000,data); return;
+ case 0x2: mz3500_work_ram_w((offset & 0x1fff) | 0xe000,data); return;
}
printf("Read with unmapped memory bank offset %04x MS %02x MO %02x\n",offset,m_ms,m_mo);
}
- if((offset & 0xc000) == 0x4000) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x4000,data); return; }
- if((offset & 0xc000) == 0x8000) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x8000,data); return; }
+ if((offset & 0xc000) == 0x4000) { mz3500_work_ram_w((offset & 0x3fff) | 0x4000,data); return; }
+ if((offset & 0xc000) == 0x8000) { mz3500_work_ram_w((offset & 0x3fff) | 0x8000,data); return; }
if((offset & 0xc000) == 0xc000)
{
switch(m_ma)
{
- case 0x0: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x10000,data); return;
- case 0x1: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x14000,data); return;
- case 0x2: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x18000,data); return;
- case 0x3: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x1c000,data); return;
- case 0x4: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x20000,data); return;
- case 0x5: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x24000,data); return;
- case 0x6: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x28000,data); return;
- case 0x7: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x2c000,data); return;
- case 0x8: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x30000,data); return;
- case 0x9: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x34000,data); return;
- case 0xa: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x38000,data); return;
- case 0xb: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x3c000,data); return;
- case 0xf: mz3500_shared_ram_w(space,(offset & 0x7ff),data); return;
+ case 0x0: mz3500_work_ram_w((offset & 0x3fff) | 0x10000,data); return;
+ case 0x1: mz3500_work_ram_w((offset & 0x3fff) | 0x14000,data); return;
+ case 0x2: mz3500_work_ram_w((offset & 0x3fff) | 0x18000,data); return;
+ case 0x3: mz3500_work_ram_w((offset & 0x3fff) | 0x1c000,data); return;
+ case 0x4: mz3500_work_ram_w((offset & 0x3fff) | 0x20000,data); return;
+ case 0x5: mz3500_work_ram_w((offset & 0x3fff) | 0x24000,data); return;
+ case 0x6: mz3500_work_ram_w((offset & 0x3fff) | 0x28000,data); return;
+ case 0x7: mz3500_work_ram_w((offset & 0x3fff) | 0x2c000,data); return;
+ case 0x8: mz3500_work_ram_w((offset & 0x3fff) | 0x30000,data); return;
+ case 0x9: mz3500_work_ram_w((offset & 0x3fff) | 0x34000,data); return;
+ case 0xa: mz3500_work_ram_w((offset & 0x3fff) | 0x38000,data); return;
+ case 0xb: mz3500_work_ram_w((offset & 0x3fff) | 0x3c000,data); return;
+ case 0xf: mz3500_shared_ram_w((offset & 0x7ff),data); return;
}
}
}
}
-READ8_MEMBER(mz3500_state::mz3500_shared_ram_r)
+uint8_t mz3500_state::mz3500_shared_ram_r(offs_t offset)
{
return m_shared_ram[offset];
}
-WRITE8_MEMBER(mz3500_state::mz3500_shared_ram_w)
+void mz3500_state::mz3500_shared_ram_w(offs_t offset, uint8_t data)
{
m_shared_ram[offset] = data;
}
-READ8_MEMBER(mz3500_state::mz3500_io_r)
+uint8_t mz3500_state::mz3500_io_r(offs_t offset)
{
/*
[2]
@@ -501,7 +501,7 @@ READ8_MEMBER(mz3500_state::mz3500_io_r)
return 0;
}
-WRITE8_MEMBER(mz3500_state::mz3500_io_w)
+void mz3500_state::mz3500_io_w(offs_t offset, uint8_t data)
{
/*
[0]
@@ -539,7 +539,7 @@ WRITE8_MEMBER(mz3500_state::mz3500_io_w)
}
}
-WRITE8_MEMBER(mz3500_state::mz3500_crtc_w)
+void mz3500_state::mz3500_crtc_w(offs_t offset, uint8_t data)
{
if(offset & 8)
{
@@ -552,7 +552,7 @@ WRITE8_MEMBER(mz3500_state::mz3500_crtc_w)
m_crtc[offset] = data;
}
-READ8_MEMBER(mz3500_state::mz3500_fdc_r)
+uint8_t mz3500_state::mz3500_fdc_r()
{
/*
---- -x-- Motor
@@ -565,7 +565,7 @@ READ8_MEMBER(mz3500_state::mz3500_fdc_r)
return (floppy->mon_r() << 2) | (floppy->idx_r() << 1) | (m_fdc->get_drq() & 1);
}
-WRITE8_MEMBER(mz3500_state::mz3500_fdc_w)
+void mz3500_state::mz3500_fdc_w(uint8_t data)
{
/*
x--- ---- FDC int enable
@@ -591,7 +591,7 @@ WRITE8_MEMBER(mz3500_state::mz3500_fdc_w)
}
-READ8_MEMBER(mz3500_state::mz3500_fdc_dma_r)
+uint8_t mz3500_state::mz3500_fdc_dma_r()
{
return m_fdc->dma_r();
}
diff --git a/src/mame/drivers/n64.cpp b/src/mame/drivers/n64.cpp
index 9735619262c..4a94be10476 100644
--- a/src/mame/drivers/n64.cpp
+++ b/src/mame/drivers/n64.cpp
@@ -34,7 +34,7 @@ public:
void n64dd(machine_config &config);
private:
- DECLARE_READ32_MEMBER(dd_null_r);
+ uint32_t dd_null_r();
DECLARE_MACHINE_START(n64dd);
INTERRUPT_GEN_MEMBER(n64_reset_poll);
DECLARE_DEVICE_IMAGE_LOAD_MEMBER(cart_load);
@@ -48,7 +48,7 @@ private:
void rsp_map(address_map &map);
};
-READ32_MEMBER(n64_mess_state::dd_null_r)
+uint32_t n64_mess_state::dd_null_r()
{
return 0xffffffff;
}
diff --git a/src/mame/drivers/nakajies.cpp b/src/mame/drivers/nakajies.cpp
index 0269a46e965..6bc65b490c2 100644
--- a/src/mame/drivers/nakajies.cpp
+++ b/src/mame/drivers/nakajies.cpp
@@ -308,24 +308,24 @@ private:
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
void nakajies_update_irqs();
- DECLARE_READ8_MEMBER( irq_clear_r );
- DECLARE_WRITE8_MEMBER( irq_clear_w );
- DECLARE_READ8_MEMBER( irq_enable_r );
- DECLARE_WRITE8_MEMBER( irq_enable_w );
- DECLARE_READ8_MEMBER( unk_a0_r );
- DECLARE_WRITE8_MEMBER( lcd_memory_start_w );
- DECLARE_READ8_MEMBER( keyboard_r );
- DECLARE_WRITE8_MEMBER( banking_w );
+ uint8_t irq_clear_r();
+ void irq_clear_w(uint8_t data);
+ uint8_t irq_enable_r();
+ void irq_enable_w(uint8_t data);
+ uint8_t unk_a0_r();
+ void lcd_memory_start_w(uint8_t data);
+ uint8_t keyboard_r();
+ void banking_w(offs_t offset, uint8_t data) ;
void update_banks();
void bank_w(uint8_t banknr, offs_t offset, uint8_t data);
- DECLARE_WRITE8_MEMBER( bank0_w );
- DECLARE_WRITE8_MEMBER( bank1_w );
- DECLARE_WRITE8_MEMBER( bank2_w );
- DECLARE_WRITE8_MEMBER( bank3_w );
- DECLARE_WRITE8_MEMBER( bank4_w );
- DECLARE_WRITE8_MEMBER( bank5_w );
- DECLARE_WRITE8_MEMBER( bank6_w );
- DECLARE_WRITE8_MEMBER( bank7_w );
+ void bank0_w(offs_t offset, uint8_t data) ;
+ void bank1_w(offs_t offset, uint8_t data) ;
+ void bank2_w(offs_t offset, uint8_t data) ;
+ void bank3_w(offs_t offset, uint8_t data) ;
+ void bank4_w(offs_t offset, uint8_t data) ;
+ void bank5_w(offs_t offset, uint8_t data) ;
+ void bank6_w(offs_t offset, uint8_t data) ;
+ void bank7_w(offs_t offset, uint8_t data) ;
void nakajies_palette(palette_device &palette) const;
TIMER_DEVICE_CALLBACK_MEMBER(kb_timer);
@@ -394,14 +394,14 @@ void nakajies_state::bank_w( uint8_t banknr, offs_t offset, uint8_t data )
}
}
-WRITE8_MEMBER( nakajies_state::bank0_w ) { bank_w( 0, offset, data ); }
-WRITE8_MEMBER( nakajies_state::bank1_w ) { bank_w( 1, offset, data ); }
-WRITE8_MEMBER( nakajies_state::bank2_w ) { bank_w( 2, offset, data ); }
-WRITE8_MEMBER( nakajies_state::bank3_w ) { bank_w( 3, offset, data ); }
-WRITE8_MEMBER( nakajies_state::bank4_w ) { bank_w( 4, offset, data ); }
-WRITE8_MEMBER( nakajies_state::bank5_w ) { bank_w( 5, offset, data ); }
-WRITE8_MEMBER( nakajies_state::bank6_w ) { bank_w( 6, offset, data ); }
-WRITE8_MEMBER( nakajies_state::bank7_w ) { bank_w( 7, offset, data ); }
+void nakajies_state::bank0_w(offs_t offset, uint8_t data) { bank_w( 0, offset, data ); }
+void nakajies_state::bank1_w(offs_t offset, uint8_t data) { bank_w( 1, offset, data ); }
+void nakajies_state::bank2_w(offs_t offset, uint8_t data) { bank_w( 2, offset, data ); }
+void nakajies_state::bank3_w(offs_t offset, uint8_t data) { bank_w( 3, offset, data ); }
+void nakajies_state::bank4_w(offs_t offset, uint8_t data) { bank_w( 4, offset, data ); }
+void nakajies_state::bank5_w(offs_t offset, uint8_t data) { bank_w( 5, offset, data ); }
+void nakajies_state::bank6_w(offs_t offset, uint8_t data) { bank_w( 6, offset, data ); }
+void nakajies_state::bank7_w(offs_t offset, uint8_t data) { bank_w( 7, offset, data ); }
void nakajies_state::nakajies_map(address_map &map)
@@ -449,26 +449,26 @@ void nakajies_state::nakajies_update_irqs()
}
-READ8_MEMBER( nakajies_state::irq_clear_r )
+uint8_t nakajies_state::irq_clear_r()
{
return 0x00;
}
-WRITE8_MEMBER( nakajies_state::irq_clear_w )
+void nakajies_state::irq_clear_w(uint8_t data)
{
m_irq_active &= ~data;
nakajies_update_irqs();
}
-READ8_MEMBER( nakajies_state::irq_enable_r )
+uint8_t nakajies_state::irq_enable_r()
{
return m_irq_enabled;
}
-WRITE8_MEMBER( nakajies_state::irq_enable_w )
+void nakajies_state::irq_enable_w(uint8_t data)
{
m_irq_enabled = data;
nakajies_update_irqs();
@@ -481,25 +481,25 @@ WRITE8_MEMBER( nakajies_state::irq_enable_w )
bit 3 - battery low (when set)
bit 2-0 - unknown
*/
-READ8_MEMBER( nakajies_state::unk_a0_r )
+uint8_t nakajies_state::unk_a0_r()
{
return 0xf7;
}
-WRITE8_MEMBER( nakajies_state::lcd_memory_start_w )
+void nakajies_state::lcd_memory_start_w(uint8_t data)
{
m_lcd_memory_start = data;
}
-WRITE8_MEMBER( nakajies_state::banking_w )
+void nakajies_state::banking_w(offs_t offset, uint8_t data)
{
m_bank[offset] = data;
update_banks();
}
-READ8_MEMBER( nakajies_state::keyboard_r )
+uint8_t nakajies_state::keyboard_r()
{
static const char *const bitnames[] = { "ROW0", "ROW1", "ROW2", "ROW3", "ROW4",
"ROW5", "ROW6", "ROW7", "ROW8", "ROW9" };
diff --git a/src/mame/drivers/namcos10.cpp b/src/mame/drivers/namcos10.cpp
index b54e80cb327..65012edf71e 100644
--- a/src/mame/drivers/namcos10.cpp
+++ b/src/mame/drivers/namcos10.cpp
@@ -446,30 +446,30 @@ public:
private:
// memm variant interface
- DECLARE_WRITE16_MEMBER(crypto_switch_w);
- DECLARE_READ16_MEMBER(range_r);
- DECLARE_WRITE16_MEMBER(bank_w);
+ void crypto_switch_w(uint16_t data);
+ uint16_t range_r(offs_t offset);
+ void bank_w(offs_t offset, uint16_t data);
// memn variant interface
- DECLARE_READ16_MEMBER(nand_status_r);
- DECLARE_WRITE8_MEMBER(nand_address1_w);
- DECLARE_WRITE8_MEMBER(nand_address2_w);
- DECLARE_WRITE8_MEMBER(nand_address3_w);
- DECLARE_WRITE8_MEMBER(nand_address4_w);
- DECLARE_READ16_MEMBER(nand_data_r);
- DECLARE_WRITE16_MEMBER(nand_block_w);
- DECLARE_READ16_MEMBER(nand_block_r);
-
- DECLARE_READ16_MEMBER (control_r);
- DECLARE_WRITE16_MEMBER(control_w);
-
- DECLARE_READ16_MEMBER (i2c_clock_r);
- DECLARE_WRITE16_MEMBER(i2c_clock_w);
- DECLARE_READ16_MEMBER (i2c_data_r);
- DECLARE_WRITE16_MEMBER(i2c_data_w);
-
- DECLARE_READ16_MEMBER (sprot_r);
- DECLARE_WRITE16_MEMBER(sprot_w);
+ uint16_t nand_status_r();
+ void nand_address1_w(uint8_t data);
+ void nand_address2_w(uint8_t data);
+ void nand_address3_w(uint8_t data);
+ void nand_address4_w(uint8_t data);
+ uint16_t nand_data_r();
+ void nand_block_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t nand_block_r(offs_t offset);
+
+ uint16_t control_r(offs_t offset);
+ void control_w(offs_t offset, uint16_t data);
+
+ uint16_t i2c_clock_r();
+ void i2c_clock_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t i2c_data_r();
+ void i2c_data_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+
+ uint16_t sprot_r();
+ void sprot_w(uint16_t data);
uint8_t *nand_base;
void nand_copy( uint32_t *dst, uint32_t address, int len );
@@ -529,7 +529,7 @@ void namcos10_state::namcos10_map(address_map &map)
// bios copies 62000-37ffff from the flash to 80012000 in ram through the
// decryption in range_r then jumps there
-WRITE16_MEMBER(namcos10_state::crypto_switch_w)
+void namcos10_state::crypto_switch_w(uint16_t data)
{
printf("crypto_switch_w: %04x\n", data);
if (decrypter == nullptr)
@@ -541,12 +541,12 @@ WRITE16_MEMBER(namcos10_state::crypto_switch_w)
decrypter->deactivate();
}
-WRITE16_MEMBER(namcos10_state::bank_w)
+void namcos10_state::bank_w(offs_t offset, uint16_t data)
{
bank_base = 0x100000 * offset;
}
-READ16_MEMBER(namcos10_state::range_r)
+uint16_t namcos10_state::range_r(offs_t offset)
{
uint16_t data = ((const uint16_t *)(memregion("maincpu:rom")->base()))[bank_base+offset];
@@ -559,7 +559,7 @@ READ16_MEMBER(namcos10_state::range_r)
return data;
}
-READ16_MEMBER(namcos10_state::control_r)
+uint16_t namcos10_state::control_r(offs_t offset)
{
logerror("%s: control_r %d (%x)\n", machine().describe_context(), offset);
if(offset == 2)
@@ -567,12 +567,12 @@ READ16_MEMBER(namcos10_state::control_r)
return 0;
}
-WRITE16_MEMBER(namcos10_state::control_w)
+void namcos10_state::control_w(offs_t offset, uint16_t data)
{
logerror("%s: control_w %d, %04x (%x)\n", machine().describe_context(), offset, data);
}
-WRITE16_MEMBER(namcos10_state::sprot_w)
+void namcos10_state::sprot_w(uint16_t data)
{
logerror("%s: sprot_w %04x (%x)\n", machine().describe_context(), data);
sprot_bit = 7;
@@ -587,7 +587,7 @@ WRITE16_MEMBER(namcos10_state::sprot_w)
// 800128e0: jal 1649c
// 800128e8: jal 2c47c
-READ16_MEMBER(namcos10_state::sprot_r)
+uint16_t namcos10_state::sprot_r()
{
// If line 3 has 0x30/0x31 in it, something happens. That
// something currently kills the system though.
@@ -610,7 +610,7 @@ READ16_MEMBER(namcos10_state::sprot_r)
return res;
}
-READ16_MEMBER(namcos10_state::i2c_clock_r)
+uint16_t namcos10_state::i2c_clock_r()
{
uint16_t res = i2c_dev_clock & i2c_host_clock & 1;
// logerror("i2c_clock_r %d (%x)\n", res, m_maincpu->pc());
@@ -618,14 +618,14 @@ READ16_MEMBER(namcos10_state::i2c_clock_r)
}
-WRITE16_MEMBER(namcos10_state::i2c_clock_w)
+void namcos10_state::i2c_clock_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&i2c_host_clock);
// logerror("i2c_clock_w %d (%x)\n", data, m_maincpu->pc());
i2c_update();
}
-READ16_MEMBER(namcos10_state::i2c_data_r)
+uint16_t namcos10_state::i2c_data_r()
{
uint16_t res = i2c_dev_data & i2c_host_data & 1;
// logerror("i2c_data_r %d (%x)\n", res, m_maincpu->pc());
@@ -633,7 +633,7 @@ READ16_MEMBER(namcos10_state::i2c_data_r)
}
-WRITE16_MEMBER(namcos10_state::i2c_data_w)
+void namcos10_state::i2c_data_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&i2c_host_data);
// logerror("i2c_data_w %d (%x)\n", data, m_maincpu->pc());
@@ -709,30 +709,30 @@ void namcos10_state::namcos10_memm_map(address_map &map)
// Block access to the nand. Something strange is going on with the
// status port. Interaction with the decryption is unclear at best.
-READ16_MEMBER(namcos10_state::nand_status_r )
+uint16_t namcos10_state::nand_status_r()
{
return 0;
}
-WRITE8_MEMBER(namcos10_state::nand_address1_w )
+void namcos10_state::nand_address1_w(uint8_t data)
{
logerror("%s: nand_a1_w %08x (%08x)\n", machine().describe_context(), data);
// nand_address = ( nand_address & 0x00ffffff ) | ( data << 24 );
}
-WRITE8_MEMBER( namcos10_state::nand_address2_w )
+void namcos10_state::nand_address2_w(uint8_t data)
{
logerror("%s: nand_a2_w %08x (%08x)\n", machine().describe_context(), data);
nand_address = ( nand_address & 0xffffff00 ) | ( data << 0 );
}
-WRITE8_MEMBER( namcos10_state::nand_address3_w )
+void namcos10_state::nand_address3_w(uint8_t data)
{
logerror("%s: nand_a3_w %08x (%08x)\n", machine().describe_context(), data);
nand_address = ( nand_address & 0xffff00ff ) | ( data << 8 );
}
-WRITE8_MEMBER( namcos10_state::nand_address4_w )
+void namcos10_state::nand_address4_w(uint8_t data)
{
nand_address = ( nand_address & 0xff00ffff ) | ( data << 16 );
logerror("%s: nand_a4_w %08x (%08x) -> %08x\n", machine().describe_context(), data, nand_address*2);
@@ -750,7 +750,7 @@ uint16_t namcos10_state::nand_read2( uint32_t address )
return nand_base[ index + 1 ] | ( nand_base[ index ] << 8 );
}
-READ16_MEMBER( namcos10_state::nand_data_r )
+uint16_t namcos10_state::nand_data_r()
{
uint16_t data = nand_read2( nand_address * 2 );
@@ -780,12 +780,12 @@ void namcos10_state::nand_copy( uint32_t *dst, uint32_t address, int len )
}
}
-WRITE16_MEMBER(namcos10_state::nand_block_w)
+void namcos10_state::nand_block_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA( &block[offset] );
}
-READ16_MEMBER(namcos10_state::nand_block_r)
+uint16_t namcos10_state::nand_block_r(offs_t offset)
{
return block[ offset ];
}
diff --git a/src/mame/drivers/namcos11.cpp b/src/mame/drivers/namcos11.cpp
index 2ab7cafb8ef..3d9f64a20bd 100644
--- a/src/mame/drivers/namcos11.cpp
+++ b/src/mame/drivers/namcos11.cpp
@@ -346,15 +346,15 @@ public:
void tekken2(machine_config &config);
private:
- DECLARE_WRITE16_MEMBER(rom8_w);
- DECLARE_WRITE16_MEMBER(rom8_64_upper_w);
- DECLARE_WRITE16_MEMBER(rom8_64_w);
- DECLARE_WRITE16_MEMBER(lightgun_w);
- DECLARE_READ16_MEMBER(lightgun_r);
- DECLARE_READ16_MEMBER(c76_shared_r);
- DECLARE_WRITE16_MEMBER(c76_shared_w);
- DECLARE_READ16_MEMBER(c76_speedup_r);
- DECLARE_WRITE16_MEMBER(c76_speedup_w);
+ void rom8_w(offs_t offset, uint16_t data);
+ void rom8_64_upper_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ void rom8_64_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ void lightgun_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t lightgun_r(offs_t offset, uint16_t mem_mask = ~0);
+ uint16_t c76_shared_r(offs_t offset);
+ void c76_shared_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t c76_speedup_r();
+ void c76_speedup_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
TIMER_DEVICE_CALLBACK_MEMBER(mcu_irq0_cb);
TIMER_DEVICE_CALLBACK_MEMBER(mcu_irq2_cb);
@@ -393,19 +393,19 @@ inline void ATTR_PRINTF(3,4) namcos11_state::verboselog( int n_level, const char
}
}
-WRITE16_MEMBER(namcos11_state::rom8_w)
+void namcos11_state::rom8_w(offs_t offset, uint16_t data)
{
m_bank[ offset ]->set_entry( ( ( data & 0xc0 ) >> 4 ) + ( data & 0x03 ) );
}
-WRITE16_MEMBER(namcos11_state::rom8_64_upper_w)
+void namcos11_state::rom8_64_upper_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
verboselog(2, "rom8_64_upper_w( %08x, %08x, %08x )\n", offset, data, mem_mask );
m_n_bankoffset = offset * 16;
}
-WRITE16_MEMBER(namcos11_state::rom8_64_w)
+void namcos11_state::rom8_64_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
verboselog(2, "rom8_64_w( %08x, %08x, %08x )\n", offset, data, mem_mask );
@@ -413,7 +413,7 @@ WRITE16_MEMBER(namcos11_state::rom8_64_w)
m_bank[ offset ]->set_entry( ( ( ( ( data & 0xc0 ) >> 3 ) + ( data & 0x07 ) ) ^ m_n_bankoffset ) );
}
-WRITE16_MEMBER(namcos11_state::lightgun_w)
+void namcos11_state::lightgun_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch( offset )
{
@@ -432,7 +432,7 @@ WRITE16_MEMBER(namcos11_state::lightgun_w)
}
}
-READ16_MEMBER(namcos11_state::lightgun_r)
+uint16_t namcos11_state::lightgun_r(offs_t offset, uint16_t mem_mask)
{
uint16_t data = 0;
@@ -466,12 +466,12 @@ READ16_MEMBER(namcos11_state::lightgun_r)
return data;
}
-READ16_MEMBER( namcos11_state::c76_shared_r )
+uint16_t namcos11_state::c76_shared_r(offs_t offset)
{
return m_sharedram.target()[ offset ];
}
-WRITE16_MEMBER( namcos11_state::c76_shared_w )
+void namcos11_state::c76_shared_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA( &m_sharedram.target()[ offset ] );
}
@@ -539,7 +539,7 @@ void namcos11_state::c76_map(address_map &map)
map(0x301000, 0x301001).nopw();
}
-READ16_MEMBER(namcos11_state::c76_speedup_r)
+uint16_t namcos11_state::c76_speedup_r()
{
if ((m_mcu->pc() == 0xc153) && (!(m_su_83 & 0xff00)))
{
@@ -549,7 +549,7 @@ READ16_MEMBER(namcos11_state::c76_speedup_r)
return m_su_83;
}
-WRITE16_MEMBER(namcos11_state::c76_speedup_w)
+void namcos11_state::c76_speedup_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_su_83);
}
@@ -561,7 +561,8 @@ void namcos11_state::driver_start()
{
m_su_83 = 0;
save_item( NAME(m_su_83) );
- m_mcu->space(AS_PROGRAM).install_readwrite_handler(0x82, 0x83, read16_delegate(*this, FUNC(namcos11_state::c76_speedup_r)), write16_delegate(*this, FUNC(namcos11_state::c76_speedup_w)));
+ m_mcu->space(AS_PROGRAM).install_read_handler(0x82, 0x83, read16smo_delegate(*this, FUNC(namcos11_state::c76_speedup_r)));
+ m_mcu->space(AS_PROGRAM).install_write_handler(0x82, 0x83, write16s_delegate(*this, FUNC(namcos11_state::c76_speedup_w)));
}
if( m_bankedroms != nullptr )
diff --git a/src/mame/drivers/namcos12.cpp b/src/mame/drivers/namcos12.cpp
index 06fd1d6e18f..8a90913b3d5 100644
--- a/src/mame/drivers/namcos12.cpp
+++ b/src/mame/drivers/namcos12.cpp
@@ -1180,30 +1180,30 @@ private:
uint8_t m_jvssense;
uint8_t m_tssio_port_4;
- DECLARE_READ16_MEMBER(s12_mcu_p6_r);
- DECLARE_READ16_MEMBER(iob_p4_r);
- DECLARE_READ16_MEMBER(iob_p6_r);
- DECLARE_WRITE16_MEMBER(iob_p4_w);
-
- DECLARE_WRITE16_MEMBER(sharedram_w);
- DECLARE_READ16_MEMBER(sharedram_r);
- DECLARE_WRITE16_MEMBER(bankoffset_w);
- DECLARE_WRITE16_MEMBER(dmaoffset_w);
- DECLARE_WRITE16_MEMBER(system11gun_w);
- DECLARE_READ16_MEMBER(system11gun_r);
- DECLARE_WRITE16_MEMBER(tektagt_protection_1_w);
- DECLARE_READ16_MEMBER(tektagt_protection_1_r);
- DECLARE_WRITE16_MEMBER(tektagt_protection_2_w);
- DECLARE_READ16_MEMBER(tektagt_protection_2_r);
- DECLARE_READ16_MEMBER(tektagt_protection_3_r);
- DECLARE_READ16_MEMBER(s12_mcu_p8_r);
- DECLARE_READ16_MEMBER(s12_mcu_jvs_p8_r);
- DECLARE_READ16_MEMBER(s12_mcu_pa_r);
- DECLARE_WRITE16_MEMBER(s12_mcu_pa_w);
- DECLARE_READ16_MEMBER(s12_mcu_portB_r);
- DECLARE_WRITE16_MEMBER(s12_mcu_portB_w);
- DECLARE_READ16_MEMBER(s12_mcu_gun_h_r);
- DECLARE_READ16_MEMBER(s12_mcu_gun_v_r);
+ uint16_t s12_mcu_p6_r();
+ uint16_t iob_p4_r();
+ uint16_t iob_p6_r();
+ void iob_p4_w(uint16_t data);
+
+ void sharedram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t sharedram_r(offs_t offset, uint16_t mem_mask = ~0);
+ void bankoffset_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ void dmaoffset_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ void system11gun_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t system11gun_r(offs_t offset, uint16_t mem_mask = ~0);
+ void tektagt_protection_1_w(offs_t offset, uint16_t data);
+ uint16_t tektagt_protection_1_r(offs_t offset);
+ void tektagt_protection_2_w(offs_t offset, uint16_t data);
+ uint16_t tektagt_protection_2_r(offs_t offset);
+ uint16_t tektagt_protection_3_r();
+ uint16_t s12_mcu_p8_r();
+ uint16_t s12_mcu_jvs_p8_r();
+ uint16_t s12_mcu_pa_r();
+ void s12_mcu_pa_w(uint16_t data);
+ uint16_t s12_mcu_portB_r();
+ void s12_mcu_portB_w(uint16_t data);
+ uint16_t s12_mcu_gun_h_r();
+ uint16_t s12_mcu_gun_v_r();
inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ... );
void namcos12_rom_read( uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size );
@@ -1240,19 +1240,19 @@ inline void ATTR_PRINTF(3,4) namcos12_state::verboselog( int n_level, const char
}
}
-WRITE16_MEMBER(namcos12_state::sharedram_w)
+void namcos12_state::sharedram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
verboselog(1, "sharedram_w( %08x, %08x, %08x )\n", ( offset * 4 ), data, mem_mask );
COMBINE_DATA( &m_sharedram[ offset ] );
}
-READ16_MEMBER(namcos12_state::sharedram_r)
+uint16_t namcos12_state::sharedram_r(offs_t offset, uint16_t mem_mask)
{
verboselog(1, "sharedram_r( %08x, %08x ) %08x\n", ( offset * 4 ), mem_mask, m_sharedram[ offset ] );
return m_sharedram[ offset ];
}
-WRITE16_MEMBER(namcos12_state::bankoffset_w)
+void namcos12_state::bankoffset_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
// Golgo 13 has different banking (maybe the keycus controls it?)
if(m_alt_bank)
@@ -1276,7 +1276,7 @@ WRITE16_MEMBER(namcos12_state::bankoffset_w)
verboselog(1, "bankoffset_w( %08x, %08x, %08x ) %08x\n", offset, data, mem_mask, m_n_bankoffset );
}
-WRITE16_MEMBER(namcos12_state::dmaoffset_w)
+void namcos12_state::dmaoffset_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
m_n_dmaoffset = ( offset * 2 ) | ( data << 16 );
@@ -1387,7 +1387,7 @@ void namcos12_state::tektagt_map(address_map &map)
map(0x1f700000, 0x1f700003).r(FUNC(namcos12_state::tektagt_protection_3_r));
}
-WRITE16_MEMBER(namcos12_state::system11gun_w)
+void namcos12_state::system11gun_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch (offset)
{
@@ -1412,7 +1412,7 @@ WRITE16_MEMBER(namcos12_state::system11gun_w)
}
}
-READ16_MEMBER(namcos12_state::system11gun_r)
+uint16_t namcos12_state::system11gun_r(offs_t offset, uint16_t mem_mask)
{
uint16_t data = 0;
@@ -1446,7 +1446,7 @@ READ16_MEMBER(namcos12_state::system11gun_r)
return data;
}
-WRITE16_MEMBER(namcos12_state::tektagt_protection_1_w)
+void namcos12_state::tektagt_protection_1_w(offs_t offset, uint16_t data)
{
// Second dma offset or protection ref values write
@@ -1467,7 +1467,7 @@ WRITE16_MEMBER(namcos12_state::tektagt_protection_1_w)
}
}
-READ16_MEMBER(namcos12_state::tektagt_protection_1_r)
+uint16_t namcos12_state::tektagt_protection_1_r(offs_t offset)
{
switch (offset)
{
@@ -1481,7 +1481,7 @@ READ16_MEMBER(namcos12_state::tektagt_protection_1_r)
return 0;
}
-WRITE16_MEMBER(namcos12_state::tektagt_protection_2_w)
+void namcos12_state::tektagt_protection_2_w(offs_t offset, uint16_t data)
{
switch (offset)
{
@@ -1494,7 +1494,7 @@ WRITE16_MEMBER(namcos12_state::tektagt_protection_2_w)
}
}
-READ16_MEMBER(namcos12_state::tektagt_protection_2_r)
+uint16_t namcos12_state::tektagt_protection_2_r(offs_t offset)
{
if( m_ttt_cnt == 2 )
{
@@ -1528,7 +1528,7 @@ READ16_MEMBER(namcos12_state::tektagt_protection_2_r)
return 0;
}
-READ16_MEMBER(namcos12_state::tektagt_protection_3_r)
+uint16_t namcos12_state::tektagt_protection_3_r()
{
m_has_tektagt_dma = 1;
// Always ignored
@@ -1537,8 +1537,7 @@ READ16_MEMBER(namcos12_state::tektagt_protection_3_r)
void namcos12_state::machine_reset()
{
- address_space &space = m_maincpu->space(AS_PROGRAM);
- bankoffset_w(space,0,0,0xffff);
+ bankoffset_w(0,0,0xffff);
m_jvssense = 1;
m_tssio_port_4 = 0;
@@ -1581,7 +1580,7 @@ void namcos12_state::s12h8rwjvsmap(address_map &map)
map(0x300030, 0x300031).noprw(); // most S12 bioses write here simply to generate a wait state. there is no deeper meaning.
}
-READ16_MEMBER(namcos12_state::s12_mcu_p8_r)
+uint16_t namcos12_state::s12_mcu_p8_r()
{
return 0x02;
}
@@ -1590,37 +1589,37 @@ READ16_MEMBER(namcos12_state::s12_mcu_p8_r)
// in System 12, bit 0 of H8/3002 port A is connected to its chip enable
// the actual I/O takes place through the H8/3002's serial port B.
-READ16_MEMBER(namcos12_state::s12_mcu_pa_r)
+uint16_t namcos12_state::s12_mcu_pa_r()
{
return m_sub_porta;
}
-WRITE16_MEMBER(namcos12_state::s12_mcu_pa_w)
+void namcos12_state::s12_mcu_pa_w(uint16_t data)
{
m_sub_porta = data;
m_rtc->ce_w((m_sub_portb & 0x20) && (m_sub_porta & 1));
m_settings->ce_w((m_sub_portb & 0x20) && !(m_sub_porta & 1));
}
-READ16_MEMBER(namcos12_state::s12_mcu_portB_r)
+uint16_t namcos12_state::s12_mcu_portB_r()
{
return m_sub_portb;
}
-WRITE16_MEMBER(namcos12_state::s12_mcu_portB_w)
+void namcos12_state::s12_mcu_portB_w(uint16_t data)
{
m_sub_portb = (m_sub_portb & 0x80) | (data & 0x7f);
m_rtc->ce_w((m_sub_portb & 0x20) && (m_sub_porta & 1));
m_settings->ce_w((m_sub_portb & 0x20) && !(m_sub_porta & 1));
}
-READ16_MEMBER(namcos12_state::s12_mcu_p6_r)
+uint16_t namcos12_state::s12_mcu_p6_r()
{
// bit 1 = JVS cable present sense (1 = I/O board plugged in)
return (m_jvssense << 1) | 0xfd;
}
-READ16_MEMBER(namcos12_state::s12_mcu_jvs_p8_r)
+uint16_t namcos12_state::s12_mcu_jvs_p8_r()
{
return 0x12; // bit 4 = JVS enable. aplarail requires it to be on, soulclbr & others will require JVS I/O if it's on
}
@@ -1666,12 +1665,12 @@ void namcos12_state::s12h8railiomap(address_map &map)
// Golgo 13 lightgun inputs
-READ16_MEMBER(namcos12_state::s12_mcu_gun_h_r)
+uint16_t namcos12_state::s12_mcu_gun_h_r()
{
return m_lightgun_io[0]->read();
}
-READ16_MEMBER(namcos12_state::s12_mcu_gun_v_r)
+uint16_t namcos12_state::s12_mcu_gun_v_r()
{
return m_lightgun_io[1]->read();
}
@@ -1839,12 +1838,12 @@ void namcos12_boothack_state::truckk(machine_config &config)
config.set_maximum_quantum(attotime::from_hz(2*115200));
}
-READ16_MEMBER(namcos12_state::iob_p4_r)
+uint16_t namcos12_state::iob_p4_r()
{
return m_tssio_port_4;
}
-WRITE16_MEMBER(namcos12_state::iob_p4_w)
+void namcos12_state::iob_p4_w(uint16_t data)
{
m_tssio_port_4 = data;
@@ -1852,7 +1851,7 @@ WRITE16_MEMBER(namcos12_state::iob_p4_w)
m_jvssense = (data & 0x04) ? 0 : 1;
}
-READ16_MEMBER(namcos12_state::iob_p6_r)
+uint16_t namcos12_state::iob_p6_r()
{
// d4 is service button
uint8_t sb = (m_service_io->read() & 1) << 4;
diff --git a/src/mame/drivers/namcos21.cpp b/src/mame/drivers/namcos21.cpp
index 5cc3ad9e4f5..ee8177e023d 100644
--- a/src/mame/drivers/namcos21.cpp
+++ b/src/mame/drivers/namcos21.cpp
@@ -346,25 +346,25 @@ private:
uint16_t m_winrun_color;
uint16_t m_winrun_gpu_register[0x10/2];
- DECLARE_READ16_MEMBER(video_enable_r);
- DECLARE_WRITE16_MEMBER(video_enable_w);
+ uint16_t video_enable_r();
+ void video_enable_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
- DECLARE_READ16_MEMBER(dpram_word_r);
- DECLARE_WRITE16_MEMBER(dpram_word_w);
+ uint16_t dpram_word_r(offs_t offset);
+ void dpram_word_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint8_t dpram_byte_r(offs_t offset);
void dpram_byte_w(offs_t offset, uint8_t data);
- DECLARE_READ16_MEMBER(winrun_gpu_color_r);
- DECLARE_WRITE16_MEMBER(winrun_gpu_color_w);
- DECLARE_READ16_MEMBER(winrun_gpu_register_r);
- DECLARE_WRITE16_MEMBER(winrun_gpu_register_w);
- DECLARE_WRITE16_MEMBER(winrun_gpu_videoram_w);
- DECLARE_READ16_MEMBER(winrun_gpu_videoram_r);
+ uint16_t winrun_gpu_color_r();
+ void winrun_gpu_color_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t winrun_gpu_register_r(offs_t offset);
+ void winrun_gpu_register_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ void winrun_gpu_videoram_w(offs_t offset, uint16_t data);
+ uint16_t winrun_gpu_videoram_r(offs_t offset);
- DECLARE_WRITE8_MEMBER(eeprom_w);
- DECLARE_READ8_MEMBER(eeprom_r);
+ void eeprom_w(offs_t offset, uint8_t data);
+ uint8_t eeprom_r(offs_t offset);
- DECLARE_WRITE8_MEMBER(sound_bankselect_w);
+ void sound_bankselect_w(uint8_t data);
void sound_reset_w(uint8_t data);
void system_reset_w(uint8_t data);
@@ -391,33 +391,32 @@ private:
void c140_map(address_map &map);
};
-READ16_MEMBER(namcos21_state::winrun_gpu_color_r)
+uint16_t namcos21_state::winrun_gpu_color_r()
{
return m_winrun_color;
}
-WRITE16_MEMBER(namcos21_state::winrun_gpu_color_w)
+void namcos21_state::winrun_gpu_color_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA( &m_winrun_color );
}
-READ16_MEMBER(namcos21_state::winrun_gpu_register_r)
+uint16_t namcos21_state::winrun_gpu_register_r(offs_t offset)
{
return m_winrun_gpu_register[offset];
}
-WRITE16_MEMBER(namcos21_state::winrun_gpu_register_w)
+void namcos21_state::winrun_gpu_register_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA( &m_winrun_gpu_register[offset] );
m_screen->update_partial(m_screen->vpos());
}
-WRITE16_MEMBER(namcos21_state::winrun_gpu_videoram_w)
+void namcos21_state::winrun_gpu_videoram_w(offs_t offset, uint16_t data)
{
int color = data>>8;
int mask = data&0xff;
- int i;
- for( i=0; i<8; i++ )
+ for( int i=0; i<8; i++ )
{
if( mask&(0x01<<i) )
{
@@ -427,7 +426,7 @@ WRITE16_MEMBER(namcos21_state::winrun_gpu_videoram_w)
}
}
-READ16_MEMBER(namcos21_state::winrun_gpu_videoram_r)
+uint16_t namcos21_state::winrun_gpu_videoram_r(offs_t offset)
{
return (m_gpu_videoram[offset]<<8) | m_gpu_maskram[offset];
}
@@ -483,12 +482,12 @@ uint32_t namcos21_state::screen_update(screen_device &screen, bitmap_ind16 &bitm
-READ16_MEMBER(namcos21_state::video_enable_r)
+uint16_t namcos21_state::video_enable_r()
{
return m_video_enable;
}
-WRITE16_MEMBER(namcos21_state::video_enable_w)
+void namcos21_state::video_enable_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA( &m_video_enable ); /* 0x40 = enable */
if( m_video_enable!=0 && m_video_enable!=0x40 )
@@ -501,12 +500,12 @@ WRITE16_MEMBER(namcos21_state::video_enable_w)
/* dual port ram memory handlers */
-READ16_MEMBER(namcos21_state::dpram_word_r)
+uint16_t namcos21_state::dpram_word_r(offs_t offset)
{
return m_dpram[offset];
}
-WRITE16_MEMBER(namcos21_state::dpram_word_w)
+void namcos21_state::dpram_word_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if( ACCESSING_BITS_0_7 )
{
@@ -765,7 +764,7 @@ static INPUT_PORTS_START( winrungp )
PORT_DIPSETTING( 0x00, "4M" )
INPUT_PORTS_END
-WRITE8_MEMBER( namcos21_state::sound_bankselect_w )
+void namcos21_state::sound_bankselect_w(uint8_t data)
{
m_audiobank->set_entry(data>>4);
}
@@ -799,12 +798,12 @@ void namcos21_state::reset_all_subcpus(int state)
m_c65->ext_reset(state);
}
-WRITE8_MEMBER(namcos21_state::eeprom_w)
+void namcos21_state::eeprom_w(offs_t offset, uint8_t data)
{
m_eeprom[offset] = data;
}
-READ8_MEMBER(namcos21_state::eeprom_r)
+uint8_t namcos21_state::eeprom_r(offs_t offset)
{
return m_eeprom[offset];
}
diff --git a/src/mame/drivers/namcos21_c67.cpp b/src/mame/drivers/namcos21_c67.cpp
index a5f21bbfe48..98b200292f3 100644
--- a/src/mame/drivers/namcos21_c67.cpp
+++ b/src/mame/drivers/namcos21_c67.cpp
@@ -325,18 +325,18 @@ private:
uint16_t m_video_enable;
- DECLARE_READ16_MEMBER(video_enable_r);
- DECLARE_WRITE16_MEMBER(video_enable_w);
+ uint16_t video_enable_r();
+ void video_enable_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
- DECLARE_READ16_MEMBER(dpram_word_r);
- DECLARE_WRITE16_MEMBER(dpram_word_w);
+ uint16_t dpram_word_r(offs_t offset);
+ void dpram_word_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint8_t dpram_byte_r(offs_t offset);
void dpram_byte_w(offs_t offset, uint8_t data);
- DECLARE_WRITE8_MEMBER(eeprom_w);
- DECLARE_READ8_MEMBER(eeprom_r);
+ void eeprom_w(offs_t offset, uint8_t data);
+ uint8_t eeprom_r(offs_t offset);
- DECLARE_WRITE8_MEMBER(sound_bankselect_w);
+ void sound_bankselect_w(uint8_t data);
void sound_reset_w(uint8_t data);
void system_reset_w(uint8_t data);
@@ -390,12 +390,12 @@ uint32_t namcos21_c67_state::screen_update(screen_device &screen, bitmap_ind16 &
return 0;
}
-READ16_MEMBER(namcos21_c67_state::video_enable_r)
+uint16_t namcos21_c67_state::video_enable_r()
{
return m_video_enable;
}
-WRITE16_MEMBER(namcos21_c67_state::video_enable_w)
+void namcos21_c67_state::video_enable_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA( &m_video_enable ); /* 0x40 = enable */
if( m_video_enable!=0 && m_video_enable!=0x40 )
@@ -408,12 +408,12 @@ WRITE16_MEMBER(namcos21_c67_state::video_enable_w)
/* dual port ram memory handlers */
-READ16_MEMBER(namcos21_c67_state::dpram_word_r)
+uint16_t namcos21_c67_state::dpram_word_r(offs_t offset)
{
return m_dpram[offset];
}
-WRITE16_MEMBER(namcos21_c67_state::dpram_word_w)
+void namcos21_c67_state::dpram_word_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if( ACCESSING_BITS_0_7 )
{
@@ -688,7 +688,7 @@ static INPUT_PORTS_START( aircomb )
INPUT_PORTS_END
-WRITE8_MEMBER( namcos21_c67_state::sound_bankselect_w )
+void namcos21_c67_state::sound_bankselect_w(uint8_t data)
{
m_audiobank->set_entry(data>>4);
}
@@ -729,12 +729,12 @@ void namcos21_c67_state::reset_all_subcpus(int state)
m_namcos21_dsp_c67->reset_dsps(state);
}
-WRITE8_MEMBER(namcos21_c67_state::eeprom_w)
+void namcos21_c67_state::eeprom_w(offs_t offset, uint8_t data)
{
m_eeprom[offset] = data;
}
-READ8_MEMBER(namcos21_c67_state::eeprom_r)
+uint8_t namcos21_c67_state::eeprom_r(offs_t offset)
{
return m_eeprom[offset];
}
diff --git a/src/mame/drivers/namcos21_de.cpp b/src/mame/drivers/namcos21_de.cpp
index e7f78b0f0a0..333483c4a31 100644
--- a/src/mame/drivers/namcos21_de.cpp
+++ b/src/mame/drivers/namcos21_de.cpp
@@ -91,18 +91,18 @@ private:
uint16_t m_video_enable;
- DECLARE_READ16_MEMBER(video_enable_r);
- DECLARE_WRITE16_MEMBER(video_enable_w);
+ uint16_t video_enable_r();
+ void video_enable_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
- DECLARE_READ16_MEMBER(dpram_word_r);
- DECLARE_WRITE16_MEMBER(dpram_word_w);
+ uint16_t dpram_word_r(offs_t offset);
+ void dpram_word_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint8_t dpram_byte_r(offs_t offset);
void dpram_byte_w(offs_t offset, uint8_t data);
- DECLARE_WRITE8_MEMBER(eeprom_w);
- DECLARE_READ8_MEMBER(eeprom_r);
+ void eeprom_w(offs_t offset, uint8_t data);
+ uint8_t eeprom_r(offs_t offset);
- DECLARE_WRITE8_MEMBER(sound_bankselect_w);
+ void sound_bankselect_w(uint8_t data);
void sound_reset_w(uint8_t data);
void system_reset_w(uint8_t data);
@@ -244,12 +244,12 @@ uint32_t namco_de_pcbstack_device::screen_update(screen_device &screen, bitmap_i
}
-READ16_MEMBER(namco_de_pcbstack_device::video_enable_r)
+uint16_t namco_de_pcbstack_device::video_enable_r()
{
return m_video_enable;
}
-WRITE16_MEMBER(namco_de_pcbstack_device::video_enable_w)
+void namco_de_pcbstack_device::video_enable_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA( &m_video_enable ); /* 0x40 = enable */
if( m_video_enable!=0 && m_video_enable!=0x40 )
@@ -262,12 +262,12 @@ WRITE16_MEMBER(namco_de_pcbstack_device::video_enable_w)
/* dual port ram memory handlers */
-READ16_MEMBER(namco_de_pcbstack_device::dpram_word_r)
+uint16_t namco_de_pcbstack_device::dpram_word_r(offs_t offset)
{
return m_dpram[offset];
}
-WRITE16_MEMBER(namco_de_pcbstack_device::dpram_word_w)
+void namco_de_pcbstack_device::dpram_word_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if( ACCESSING_BITS_0_7 )
{
@@ -383,7 +383,7 @@ void namco_de_pcbstack_device::driveyes_slave_map(address_map &map)
map(0x1c0000, 0x1fffff).m(m_slave_intc, FUNC(namco_c148_device::map));
}
-WRITE8_MEMBER( namco_de_pcbstack_device::sound_bankselect_w )
+void namco_de_pcbstack_device::sound_bankselect_w(uint8_t data)
{
m_audiobank->set_entry(data>>4);
}
@@ -417,12 +417,12 @@ void namco_de_pcbstack_device::reset_all_subcpus(int state)
m_c68->ext_reset(state);
}
-WRITE8_MEMBER(namco_de_pcbstack_device::eeprom_w)
+void namco_de_pcbstack_device::eeprom_w(offs_t offset, uint8_t data)
{
m_eeprom[offset] = data;
}
-READ8_MEMBER(namco_de_pcbstack_device::eeprom_r)
+uint8_t namco_de_pcbstack_device::eeprom_r(offs_t offset)
{
return m_eeprom[offset];
}
diff --git a/src/mame/drivers/namcos23.cpp b/src/mame/drivers/namcos23.cpp
index f326d30d025..73de0bfebc8 100644
--- a/src/mame/drivers/namcos23.cpp
+++ b/src/mame/drivers/namcos23.cpp
@@ -1458,52 +1458,52 @@ private:
void update_main_interrupts(uint32_t cause);
void update_mixer();
- DECLARE_WRITE32_MEMBER(textram_w);
- DECLARE_WRITE32_MEMBER(textchar_w);
- DECLARE_WRITE32_MEMBER(paletteram_w);
- DECLARE_READ16_MEMBER(c417_r);
- DECLARE_WRITE16_MEMBER(c417_w);
- DECLARE_READ16_MEMBER(c412_ram_r);
- DECLARE_WRITE16_MEMBER(c412_ram_w);
- DECLARE_READ16_MEMBER(c412_r);
- DECLARE_WRITE16_MEMBER(c412_w);
- DECLARE_READ16_MEMBER(c421_ram_r);
- DECLARE_WRITE16_MEMBER(c421_ram_w);
- DECLARE_READ16_MEMBER(c421_r);
- DECLARE_WRITE16_MEMBER(c421_w);
- DECLARE_WRITE16_MEMBER(ctl_w);
- DECLARE_READ16_MEMBER(ctl_r);
- DECLARE_WRITE16_MEMBER(c361_w);
- DECLARE_READ16_MEMBER(c361_r);
- DECLARE_READ16_MEMBER(c422_r);
- DECLARE_WRITE16_MEMBER(c422_w);
- DECLARE_WRITE16_MEMBER(mcuen_w);
- DECLARE_READ16_MEMBER(sub_comm_r);
- DECLARE_WRITE16_MEMBER(sub_comm_w);
- DECLARE_READ32_MEMBER(c435_r);
- DECLARE_WRITE32_MEMBER(c435_w);
- DECLARE_READ32_MEMBER(gmen_trigger_sh2);
- DECLARE_READ32_MEMBER(sh2_shared_r);
- DECLARE_WRITE32_MEMBER(sh2_shared_w);
- DECLARE_WRITE16_MEMBER(sharedram_sub_w);
- DECLARE_READ16_MEMBER(sharedram_sub_r);
- DECLARE_WRITE16_MEMBER(sub_interrupt_main_w);
- DECLARE_READ16_MEMBER(mcu_p8_r);
- DECLARE_WRITE16_MEMBER(mcu_p8_w);
- DECLARE_READ16_MEMBER(mcu_pa_r);
- DECLARE_WRITE16_MEMBER(mcu_pa_w);
- DECLARE_READ16_MEMBER(mcu_pb_r);
- DECLARE_WRITE16_MEMBER(mcu_pb_w);
- DECLARE_READ16_MEMBER(mcu_p6_r);
- DECLARE_WRITE16_MEMBER(mcu_p6_w);
- DECLARE_READ16_MEMBER(iob_p4_r);
- DECLARE_WRITE16_MEMBER(iob_p4_w);
- DECLARE_READ16_MEMBER(iob_p6_r);
- DECLARE_WRITE16_MEMBER(iob_p6_w);
- DECLARE_READ8_MEMBER(iob_gun_r);
- DECLARE_READ16_MEMBER(iob_analog_r);
- DECLARE_WRITE16_MEMBER(c435_state_pio_w);
- DECLARE_WRITE16_MEMBER(c435_state_reset_w);
+ void textram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ void textchar_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ void paletteram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint16_t c417_r(offs_t offset, uint16_t mem_mask = ~0);
+ void c417_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t c412_ram_r(offs_t offset);
+ void c412_ram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t c412_r(offs_t offset, uint16_t mem_mask = ~0);
+ void c412_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t c421_ram_r(offs_t offset);
+ void c421_ram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t c421_r(offs_t offset, uint16_t mem_mask = ~0);
+ void c421_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ void ctl_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t ctl_r(offs_t offset, uint16_t mem_mask = ~0);
+ void c361_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t c361_r(offs_t offset, uint16_t mem_mask = ~0);
+ uint16_t c422_r(offs_t offset);
+ void c422_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ void mcuen_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t sub_comm_r(offs_t offset);
+ void sub_comm_w(offs_t offset, uint16_t data);
+ uint32_t c435_r(offs_t offset, uint32_t mem_mask = ~0);
+ void c435_w(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t gmen_trigger_sh2();
+ uint32_t sh2_shared_r(offs_t offset);
+ void sh2_shared_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ void sharedram_sub_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t sharedram_sub_r(offs_t offset);
+ void sub_interrupt_main_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t mcu_p8_r();
+ void mcu_p8_w(uint16_t data);
+ uint16_t mcu_pa_r();
+ void mcu_pa_w(uint16_t data);
+ uint16_t mcu_pb_r();
+ void mcu_pb_w(uint16_t data);
+ uint16_t mcu_p6_r();
+ void mcu_p6_w(uint16_t data);
+ uint16_t iob_p4_r();
+ void iob_p4_w(uint16_t data);
+ uint16_t iob_p6_r();
+ void iob_p6_w(uint16_t data);
+ uint8_t iob_gun_r(offs_t offset);
+ uint16_t iob_analog_r(offs_t offset);
+ void c435_state_pio_w(uint16_t data);
+ void c435_state_reset_w(uint16_t data);
TILE_GET_INFO_MEMBER(TextTilemapGetInfo);
DECLARE_VIDEO_START(s23);
@@ -1764,12 +1764,12 @@ void namcos23_state::c435_state_set(uint16_t type, const uint16_t *param)
}
}
-WRITE16_MEMBER(namcos23_state::c435_state_reset_w)
+void namcos23_state::c435_state_reset_w(uint16_t data)
{
m_c435_buffer_pos = 0;
}
-WRITE16_MEMBER(namcos23_state::c435_state_pio_w)
+void namcos23_state::c435_state_pio_w(uint16_t data)
{
m_c435_buffer[m_c435_buffer_pos++] = data;
int psize = c435_get_state_entry_size(m_c435_buffer[0]);
@@ -2019,7 +2019,7 @@ void namcos23_state::c435_dma(address_space &space, uint32_t adr, uint32_t size)
c435_pio_w(space.read_word(adr+pos));
}
-READ32_MEMBER(namcos23_state::c435_r)
+uint32_t namcos23_state::c435_r(offs_t offset, uint32_t mem_mask)
{
switch(offset) {
case 0xa:
@@ -2030,7 +2030,7 @@ READ32_MEMBER(namcos23_state::c435_r)
return 0;
}
-WRITE32_MEMBER(namcos23_state::c435_w)
+void namcos23_state::c435_w(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask)
{
switch(offset) {
case 0x7:
@@ -2365,7 +2365,7 @@ void namcos23_state::update_mixer()
m_c404.layer = nthword(m_gammaram, 0x1f) & 0xff;
}
-WRITE32_MEMBER(namcos23_state::paletteram_w)
+void namcos23_state::paletteram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_generic_paletteram_32[offset]);
@@ -2394,14 +2394,14 @@ TILE_GET_INFO_MEMBER(namcos23_state::TextTilemapGetInfo)
tileinfo.set(0, data&0x03ff, data>>12, TILE_FLIPYX((data&0x0c00)>>10));
}
-WRITE32_MEMBER(namcos23_state::textram_w)
+void namcos23_state::textram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA( &m_textram[offset] );
m_bgtilemap->mark_tile_dirty(offset*2);
m_bgtilemap->mark_tile_dirty((offset*2)+1);
}
-WRITE32_MEMBER(namcos23_state::textchar_w)
+void namcos23_state::textchar_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_charram[offset]);
m_gfxdecode->gfx(0)->mark_dirty(offset/32);
@@ -2499,7 +2499,7 @@ WRITE_LINE_MEMBER(namcos23_state::sub_irq)
// C417
-READ16_MEMBER(namcos23_state::c417_r)
+uint16_t namcos23_state::c417_r(offs_t offset, uint16_t mem_mask)
{
switch(offset) {
/* According to timecrs2v4a, +0 is the status word with bits being:
@@ -2538,7 +2538,7 @@ READ16_MEMBER(namcos23_state::c417_r)
return 0;
}
-WRITE16_MEMBER(namcos23_state::c417_w)
+void namcos23_state::c417_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset) {
case 0:
@@ -2571,7 +2571,7 @@ WRITE16_MEMBER(namcos23_state::c417_w)
// C412
-READ16_MEMBER(namcos23_state::c412_ram_r)
+uint16_t namcos23_state::c412_ram_r(offs_t offset)
{
// logerror("c412_ram_r %06x (%08x, %08x)\n", offset, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
if(offset < 0x100000)
@@ -2586,7 +2586,7 @@ READ16_MEMBER(namcos23_state::c412_ram_r)
return 0xffff;
}
-WRITE16_MEMBER(namcos23_state::c412_ram_w)
+void namcos23_state::c412_ram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
// logerror("c412_ram_w %06x = %04x (%08x, %08x)\n", offset, data, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
if(offset < 0x100000)
@@ -2599,7 +2599,7 @@ WRITE16_MEMBER(namcos23_state::c412_ram_w)
COMBINE_DATA(m_c412.pczram + (offset & 0x001ff));
}
-READ16_MEMBER(namcos23_state::c412_r)
+uint16_t namcos23_state::c412_r(offs_t offset, uint16_t mem_mask)
{
switch(offset) {
case 0x3:
@@ -2609,7 +2609,7 @@ READ16_MEMBER(namcos23_state::c412_r)
case 0x9:
return m_c412.adr >> 16;
case 0xa:
- return c412_ram_r(space, m_c412.adr, mem_mask);
+ return c412_ram_r(m_c412.adr);
case 0xc:
// unknown status, 500gp reads it and waits for a transition
// no other games use it?
@@ -2621,7 +2621,7 @@ READ16_MEMBER(namcos23_state::c412_r)
return 0;
}
-WRITE16_MEMBER(namcos23_state::c412_w)
+void namcos23_state::c412_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset) {
case 0x2:
@@ -2635,7 +2635,7 @@ WRITE16_MEMBER(namcos23_state::c412_w)
m_c412.adr = ((data & mem_mask) << 16) | (m_c412.adr & (0xffffffff ^ (mem_mask << 16)));
break;
case 0xa:
- c412_ram_w(space, m_c412.adr, data, mem_mask);
+ c412_ram_w(m_c412.adr, data, mem_mask);
m_c412.adr += 2;
break;
default:
@@ -2648,7 +2648,7 @@ WRITE16_MEMBER(namcos23_state::c412_w)
// C421
-READ16_MEMBER(namcos23_state::c421_ram_r)
+uint16_t namcos23_state::c421_ram_r(offs_t offset)
{
// logerror("c421_ram_r %06x (%08x, %08x)\n", offset, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
if(offset < 0x40000)
@@ -2661,7 +2661,7 @@ READ16_MEMBER(namcos23_state::c421_ram_r)
return 0xffff;
}
-WRITE16_MEMBER(namcos23_state::c421_ram_w)
+void namcos23_state::c421_ram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
// logerror("c421_ram_w %06x = %04x (%08x, %08x)\n", offset, data, m_maincpu->pc(), (unsigned int)m_maincpu->state_int(MIPS3_R31));
if(offset < 0x40000)
@@ -2672,11 +2672,11 @@ WRITE16_MEMBER(namcos23_state::c421_ram_w)
COMBINE_DATA(m_c421.sram + (offset & 0x07fff));
}
-READ16_MEMBER(namcos23_state::c421_r)
+uint16_t namcos23_state::c421_r(offs_t offset, uint16_t mem_mask)
{
switch(offset) {
case 0:
- return c421_ram_r(space, m_c421.adr & 0xfffff, mem_mask);
+ return c421_ram_r(m_c421.adr & 0xfffff);
case 2:
return m_c421.adr >> 16;
@@ -2688,11 +2688,11 @@ READ16_MEMBER(namcos23_state::c421_r)
return 0;
}
-WRITE16_MEMBER(namcos23_state::c421_w)
+void namcos23_state::c421_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset) {
case 0:
- c421_ram_w(space, m_c421.adr & 0xfffff, data, mem_mask);
+ c421_ram_w(m_c421.adr & 0xfffff, data, mem_mask);
m_c421.adr += 2;
break;
case 2:
@@ -2711,12 +2711,12 @@ WRITE16_MEMBER(namcos23_state::c421_w)
// C422
-READ16_MEMBER(namcos23_state::c422_r)
+uint16_t namcos23_state::c422_r(offs_t offset)
{
return m_c422.regs[offset];
}
-WRITE16_MEMBER(namcos23_state::c422_w)
+void namcos23_state::c422_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset) {
case 1:
@@ -2756,7 +2756,7 @@ TIMER_CALLBACK_MEMBER(namcos23_state::c361_timer_cb)
update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
}
-WRITE16_MEMBER(namcos23_state::c361_w)
+void namcos23_state::c361_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset) {
case 0:
@@ -2778,7 +2778,7 @@ WRITE16_MEMBER(namcos23_state::c361_w)
}
}
-READ16_MEMBER(namcos23_state::c361_r)
+uint16_t namcos23_state::c361_r(offs_t offset, uint16_t mem_mask)
{
switch(offset) {
// current raster position
@@ -2799,7 +2799,7 @@ READ16_MEMBER(namcos23_state::c361_r)
// C?? (control)
-WRITE16_MEMBER(namcos23_state::ctl_w)
+void namcos23_state::ctl_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset) {
case 0:
@@ -2832,7 +2832,7 @@ WRITE16_MEMBER(namcos23_state::ctl_w)
}
}
-READ16_MEMBER(namcos23_state::ctl_r)
+uint16_t namcos23_state::ctl_r(offs_t offset, uint16_t mem_mask)
{
switch(offset) {
// 0100 set freezes gorgon (polygon fifo flag)
@@ -2853,7 +2853,7 @@ READ16_MEMBER(namcos23_state::ctl_r)
// C?? (MCU enable)
-WRITE16_MEMBER(namcos23_state::mcuen_w)
+void namcos23_state::mcuen_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset) {
case 2:
@@ -2893,7 +2893,7 @@ WRITE16_MEMBER(namcos23_state::mcuen_w)
// while getting the subcpu to be ready, panicprk sits in a tight loop waiting for this AND 0002 to be non-zero (at PC=BFC02F00)
// timecrs2 locks up in a similar way as panicprk, at the beginning of the 2nd level, by reading/writing to this register a couple of times
-READ16_MEMBER(namcos23_state::sub_comm_r)
+uint16_t namcos23_state::sub_comm_r(offs_t offset)
{
// status register
if (offset == 0)
@@ -2912,7 +2912,7 @@ READ16_MEMBER(namcos23_state::sub_comm_r)
return m_mcu_unk; //machine().rand();
}
-WRITE16_MEMBER(namcos23_state::sub_comm_w)
+void namcos23_state::sub_comm_w(offs_t offset, uint16_t data)
{
if (offset == 1)
{
@@ -2981,7 +2981,7 @@ void namcos23_state::s23_map(address_map &map)
// GMEN interface
-READ32_MEMBER(namcos23_state::gmen_trigger_sh2)
+uint32_t namcos23_state::gmen_trigger_sh2()
{
logerror("gmen_trigger_sh2: booting SH-2\n");
m_gmen_sh2->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
@@ -2989,12 +2989,12 @@ READ32_MEMBER(namcos23_state::gmen_trigger_sh2)
return 0;
}
-READ32_MEMBER(namcos23_state::sh2_shared_r)
+uint32_t namcos23_state::sh2_shared_r(offs_t offset)
{
return m_gmen_sh2_shared[offset];
}
-WRITE32_MEMBER(namcos23_state::sh2_shared_w)
+void namcos23_state::sh2_shared_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_gmen_sh2_shared[offset]);
}
@@ -3029,7 +3029,7 @@ void namcos23_state::gmen_sh2_map(address_map &map)
***************************************************************************/
-WRITE16_MEMBER(namcos23_state::sharedram_sub_w)
+void namcos23_state::sharedram_sub_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
uint16_t *shared16 = reinterpret_cast<uint16_t *>(m_shared_ram.target());
@@ -3043,7 +3043,7 @@ WRITE16_MEMBER(namcos23_state::sharedram_sub_w)
COMBINE_DATA(&shared16[BYTE_XOR_BE(offset)]);
}
-READ16_MEMBER(namcos23_state::sharedram_sub_r)
+uint16_t namcos23_state::sharedram_sub_r(offs_t offset)
{
uint16_t *shared16 = reinterpret_cast<uint16_t *>(m_shared_ram.target());
@@ -3051,7 +3051,7 @@ READ16_MEMBER(namcos23_state::sharedram_sub_r)
}
-WRITE16_MEMBER(namcos23_state::sub_interrupt_main_w)
+void namcos23_state::sub_interrupt_main_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if((mem_mask == 0xffff) && (data == 0x3170)) {
update_main_interrupts(m_main_irqcause | MAIN_SUBCPU_IRQ);
@@ -3064,13 +3064,13 @@ WRITE16_MEMBER(namcos23_state::sub_interrupt_main_w)
// Port 6
-READ16_MEMBER(namcos23_state::mcu_p6_r)
+uint16_t namcos23_state::mcu_p6_r()
{
// bit 1 = JVS cable present sense (1 = I/O board plugged in)
return (m_jvssense << 1) | 0xfd;
}
-WRITE16_MEMBER(namcos23_state::mcu_p6_w)
+void namcos23_state::mcu_p6_w(uint16_t data)
{
//printf("%02x to port 6\n", data);
}
@@ -3079,12 +3079,12 @@ WRITE16_MEMBER(namcos23_state::mcu_p6_w)
// Port 8, looks like serial comms, where to/from?
-READ16_MEMBER(namcos23_state::mcu_p8_r)
+uint16_t namcos23_state::mcu_p8_r()
{
return 0x02;
}
-WRITE16_MEMBER(namcos23_state::mcu_p8_w)
+void namcos23_state::mcu_p8_w(uint16_t data)
{
;
}
@@ -3093,12 +3093,12 @@ WRITE16_MEMBER(namcos23_state::mcu_p8_w)
// Port A
-READ16_MEMBER(namcos23_state::mcu_pa_r)
+uint16_t namcos23_state::mcu_pa_r()
{
return m_sub_porta;
}
-WRITE16_MEMBER(namcos23_state::mcu_pa_w)
+void namcos23_state::mcu_pa_w(uint16_t data)
{
m_rtc->ce_w(data & 1);
m_sub_porta = data;
@@ -3110,12 +3110,12 @@ WRITE16_MEMBER(namcos23_state::mcu_pa_w)
// Port B
-READ16_MEMBER(namcos23_state::mcu_pb_r)
+uint16_t namcos23_state::mcu_pb_r()
{
return m_sub_portb;
}
-WRITE16_MEMBER(namcos23_state::mcu_pb_w)
+void namcos23_state::mcu_pb_w(uint16_t data)
{
m_sub_portb = (m_sub_portb & 0xc0) | (data & 0x3f);
m_rtc->ce_w((m_sub_portb & 0x20) && (m_sub_porta & 1));
@@ -3159,12 +3159,12 @@ void namcos23_state::s23h8iomap(address_map &map)
// Port 4
-READ16_MEMBER(namcos23_state::iob_p4_r)
+uint16_t namcos23_state::iob_p4_r()
{
return m_tssio_port_4;
}
-WRITE16_MEMBER(namcos23_state::iob_p4_w)
+void namcos23_state::iob_p4_w(uint16_t data)
{
m_tssio_port_4 = data;
@@ -3176,7 +3176,7 @@ WRITE16_MEMBER(namcos23_state::iob_p4_w)
// Port 6
-READ16_MEMBER(namcos23_state::iob_p6_r)
+uint16_t namcos23_state::iob_p6_r()
{
// d4 is service button
uint8_t sb = (ioport("SERVICE")->read() & 1) << 4;
@@ -3185,7 +3185,7 @@ READ16_MEMBER(namcos23_state::iob_p6_r)
return sb | 0;
}
-WRITE16_MEMBER(namcos23_state::iob_p6_w)
+void namcos23_state::iob_p6_w(uint16_t data)
{
//printf("iob %02x to port 6\n", data);
}
@@ -3193,7 +3193,7 @@ WRITE16_MEMBER(namcos23_state::iob_p6_w)
// Analog Ports
-READ16_MEMBER(namcos23_state::iob_analog_r)
+uint16_t namcos23_state::iob_analog_r(offs_t offset)
{
return m_adc_ports[offset].read_safe(0);
}
@@ -3222,7 +3222,7 @@ void namcos23_state::s23iobrdiomap(address_map &map)
// Time Crisis lightgun
-READ8_MEMBER(namcos23_state::iob_gun_r)
+uint8_t namcos23_state::iob_gun_r(offs_t offset)
{
uint16_t xpos = m_lightx->read();
uint16_t ypos = m_lighty->read();
diff --git a/src/mame/drivers/nanos.cpp b/src/mame/drivers/nanos.cpp
index 43ed2d29351..58710a1fb80 100644
--- a/src/mame/drivers/nanos.cpp
+++ b/src/mame/drivers/nanos.cpp
@@ -59,7 +59,7 @@ protected:
virtual void machine_start() override;
private:
- DECLARE_WRITE8_MEMBER(tc_w);
+ void tc_w(uint8_t data);
DECLARE_WRITE_LINE_MEMBER(ctc_z0_w);
DECLARE_WRITE_LINE_MEMBER(ctc_z1_w);
DECLARE_WRITE_LINE_MEMBER(ctc_z2_w);
@@ -108,7 +108,7 @@ void nanos_state::mem_map(address_map &map)
map(0x1000, 0xffff).bankrw(m_bank2);
}
-WRITE8_MEMBER(nanos_state::tc_w)
+void nanos_state::tc_w(uint8_t data)
{
m_fdc->tc_w(BIT(data,1));
}
diff --git a/src/mame/drivers/nascom1.cpp b/src/mame/drivers/nascom1.cpp
index 4c5ed87ee3d..30eb112a519 100644
--- a/src/mame/drivers/nascom1.cpp
+++ b/src/mame/drivers/nascom1.cpp
@@ -76,11 +76,11 @@ protected:
virtual void machine_reset() override;
- DECLARE_READ8_MEMBER(nascom1_port_00_r);
- DECLARE_WRITE8_MEMBER(nascom1_port_00_w);
- DECLARE_READ8_MEMBER(nascom1_port_01_r);
- DECLARE_WRITE8_MEMBER(nascom1_port_01_w);
- DECLARE_READ8_MEMBER(nascom1_port_02_r);
+ uint8_t nascom1_port_00_r();
+ void nascom1_port_00_w(uint8_t data);
+ uint8_t nascom1_port_01_r();
+ void nascom1_port_01_w(uint8_t data);
+ uint8_t nascom1_port_02_r();
DECLARE_READ_LINE_MEMBER(hd6402_si);
DECLARE_WRITE_LINE_MEMBER(hd6402_so);
@@ -175,12 +175,12 @@ private:
// KEYBOARD
//**************************************************************************
-READ8_MEMBER( nascom_state::nascom1_port_00_r )
+uint8_t nascom_state::nascom1_port_00_r()
{
return m_keyboard[m_kb_select]->read() | ~0x7f;
}
-WRITE8_MEMBER( nascom_state::nascom1_port_00_w )
+void nascom_state::nascom1_port_00_w(uint8_t data)
{
u8 bits = data ^ m_port00;
@@ -203,17 +203,17 @@ WRITE8_MEMBER( nascom_state::nascom1_port_00_w )
// CASSETTE
//**************************************************************************
-READ8_MEMBER( nascom_state::nascom1_port_01_r )
+uint8_t nascom_state::nascom1_port_01_r()
{
return m_hd6402->receive();
}
-WRITE8_MEMBER( nascom_state::nascom1_port_01_w )
+void nascom_state::nascom1_port_01_w(uint8_t data)
{
m_hd6402->transmit(data);
}
-READ8_MEMBER( nascom_state::nascom1_port_02_r )
+uint8_t nascom_state::nascom1_port_02_r()
{
uint8_t data = 0x31; // bits 0,4,5 not used
diff --git a/src/mame/drivers/ncdmips.cpp b/src/mame/drivers/ncdmips.cpp
index 2dc5edff57d..efefc81f9f6 100644
--- a/src/mame/drivers/ncdmips.cpp
+++ b/src/mame/drivers/ncdmips.cpp
@@ -48,8 +48,8 @@ private:
optional_shared_ptr<uint32_t> m_mainram;
required_device<scn2681_device> m_duart;
- DECLARE_READ32_MEMBER(unk_r);
- DECLARE_WRITE32_MEMBER(tty_w);
+ u32 unk_r();
+ void tty_w(u32 data);
inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ... );
@@ -94,12 +94,12 @@ uint32_t ncd_mips_state::screen_update(screen_device &screen, bitmap_rgb32 &bitm
return 0;
}
-READ32_MEMBER(ncd_mips_state::unk_r)
+u32 ncd_mips_state::unk_r()
{
return 0xffffffff;
}
-WRITE32_MEMBER(ncd_mips_state::tty_w)
+void ncd_mips_state::tty_w(u32 data)
{
printf("%c", (data>>16) & 0x7f);
}
diff --git a/src/mame/drivers/ncdppc.cpp b/src/mame/drivers/ncdppc.cpp
index c6e7bac842b..2ab1fbe2c36 100644
--- a/src/mame/drivers/ncdppc.cpp
+++ b/src/mame/drivers/ncdppc.cpp
@@ -43,8 +43,8 @@ private:
required_device<screen_device> m_screen;
optional_shared_ptr<uint32_t> m_mainram;
- DECLARE_READ32_MEMBER(unk_r);
- DECLARE_WRITE32_MEMBER(tty_w);
+ uint32_t unk_r();
+ void tty_w(uint32_t data);
inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ... );
};
@@ -78,12 +78,12 @@ uint32_t ncd_ppc_state::screen_update(screen_device &screen, bitmap_rgb32 &bitma
return 0;
}
-READ32_MEMBER(ncd_ppc_state::unk_r)
+uint32_t ncd_ppc_state::unk_r()
{
return 0xffffffff;
}
-WRITE32_MEMBER(ncd_ppc_state::tty_w)
+void ncd_ppc_state::tty_w(uint32_t data)
{
printf("%c", (data>>24) & 0x7f);
}
diff --git a/src/mame/drivers/neogeocd.cpp b/src/mame/drivers/neogeocd.cpp
index 71b270bebee..9cc22fe75be 100644
--- a/src/mame/drivers/neogeocd.cpp
+++ b/src/mame/drivers/neogeocd.cpp
@@ -73,12 +73,12 @@ public:
void do_dma(address_space& curr_space);
void set_dma_regs(int offset, uint16_t wordValue);
- DECLARE_READ16_MEMBER(memcard_r);
- DECLARE_WRITE16_MEMBER(memcard_w);
- DECLARE_READ16_MEMBER(control_r);
- DECLARE_WRITE16_MEMBER(control_w);
- DECLARE_READ8_MEMBER(transfer_r);
- DECLARE_WRITE8_MEMBER(transfer_w);
+ uint16_t memcard_r(offs_t offset);
+ void memcard_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t control_r(offs_t offset);
+ void control_w(address_space &space, offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint8_t transfer_r(offs_t offset);
+ void transfer_w(offs_t offset, uint8_t data);
DECLARE_INPUT_CHANGED_MEMBER(aes_jp1);
@@ -153,13 +153,13 @@ protected:
/* The NeoCD has an 8kB internal memory card, instead of memcard slots like the MVS and AES */
-READ16_MEMBER(ngcd_state::memcard_r)
+uint16_t ngcd_state::memcard_r(offs_t offset)
{
return m_meminternal_data[offset] | 0xff00;
}
-WRITE16_MEMBER(ngcd_state::memcard_w)
+void ngcd_state::memcard_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
{
@@ -174,7 +174,7 @@ WRITE16_MEMBER(ngcd_state::memcard_w)
*
*************************************/
-READ16_MEMBER(ngcd_state::control_r)
+uint16_t ngcd_state::control_r(offs_t offset)
{
uint32_t sekAddress = 0xff0000+ (offset*2);
@@ -184,7 +184,7 @@ READ16_MEMBER(ngcd_state::control_r)
// LC8951 registers
case 0x0100:
- return m_tempcdc->segacd_cdc_mode_address_r(space, 0, 0xffff);
+ return m_tempcdc->segacd_cdc_mode_address_r();
case 0x0102:
return m_tempcdc->CDC_Reg_r();
@@ -203,7 +203,7 @@ READ16_MEMBER(ngcd_state::control_r)
}
-WRITE16_MEMBER(ngcd_state::control_w)
+void ngcd_state::control_w(address_space &space, offs_t offset, uint16_t data, uint16_t mem_mask)
{
uint32_t sekAddress = 0xff0000+ (offset*2);
uint16_t wordValue = data;
@@ -260,7 +260,7 @@ WRITE16_MEMBER(ngcd_state::control_w)
// LC8951 registers
case 0x0100:
- m_tempcdc->segacd_cdc_mode_address_w(space, 0, byteValue, 0xffff);
+ m_tempcdc->segacd_cdc_mode_address_w(0, byteValue, 0xffff);
break;
case 0x0102:
m_tempcdc->CDC_Reg_w(byteValue);
@@ -402,7 +402,7 @@ WRITE16_MEMBER(ngcd_state::control_w)
*/
-READ8_MEMBER(ngcd_state::transfer_r)
+uint8_t ngcd_state::transfer_r(offs_t offset)
{
uint32_t sekAddress = 0xe00000+ (offset);
int address;
@@ -432,7 +432,7 @@ READ8_MEMBER(ngcd_state::transfer_r)
}
-WRITE8_MEMBER(ngcd_state::transfer_w)
+void ngcd_state::transfer_w(offs_t offset, uint8_t data)
{
uint8_t byteValue = data;
uint32_t sekAddress = 0xe00000+ (offset);
diff --git a/src/mame/drivers/neopcb.cpp b/src/mame/drivers/neopcb.cpp
index f678a169d2d..6ee9087b3a0 100644
--- a/src/mame/drivers/neopcb.cpp
+++ b/src/mame/drivers/neopcb.cpp
@@ -36,7 +36,7 @@ protected:
virtual void device_post_load() override;
- DECLARE_WRITE16_MEMBER(write_bankpvc);
+ void write_bankpvc(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void install_common();
void install_banked_bios();
@@ -448,10 +448,10 @@ void neopcb_state::kf2k3pcb_sp1_decrypt()
/*********************************************** non-carts */
-WRITE16_MEMBER(neopcb_state::write_bankpvc)
+void neopcb_state::write_bankpvc(offs_t offset, uint16_t data, uint16_t mem_mask)
{
// write to cart ram
- m_pvc_prot->protection_w(space, offset, data, mem_mask);
+ m_pvc_prot->protection_w(offset, data, mem_mask);
// actual bankswitch
if (offset >= 0xff8)
@@ -469,7 +469,8 @@ void neopcb_state::install_common()
membank("cpu_bank")->set_base(m_region_maincpu->base() + 0x100000);
// install protection handlers + bankswitch handler
- m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x2fe000, 0x2fffff, read16_delegate(*m_pvc_prot, FUNC(pvc_prot_device::protection_r)), write16_delegate(*this, FUNC(neopcb_state::write_bankpvc)));
+ m_maincpu->space(AS_PROGRAM).install_read_handler(0x2fe000, 0x2fffff, read16sm_delegate(*m_pvc_prot, FUNC(pvc_prot_device::protection_r)));
+ m_maincpu->space(AS_PROGRAM).install_write_handler(0x2fe000, 0x2fffff, write16s_delegate(*this, FUNC(neopcb_state::write_bankpvc)));
// perform basic memory initialization that are usually done on-cart
m_curr_slot = 0;
diff --git a/src/mame/drivers/neoprint.cpp b/src/mame/drivers/neoprint.cpp
index 21e490bdd0d..b533ff0c0f2 100644
--- a/src/mame/drivers/neoprint.cpp
+++ b/src/mame/drivers/neoprint.cpp
@@ -69,17 +69,17 @@ protected:
virtual void video_start() override;
private:
- DECLARE_READ8_MEMBER(neoprint_calendar_r);
- DECLARE_WRITE8_MEMBER(neoprint_calendar_w);
- DECLARE_READ8_MEMBER(neoprint_unk_r);
- DECLARE_READ8_MEMBER(neoprint_audio_result_r);
- DECLARE_WRITE8_MEMBER(audio_cpu_clear_nmi_w);
- DECLARE_WRITE8_MEMBER(audio_command_w);
- DECLARE_READ8_MEMBER(audio_command_r);
- DECLARE_WRITE8_MEMBER(audio_result_w);
- DECLARE_WRITE16_MEMBER(nprsp_palette_w);
- DECLARE_WRITE8_MEMBER(nprsp_bank_w);
- DECLARE_READ16_MEMBER(rom_window_r);
+ uint8_t neoprint_calendar_r();
+ void neoprint_calendar_w(uint8_t data);
+ uint8_t neoprint_unk_r();
+ uint8_t neoprint_audio_result_r();
+ void audio_cpu_clear_nmi_w(uint8_t data);
+ void audio_command_w(offs_t offset, uint8_t data, uint8_t mem_mask = ~0);
+ uint8_t audio_command_r();
+ void audio_result_w(uint8_t data);
+ void nprsp_palette_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ void nprsp_bank_w(uint8_t data);
+ uint16_t rom_window_r(offs_t offset);
DECLARE_MACHINE_RESET(nprsp);
uint32_t screen_update_neoprint(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
uint32_t screen_update_nprsp(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
@@ -180,19 +180,19 @@ uint32_t neoprint_state::screen_update_nprsp(screen_device &screen, bitmap_ind16
}
-READ8_MEMBER(neoprint_state::neoprint_calendar_r)
+uint8_t neoprint_state::neoprint_calendar_r()
{
return (m_upd4990a->data_out_r() << 7) | (m_upd4990a->tp_r() << 6);
}
-WRITE8_MEMBER(neoprint_state::neoprint_calendar_w)
+void neoprint_state::neoprint_calendar_w(uint8_t data)
{
m_upd4990a->data_in_w(data >> 0 & 1);
m_upd4990a->clk_w(data >> 1 & 1);
m_upd4990a->stb_w(data >> 2 & 1);
}
-READ8_MEMBER(neoprint_state::neoprint_unk_r)
+uint8_t neoprint_state::neoprint_unk_r()
{
/* ---x ---- tested in irq routine, odd/even field number? */
/* ---- xx-- one of these two must be high */
@@ -206,7 +206,7 @@ READ8_MEMBER(neoprint_state::neoprint_unk_r)
return m_vblank| 4 | 3;
}
-READ8_MEMBER(neoprint_state::neoprint_audio_result_r)
+uint8_t neoprint_state::neoprint_audio_result_r()
{
return m_audio_result;
}
@@ -217,12 +217,12 @@ void neoprint_state::audio_cpu_assert_nmi()
}
-WRITE8_MEMBER(neoprint_state::audio_cpu_clear_nmi_w)
+void neoprint_state::audio_cpu_clear_nmi_w(uint8_t data)
{
m_audiocpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
}
-WRITE8_MEMBER(neoprint_state::audio_command_w)
+void neoprint_state::audio_command_w(offs_t offset, uint8_t data, uint8_t mem_mask)
{
m_soundlatch->write(data);
@@ -235,21 +235,21 @@ WRITE8_MEMBER(neoprint_state::audio_command_w)
}
-READ8_MEMBER(neoprint_state::audio_command_r)
+uint8_t neoprint_state::audio_command_r()
{
uint8_t ret = m_soundlatch->read();
//if (LOG_CPU_COMM) logerror(" AUD CPU PC %04x: audio_command_r %02x\n", m_audiocpu->pc(), ret);
/* this is a guess */
- audio_cpu_clear_nmi_w(space, 0, 0);
+ audio_cpu_clear_nmi_w(0);
return ret;
}
-WRITE8_MEMBER(neoprint_state::audio_result_w)
+void neoprint_state::audio_result_w(uint8_t data)
{
//if (LOG_CPU_COMM && (m_audio_result != data)) logerror(" AUD CPU PC %04x: audio_result_w %02x\n", m_audiocpu->pc(), data);
@@ -278,7 +278,7 @@ void neoprint_state::neoprint_map(address_map &map)
map(0x70001e, 0x70001f).nopw(); //watchdog
}
-WRITE16_MEMBER(neoprint_state::nprsp_palette_w)
+void neoprint_state::nprsp_palette_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
uint8_t r,g,b,i;
@@ -305,7 +305,7 @@ WRITE16_MEMBER(neoprint_state::nprsp_palette_w)
}
}
-WRITE8_MEMBER(neoprint_state::nprsp_bank_w)
+void neoprint_state::nprsp_bank_w(uint8_t data)
{
/* this register seems flip-flop based ... */
@@ -318,7 +318,7 @@ WRITE8_MEMBER(neoprint_state::nprsp_bank_w)
}
}
-READ16_MEMBER(neoprint_state::rom_window_r)
+uint16_t neoprint_state::rom_window_r(offs_t offset)
{
uint16_t *rom = (uint16_t *)memregion("maincpu")->base();
diff --git a/src/mame/drivers/neptunp2.cpp b/src/mame/drivers/neptunp2.cpp
index 441b800b386..7b2d8a8b53f 100644
--- a/src/mame/drivers/neptunp2.cpp
+++ b/src/mame/drivers/neptunp2.cpp
@@ -110,7 +110,7 @@ public:
void neptunp2(machine_config &config);
private:
- DECLARE_READ8_MEMBER(test_r);
+ uint8_t test_r();
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
@@ -134,7 +134,7 @@ uint32_t neptunp2_state::screen_update(screen_device &screen, bitmap_ind16 &bitm
return 0;
}
-READ8_MEMBER( neptunp2_state::test_r )
+uint8_t neptunp2_state::test_r()
{
return machine().rand();
}
diff --git a/src/mame/drivers/nexus3d.cpp b/src/mame/drivers/nexus3d.cpp
index 695c99a9a3e..a0bfc095328 100644
--- a/src/mame/drivers/nexus3d.cpp
+++ b/src/mame/drivers/nexus3d.cpp
@@ -51,10 +51,10 @@ private:
required_device<screen_device> m_screen;
required_device<palette_device> m_palette;
-// DECLARE_READ32_MEMBER(nexus3d_unk2_r);
-// DECLARE_READ32_MEMBER(nexus3d_unk3_r);
-// DECLARE_WRITE32_MEMBER(nexus3d_unk2_w);
-// DECLARE_WRITE32_MEMBER(nexus3d_unk3_w);
+// uint32_t nexus3d_unk2_r();
+// uint32_t nexus3d_unk3_r();
+// void nexus3d_unk2_w(uint32_t data);
+// void nexus3d_unk3_w(uint32_t data);
virtual void machine_start() override;
virtual void machine_reset() override;
@@ -64,22 +64,22 @@ private:
void nexus3d_map(address_map &map);
uint32_t m_intpend, m_intmask, m_intlevel;
- DECLARE_READ32_MEMBER(int_pending_r);
- DECLARE_WRITE32_MEMBER(int_ack_w);
- DECLARE_READ32_MEMBER(int_level_r);
- DECLARE_READ32_MEMBER(int_mask_r);
- DECLARE_WRITE32_MEMBER(int_mask_w);
+ uint32_t int_pending_r();
+ void int_ack_w(uint32_t data);
+ uint32_t int_level_r();
+ uint32_t int_mask_r();
+ void int_mask_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
void IntReq(int level);
- DECLARE_READ32_MEMBER(vrender3d_status_r);
- DECLARE_WRITE32_MEMBER(rop_data_w);
- DECLARE_WRITE16_MEMBER(rop_register_w);
- DECLARE_READ16_MEMBER(rop_status_r);
+ uint32_t vrender3d_status_r();
+ void rop_data_w(uint32_t data);
+ void rop_register_w(uint16_t data);
+ uint16_t rop_status_r();
- DECLARE_READ32_MEMBER(timer_status_r);
- DECLARE_WRITE32_MEMBER(timer_status_w);
- DECLARE_READ32_MEMBER(timer_count_r);
- DECLARE_WRITE32_MEMBER(timer_count_w);
+ uint32_t timer_status_r();
+ void timer_status_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t timer_count_r();
+ void timer_count_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t m_timer_status;
uint32_t m_timer_count;
emu_timer *m_timer;
@@ -87,7 +87,7 @@ private:
bool m_timer_irq;
bool m_timer_result;
- DECLARE_READ32_MEMBER(crtc_vblank_r);
+ uint32_t crtc_vblank_r();
};
void nexus3d_state::video_start()
@@ -109,7 +109,7 @@ uint32_t nexus3d_state::screen_update(screen_device &screen, bitmap_ind16 &bitma
return 0;
}
-READ32_MEMBER(nexus3d_state::vrender3d_status_r)
+uint32_t nexus3d_state::vrender3d_status_r()
{
return (0xbf<<16) | m_screen->vpos();
}
@@ -130,54 +130,54 @@ void nexus3d_state::IntReq(int level)
}
-READ32_MEMBER(nexus3d_state::int_mask_r)
+uint32_t nexus3d_state::int_mask_r()
{
return m_intmask;
}
-WRITE32_MEMBER(nexus3d_state::int_mask_w)
+void nexus3d_state::int_mask_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_intmask);
}
-READ32_MEMBER(nexus3d_state::int_pending_r)
+uint32_t nexus3d_state::int_pending_r()
{
return m_intpend;
}
-WRITE32_MEMBER(nexus3d_state::int_ack_w)
+void nexus3d_state::int_ack_w(uint32_t data)
{
m_intpend &= ~data;
IntReq(-1);
}
-READ32_MEMBER(nexus3d_state::int_level_r)
+uint32_t nexus3d_state::int_level_r()
{
return m_intlevel;
}
-WRITE16_MEMBER(nexus3d_state::rop_register_w)
+void nexus3d_state::rop_register_w(uint16_t data)
{
//printf("%04x REG\n",data);
}
-WRITE32_MEMBER(nexus3d_state::rop_data_w)
+void nexus3d_state::rop_data_w(uint32_t data)
{
//printf("%04x DATA\n",data);
}
-READ16_MEMBER(nexus3d_state::rop_status_r)
+uint16_t nexus3d_state::rop_status_r()
{
return machine().rand() & 0x1000;
}
-READ32_MEMBER(nexus3d_state::timer_status_r)
+uint32_t nexus3d_state::timer_status_r()
{
uint32_t res = (m_timer_status & ~0x30) | ((m_timer_irq == true) << 5) | ((m_timer_result == true) << 4);
return res;
}
-WRITE32_MEMBER(nexus3d_state::timer_status_w)
+void nexus3d_state::timer_status_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_timer_status);
//printf("%08x %08x\n",m_timer_status, m_timer_count);
@@ -194,12 +194,12 @@ WRITE32_MEMBER(nexus3d_state::timer_status_w)
}
}
-READ32_MEMBER(nexus3d_state::timer_count_r)
+uint32_t nexus3d_state::timer_count_r()
{
return m_timer_count;
}
-WRITE32_MEMBER(nexus3d_state::timer_count_w)
+void nexus3d_state::timer_count_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_timer_count);
}
@@ -219,7 +219,7 @@ TIMER_CALLBACK_MEMBER(nexus3d_state::timercb)
}
-READ32_MEMBER(nexus3d_state::crtc_vblank_r)
+uint32_t nexus3d_state::crtc_vblank_r()
{
uint16_t res = (m_screen->vblank()<<1) | (m_screen->hblank()<<0);
diff --git a/src/mame/drivers/ngen.cpp b/src/mame/drivers/ngen.cpp
index afc1d351559..9b4eec02b5f 100644
--- a/src/mame/drivers/ngen.cpp
+++ b/src/mame/drivers/ngen.cpp
@@ -158,23 +158,23 @@ private:
void cpu_peripheral_cb(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void peripheral_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t peripheral_r(offs_t offset, uint16_t mem_mask = ~0);
- DECLARE_WRITE16_MEMBER(xbus_w);
- DECLARE_READ16_MEMBER(xbus_r);
+ void xbus_w(uint16_t data);
+ uint16_t xbus_r();
DECLARE_WRITE_LINE_MEMBER(cpu_timer_w);
- DECLARE_WRITE16_MEMBER(hfd_w);
- DECLARE_READ16_MEMBER(hfd_r);
+ void hfd_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t hfd_r(offs_t offset, uint16_t mem_mask = ~0);
DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
- DECLARE_WRITE8_MEMBER(fdc_control_w);
+ void fdc_control_w(uint8_t data);
uint8_t irq_cb();
- DECLARE_WRITE8_MEMBER(hdc_control_w);
- DECLARE_WRITE8_MEMBER(disk_addr_ext);
+ void hdc_control_w(uint8_t data);
+ void disk_addr_ext(uint8_t data);
- DECLARE_READ16_MEMBER(b38_keyboard_r);
- DECLARE_WRITE16_MEMBER(b38_keyboard_w);
- DECLARE_READ16_MEMBER(b38_crtc_r);
- DECLARE_WRITE16_MEMBER(b38_crtc_w);
+ uint16_t b38_keyboard_r(offs_t offset, uint16_t mem_mask = ~0);
+ void b38_keyboard_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t b38_crtc_r(offs_t offset, uint16_t mem_mask = ~0);
+ void b38_crtc_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void ngen_io(address_map &map);
void ngen_mem(address_map &map);
@@ -437,7 +437,7 @@ uint16_t ngen_state::peripheral_r(offs_t offset, uint16_t mem_mask)
// expansion module. The base I/O address for the currently selected module is set by writing to
// this register (bits 0-7 are ignored)
// TODO: make expansion modules slot devices
-WRITE16_MEMBER(ngen_state::xbus_w)
+void ngen_state::xbus_w(uint16_t data)
{
uint16_t addr = (data & 0x00ff) << 8;
cpu_device* cpu;
@@ -450,7 +450,7 @@ WRITE16_MEMBER(ngen_state::xbus_w)
switch(m_xbus_current)
{
case 0x00: // Floppy/Hard disk module
- io.install_readwrite_handler(addr,addr+0xff, read16_delegate(*this, FUNC(ngen_state::hfd_r)), write16_delegate(*this, FUNC(ngen_state::hfd_w)), 0xffffffff);
+ io.install_readwrite_handler(addr,addr+0xff, read16s_delegate(*this, FUNC(ngen_state::hfd_r)), write16s_delegate(*this, FUNC(ngen_state::hfd_w)), 0xffffffff);
break;
default:
cpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero); // reached end of the modules
@@ -466,7 +466,7 @@ WRITE16_MEMBER(ngen_state::xbus_w)
// Known module IDs:
// 0x1070 - Floppy/Hard disk module
// 0x3141 - QIC Tape module
-READ16_MEMBER(ngen_state::xbus_r)
+uint16_t ngen_state::xbus_r()
{
uint16_t ret = 0xffff;
@@ -488,7 +488,7 @@ READ16_MEMBER(ngen_state::xbus_r)
// Floppy/Hard disk module
-WRITE16_MEMBER(ngen_state::hfd_w)
+void ngen_state::hfd_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset)
{
@@ -508,15 +508,15 @@ WRITE16_MEMBER(ngen_state::hfd_w)
break;
case 0x04:
if(ACCESSING_BITS_0_7)
- fdc_control_w(space,0,data & 0xff);
+ fdc_control_w(data & 0xff);
break;
case 0x05:
if(ACCESSING_BITS_0_7)
- hdc_control_w(space,0,data & 0xff);
+ hdc_control_w(data & 0xff);
break;
case 0x07:
if(ACCESSING_BITS_0_7)
- disk_addr_ext(space,0,data & 0xff);
+ disk_addr_ext(data & 0xff);
break;
case 0x08:
case 0x09:
@@ -547,7 +547,7 @@ WRITE16_MEMBER(ngen_state::hfd_w)
}
}
-READ16_MEMBER(ngen_state::hfd_r)
+uint16_t ngen_state::hfd_r(offs_t offset, uint16_t mem_mask)
{
uint16_t ret = 0xffff;
@@ -614,7 +614,7 @@ WRITE_LINE_MEMBER(ngen_state::fdc_drq_w)
// Bit 5 - side select
// Bit 6 - 1 = 2Mhz for seek, 0 = 1MHz for read/write
// Bit 7 - FDC reset
-WRITE8_MEMBER(ngen_state::fdc_control_w)
+void ngen_state::fdc_control_w(uint8_t data)
{
m_fdc->set_floppy(m_fd0->get_device());
m_fd0->get_device()->mon_w(!BIT(data, 2));
@@ -629,7 +629,7 @@ WRITE8_MEMBER(ngen_state::fdc_control_w)
// bits 3-5 - select head / expansion module head
// bit 6 - write enable, must be set to write to a hard disk
// bit 7 - HDC reset
-WRITE8_MEMBER(ngen_state::hdc_control_w)
+void ngen_state::hdc_control_w(uint8_t data)
{
m_hdc_control = data;
if(m_hdc_control & 0x04)
@@ -643,7 +643,7 @@ WRITE8_MEMBER(ngen_state::hdc_control_w)
// page of system RAM to access
// bit 7 = disables read/write signals to the WD1010
-WRITE8_MEMBER(ngen_state::disk_addr_ext)
+void ngen_state::disk_addr_ext(uint8_t data)
{
m_disk_page = data & 0x7f;
}
@@ -779,7 +779,7 @@ uint8_t ngen_state::irq_cb()
return m_pic->acknowledge();
}
-READ16_MEMBER( ngen_state::b38_keyboard_r )
+uint16_t ngen_state::b38_keyboard_r(offs_t offset, uint16_t mem_mask)
{
uint8_t ret = 0;
switch(offset)
@@ -794,7 +794,7 @@ READ16_MEMBER( ngen_state::b38_keyboard_r )
return ret;
}
-WRITE16_MEMBER( ngen_state::b38_keyboard_w )
+void ngen_state::b38_keyboard_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset)
{
@@ -806,7 +806,7 @@ WRITE16_MEMBER( ngen_state::b38_keyboard_w )
}
}
-READ16_MEMBER( ngen_state::b38_crtc_r )
+uint16_t ngen_state::b38_crtc_r(offs_t offset, uint16_t mem_mask)
{
uint8_t ret = 0;
switch(offset)
@@ -823,7 +823,7 @@ READ16_MEMBER( ngen_state::b38_crtc_r )
return ret;
}
-WRITE16_MEMBER( ngen_state::b38_crtc_w )
+void ngen_state::b38_crtc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset)
{
diff --git a/src/mame/drivers/nibble.cpp b/src/mame/drivers/nibble.cpp
index dfe35d1767b..a5ce4775c2a 100644
--- a/src/mame/drivers/nibble.cpp
+++ b/src/mame/drivers/nibble.cpp
@@ -83,7 +83,7 @@ private:
required_device<cpu_device> m_maincpu;
required_device<gfxdecode_device> m_gfxdecode;
- DECLARE_WRITE8_MEMBER(nibble_videoram_w);
+ void nibble_videoram_w(offs_t offset, uint8_t data, uint8_t mem_mask = ~0);
TILE_GET_INFO_MEMBER(get_bg_tile_info);
void nibble_palette(palette_device &palette) const;
@@ -100,7 +100,7 @@ private:
* Video Hardware *
*************************/
-WRITE8_MEMBER(nibble_state::nibble_videoram_w)
+void nibble_state::nibble_videoram_w(offs_t offset, uint8_t data, uint8_t mem_mask)
{
COMBINE_DATA(m_videoram+offset);
m_bg_tilemap->mark_tile_dirty(offset*2);
diff --git a/src/mame/drivers/nightgal.cpp b/src/mame/drivers/nightgal.cpp
index b26bc66eb9f..99b2428e3f1 100644
--- a/src/mame/drivers/nightgal.cpp
+++ b/src/mame/drivers/nightgal.cpp
@@ -94,24 +94,24 @@ private:
optional_device<cpu_device> m_audiocpu;
/* memory */
- //DECLARE_WRITE8_MEMBER(sexygal_nsc_true_blitter_w);
- DECLARE_WRITE8_MEMBER(royalqn_blitter_0_w);
- DECLARE_WRITE8_MEMBER(royalqn_blitter_1_w);
- DECLARE_WRITE8_MEMBER(royalqn_blitter_2_w);
- DECLARE_READ8_MEMBER(royalqn_nsc_blit_r);
- DECLARE_READ8_MEMBER(royalqn_comm_r);
- DECLARE_WRITE8_MEMBER(royalqn_comm_w);
- DECLARE_WRITE8_MEMBER(mux_w);
+ //void sexygal_nsc_true_blitter_w(uint8_t data);
+ void royalqn_blitter_0_w(uint8_t data);
+ void royalqn_blitter_1_w(uint8_t data);
+ void royalqn_blitter_2_w(uint8_t data);
+ uint8_t royalqn_nsc_blit_r(offs_t offset);
+ uint8_t royalqn_comm_r(offs_t offset);
+ void royalqn_comm_w(offs_t offset, uint8_t data);
+ void mux_w(uint8_t data);
uint8_t input_1p_r();
uint8_t input_2p_r();
- DECLARE_WRITE8_MEMBER(output_w);
- DECLARE_READ8_MEMBER(sexygal_soundram_r);
- DECLARE_READ8_MEMBER(sexygal_unknown_sound_r);
- DECLARE_WRITE8_MEMBER(sexygal_audioff_w);
- DECLARE_WRITE8_MEMBER(sexygal_audionmi_w);
-
- DECLARE_WRITE8_MEMBER(ngalsumr_prot_latch_w);
- DECLARE_READ8_MEMBER(ngalsumr_prot_value_r);
+ void output_w(uint8_t data);
+ uint8_t sexygal_soundram_r(offs_t offset);
+ uint8_t sexygal_unknown_sound_r();
+ void sexygal_audioff_w(uint8_t data);
+ void sexygal_audionmi_w(uint8_t data);
+
+ void ngalsumr_prot_latch_w(uint8_t data);
+ uint8_t ngalsumr_prot_value_r();
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;
@@ -243,23 +243,23 @@ void nightgal_state::nightgal_palette(palette_device &palette) const
There are three unidirectional latches that also sends an irq from z80 to MCU.
*/
// TODO: simplify this (error in the document)
-WRITE8_MEMBER(nightgal_state::royalqn_blitter_0_w)
+void nightgal_state::royalqn_blitter_0_w(uint8_t data)
{
m_blit_raw_data[0] = data;
}
-WRITE8_MEMBER(nightgal_state::royalqn_blitter_1_w)
+void nightgal_state::royalqn_blitter_1_w(uint8_t data)
{
m_blit_raw_data[1] = data;
}
-WRITE8_MEMBER(nightgal_state::royalqn_blitter_2_w)
+void nightgal_state::royalqn_blitter_2_w(uint8_t data)
{
m_blit_raw_data[2] = data;
m_subcpu->set_input_line(0, ASSERT_LINE );
}
-READ8_MEMBER(nightgal_state::royalqn_nsc_blit_r)
+uint8_t nightgal_state::royalqn_nsc_blit_r(offs_t offset)
{
if(offset == 2)
m_subcpu->set_input_line(0, CLEAR_LINE );
@@ -281,7 +281,7 @@ void nightgal_state::z80_wait_assert_cb()
m_z80_wait_ack_timer->adjust(m_maincpu->cycles_to_attotime(4));
}
-READ8_MEMBER(nightgal_state::royalqn_comm_r)
+uint8_t nightgal_state::royalqn_comm_r(offs_t offset)
{
z80_wait_assert_cb();
machine().scheduler().synchronize(); // force resync
@@ -289,7 +289,7 @@ READ8_MEMBER(nightgal_state::royalqn_comm_r)
return (m_comms_ram[offset] & 0x80) | (0x7f); //bits 6-0 are undefined, presumably open bus
}
-WRITE8_MEMBER(nightgal_state::royalqn_comm_w)
+void nightgal_state::royalqn_comm_w(offs_t offset, uint8_t data)
{
z80_wait_assert_cb();
machine().scheduler().synchronize(); // force resync
@@ -303,7 +303,7 @@ WRITE8_MEMBER(nightgal_state::royalqn_comm_w)
*
********************************************/
-WRITE8_MEMBER(nightgal_state::mux_w)
+void nightgal_state::mux_w(uint8_t data)
{
m_mux_data = ~data;
//printf("%02x\n", m_mux_data);
@@ -347,7 +347,7 @@ uint8_t nightgal_state::input_2p_r()
m_io_pl2_4->read() & m_io_pl2_5->read() & m_io_pl2_6->read()) | coin_port;
}
-WRITE8_MEMBER(nightgal_state::output_w)
+void nightgal_state::output_w(uint8_t data)
{
/*
Doesn't match Charles notes?
@@ -384,20 +384,20 @@ void nightgal_state::common_nsc_map(address_map &map)
* Sexy Gal
********************************/
-READ8_MEMBER(nightgal_state::sexygal_soundram_r)
+uint8_t nightgal_state::sexygal_soundram_r(offs_t offset)
{
// bit 7 set = contention?
return BIT(m_sound_ram[offset], 7) ? 0x00 : 0x40;
}
-READ8_MEMBER(nightgal_state::sexygal_unknown_sound_r)
+uint8_t nightgal_state::sexygal_unknown_sound_r()
{
// value read here stored in (1-bit) shared RAM but not used?
return 0;
}
// flip flop from main to audio CPU
-WRITE8_MEMBER(nightgal_state::sexygal_audioff_w)
+void nightgal_state::sexygal_audioff_w(uint8_t data)
{
// causes an irq
m_audiocpu->set_input_line(0, BIT(data, 6) ? ASSERT_LINE : CLEAR_LINE);
@@ -408,7 +408,7 @@ WRITE8_MEMBER(nightgal_state::sexygal_audioff_w)
m_sexygal_audioff = data;
}
-WRITE8_MEMBER(nightgal_state::sexygal_audionmi_w)
+void nightgal_state::sexygal_audionmi_w(uint8_t data)
{
m_maincpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
@@ -1271,12 +1271,12 @@ void nightgal_state::init_royalqn()
}
// Night Gal Summer uses a protection latch device to get some layer clearances width/height values.
-WRITE8_MEMBER(nightgal_state::ngalsumr_prot_latch_w)
+void nightgal_state::ngalsumr_prot_latch_w(uint8_t data)
{
m_z80_latch = data;
}
-READ8_MEMBER(nightgal_state::ngalsumr_prot_value_r)
+uint8_t nightgal_state::ngalsumr_prot_value_r()
{
switch(m_z80_latch)
{
@@ -1323,8 +1323,8 @@ READ8_MEMBER(nightgal_state::ngalsumr_prot_value_r)
void nightgal_state::init_ngalsumr()
{
- m_maincpu->space(AS_PROGRAM).install_write_handler(0x6000, 0x6000, write8_delegate(*this, FUNC(nightgal_state::ngalsumr_prot_latch_w)));
- m_maincpu->space(AS_PROGRAM).install_read_handler(0x6001, 0x6001, read8_delegate(*this, FUNC(nightgal_state::ngalsumr_prot_value_r)));
+ m_maincpu->space(AS_PROGRAM).install_write_handler(0x6000, 0x6000, write8smo_delegate(*this, FUNC(nightgal_state::ngalsumr_prot_latch_w)));
+ m_maincpu->space(AS_PROGRAM).install_read_handler(0x6001, 0x6001, read8smo_delegate(*this, FUNC(nightgal_state::ngalsumr_prot_value_r)));
// 0x6003 some kind of f/f state
}
diff --git a/src/mame/drivers/nightmare.cpp b/src/mame/drivers/nightmare.cpp
index 8993b05edb7..5ea1c4ac209 100644
--- a/src/mame/drivers/nightmare.cpp
+++ b/src/mame/drivers/nightmare.cpp
@@ -241,7 +241,7 @@ protected:
DECLARE_READ_LINE_MEMBER( ef2_r );
DECLARE_WRITE_LINE_MEMBER( q_w );
void ic10_w(uint8_t data);
- DECLARE_WRITE8_MEMBER( unkout_w );
+ void unkout_w(uint8_t data);
void nightmare_map(address_map &map);
void nightmare_io_map(address_map &map);
@@ -334,7 +334,7 @@ void nightmare_state::ic10_w(uint8_t data)
}
-WRITE8_MEMBER( nightmare_state::unkout_w )
+void nightmare_state::unkout_w(uint8_t data)
{
// J3
}
diff --git a/src/mame/drivers/nmg5.cpp b/src/mame/drivers/nmg5.cpp
index a8eed2679c1..a657a5641b8 100644
--- a/src/mame/drivers/nmg5.cpp
+++ b/src/mame/drivers/nmg5.cpp
@@ -290,15 +290,15 @@ private:
optional_device<decospr_device> m_sprgen;
required_device<generic_latch_8_device> m_soundlatch;
- DECLARE_READ8_MEMBER(pixmap_r);
- DECLARE_WRITE8_MEMBER(pixmap_w);
- template<int Layer> DECLARE_WRITE16_MEMBER(vram_w);
- DECLARE_WRITE8_MEMBER(soundlatch_w);
- DECLARE_READ16_MEMBER(prot_r);
- DECLARE_WRITE16_MEMBER(prot_w);
- DECLARE_WRITE16_MEMBER(gfx_bank_w);
- DECLARE_WRITE16_MEMBER(priority_reg_w);
- DECLARE_WRITE8_MEMBER(oki_banking_w);
+ uint8_t pixmap_r(offs_t offset);
+ void pixmap_w(offs_t offset, uint8_t data);
+ template<int Layer> void vram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ void soundlatch_w(uint8_t data);
+ uint16_t prot_r();
+ void prot_w(uint16_t data);
+ void gfx_bank_w(uint16_t data);
+ void priority_reg_w(uint16_t data);
+ void oki_banking_w(uint8_t data);
template<int Layer> TILE_GET_INFO_MEMBER(get_tile_info);
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
void nmg5_map(address_map &map);
@@ -310,7 +310,7 @@ private:
-READ8_MEMBER(nmg5_state::pixmap_r)
+uint8_t nmg5_state::pixmap_r(offs_t offset)
{
int const sy = offset >> 8;
int const sx = (offset & 0xff) << 1;
@@ -318,7 +318,7 @@ READ8_MEMBER(nmg5_state::pixmap_r)
return ((m_pixmap->pix16(sy & 0xff, sx & ~1) & 0xf) << 4) | (m_pixmap->pix16(sy & 0xff, sx | 1) & 0xf);
}
-WRITE8_MEMBER(nmg5_state::pixmap_w)
+void nmg5_state::pixmap_w(offs_t offset, uint8_t data)
{
int const sy = offset >> 8;
int const sx = (offset & 0xff) << 1;
@@ -328,29 +328,29 @@ WRITE8_MEMBER(nmg5_state::pixmap_w)
}
template<int Layer>
-WRITE16_MEMBER(nmg5_state::vram_w)
+void nmg5_state::vram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_vram[Layer][offset]);
m_tilemap[Layer]->mark_tile_dirty(offset);
}
-WRITE8_MEMBER(nmg5_state::soundlatch_w)
+void nmg5_state::soundlatch_w(uint8_t data)
{
m_soundlatch->write(data);
m_soundcpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
}
-READ16_MEMBER(nmg5_state::prot_r)
+uint16_t nmg5_state::prot_r()
{
return m_prot_val | m_input_data;
}
-WRITE16_MEMBER(nmg5_state::prot_w)
+void nmg5_state::prot_w(uint16_t data)
{
m_input_data = data & 0x0f;
}
-WRITE16_MEMBER(nmg5_state::gfx_bank_w)
+void nmg5_state::gfx_bank_w(uint16_t data)
{
if (m_gfx_bank != (data & 3))
{
@@ -359,7 +359,7 @@ WRITE16_MEMBER(nmg5_state::gfx_bank_w)
}
}
-WRITE16_MEMBER(nmg5_state::priority_reg_w)
+void nmg5_state::priority_reg_w(uint16_t data)
{
m_priority_reg = data & 7;
@@ -367,7 +367,7 @@ WRITE16_MEMBER(nmg5_state::priority_reg_w)
popmessage("unknown priority_reg value = %d\n", m_priority_reg);
}
-WRITE8_MEMBER(nmg5_state::oki_banking_w)
+void nmg5_state::oki_banking_w(uint8_t data)
{
m_oki->set_rom_bank(data & 1);
}
diff --git a/src/mame/drivers/nokia_3310.cpp b/src/mame/drivers/nokia_3310.cpp
index 55820d40b73..352513d8cc2 100644
--- a/src/mame/drivers/nokia_3310.cpp
+++ b/src/mame/drivers/nokia_3310.cpp
@@ -52,22 +52,22 @@ private:
PCD8544_SCREEN_UPDATE(pcd8544_screen_update);
- DECLARE_READ8_MEMBER(mad2_io_r);
- DECLARE_WRITE8_MEMBER(mad2_io_w);
- DECLARE_READ8_MEMBER(mad2_dspif_r);
- DECLARE_WRITE8_MEMBER(mad2_dspif_w);
- DECLARE_READ8_MEMBER(mad2_mcuif_r);
- DECLARE_WRITE8_MEMBER(mad2_mcuif_w);
+ uint8_t mad2_io_r(offs_t offset);
+ void mad2_io_w(offs_t offset, uint8_t data);
+ uint8_t mad2_dspif_r(offs_t offset);
+ void mad2_dspif_w(offs_t offset, uint8_t data);
+ uint8_t mad2_mcuif_r(offs_t offset);
+ void mad2_mcuif_w(offs_t offset, uint8_t data);
TIMER_CALLBACK_MEMBER(timer0);
TIMER_CALLBACK_MEMBER(timer1);
TIMER_CALLBACK_MEMBER(timer_watchdog);
TIMER_CALLBACK_MEMBER(timer_fiq8);
- DECLARE_READ16_MEMBER(ram_r) { return m_ram[offset] & mem_mask; }
- DECLARE_WRITE16_MEMBER(ram_w) { COMBINE_DATA(&m_ram[offset]); }
- DECLARE_READ16_MEMBER(dsp_ram_r);
- DECLARE_WRITE16_MEMBER(dsp_ram_w);
+ uint16_t ram_r(offs_t offset, uint16_t mem_mask = ~0) { return m_ram[offset] & mem_mask; }
+ void ram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0) { COMBINE_DATA(&m_ram[offset]); }
+ uint16_t dsp_ram_r(offs_t offset);
+ void dsp_ram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void noki3310_map(address_map &map);
@@ -479,7 +479,7 @@ TIMER_CALLBACK_MEMBER(noki3310_state::timer_watchdog)
}
}
-READ16_MEMBER(noki3310_state::dsp_ram_r)
+uint16_t noki3310_state::dsp_ram_r(offs_t offset)
{
// HACK: avoid hangs when ARM try to communicate with the DSP
if (offset <= 0x004 >> 1) return 0x01;
@@ -490,12 +490,12 @@ READ16_MEMBER(noki3310_state::dsp_ram_r)
return m_dsp_ram[offset & 0x7ff];
}
-WRITE16_MEMBER(noki3310_state::dsp_ram_w)
+void noki3310_state::dsp_ram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_dsp_ram[offset & 0x7ff]);
}
-READ8_MEMBER(noki3310_state::mad2_io_r)
+uint8_t noki3310_state::mad2_io_r(offs_t offset)
{
uint8_t data = m_mad2_regs[offset];
@@ -559,7 +559,7 @@ READ8_MEMBER(noki3310_state::mad2_io_r)
return data;
}
-WRITE8_MEMBER(noki3310_state::mad2_io_w)
+void noki3310_state::mad2_io_w(offs_t offset, uint8_t data)
{
m_mad2_regs[offset] = data;
@@ -605,7 +605,7 @@ WRITE8_MEMBER(noki3310_state::mad2_io_w)
#endif
}
-READ8_MEMBER(noki3310_state::mad2_dspif_r)
+uint8_t noki3310_state::mad2_dspif_r(offs_t offset)
{
#if LOG_MAD2_REGISTER_ACCESS
logerror("MAD2 R %02x DSPIF\n", offset);
@@ -613,14 +613,14 @@ READ8_MEMBER(noki3310_state::mad2_dspif_r)
return 0;
}
-WRITE8_MEMBER(noki3310_state::mad2_dspif_w)
+void noki3310_state::mad2_dspif_w(offs_t offset, uint8_t data)
{
#if LOG_MAD2_REGISTER_ACCESS
logerror("MAD2 W %02x = %02x DSPIF\n", offset, data);
#endif
}
-READ8_MEMBER(noki3310_state::mad2_mcuif_r)
+uint8_t noki3310_state::mad2_mcuif_r(offs_t offset)
{
#if LOG_MAD2_REGISTER_ACCESS
logerror("MAD2 R %02x MCUIF\n", offset);
@@ -628,7 +628,7 @@ READ8_MEMBER(noki3310_state::mad2_mcuif_r)
return 0;
}
-WRITE8_MEMBER(noki3310_state::mad2_mcuif_w)
+void noki3310_state::mad2_mcuif_w(offs_t offset, uint8_t data)
{
#if LOG_MAD2_REGISTER_ACCESS
logerror("MAD2 W %02x = %02x MCUIF\n", offset, data);
diff --git a/src/mame/drivers/notechan.cpp b/src/mame/drivers/notechan.cpp
index e70841aa0d0..099bed1cc41 100644
--- a/src/mame/drivers/notechan.cpp
+++ b/src/mame/drivers/notechan.cpp
@@ -312,10 +312,10 @@ public:
void notechan(machine_config &config);
private:
- DECLARE_WRITE8_MEMBER(out_f8_w);
- DECLARE_WRITE8_MEMBER(out_f9_w);
- DECLARE_WRITE8_MEMBER(out_fa_w);
- DECLARE_WRITE8_MEMBER(out_ff_w);
+ void out_f8_w(uint8_t data);
+ void out_f9_w(uint8_t data);
+ void out_fa_w(uint8_t data);
+ void out_ff_w(uint8_t data);
void notechan_map(address_map &map);
void notechan_port_map(address_map &map);
@@ -353,7 +353,7 @@ void notechan_state::notechan_port_map(address_map &map)
* Output Ports / Lamps *
*********************************************/
-WRITE8_MEMBER(notechan_state::out_f8_w)
+void notechan_state::out_f8_w(uint8_t data)
{
m_lamps[0] = BIT(data, 0);
m_lamps[1] = BIT(data, 1);
@@ -367,7 +367,7 @@ WRITE8_MEMBER(notechan_state::out_f8_w)
logerror("Output %02X to $F8\n", data);
}
-WRITE8_MEMBER(notechan_state::out_f9_w)
+void notechan_state::out_f9_w(uint8_t data)
{
m_lamps[8] = BIT(data, 0);
m_lamps[9] = BIT(data, 1);
@@ -381,7 +381,7 @@ WRITE8_MEMBER(notechan_state::out_f9_w)
logerror("Output %02X to $F9\n", data);
}
-WRITE8_MEMBER(notechan_state::out_fa_w)
+void notechan_state::out_fa_w(uint8_t data)
{
m_oki->set_rom_bank(BIT(data, 5));
@@ -397,7 +397,7 @@ WRITE8_MEMBER(notechan_state::out_fa_w)
logerror("Output %02X to $FA\n", data);
}
-WRITE8_MEMBER(notechan_state::out_ff_w)
+void notechan_state::out_ff_w(uint8_t data)
{
m_lamps[24] = BIT(data, 0);
m_lamps[25] = BIT(data, 1);
diff --git a/src/mame/drivers/notetaker.cpp b/src/mame/drivers/notetaker.cpp
index f7baa3bfd9d..89b2ed4e811 100644
--- a/src/mame/drivers/notetaker.cpp
+++ b/src/mame/drivers/notetaker.cpp
@@ -164,24 +164,24 @@ private:
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
// basic io
void IPConReg_w(uint16_t data);
- DECLARE_WRITE16_MEMBER(EPConReg_w);
+ void EPConReg_w(uint16_t data);
void FIFOReg_w(uint16_t data);
- DECLARE_WRITE16_MEMBER(FIFOBus_w);
+ void FIFOBus_w(uint16_t data);
void DiskReg_w(uint16_t data);
- DECLARE_WRITE16_MEMBER(LoadDispAddr_w);
+ void LoadDispAddr_w(uint16_t data);
// uarts
- DECLARE_READ16_MEMBER(ReadOPStatus_r);
- DECLARE_WRITE16_MEMBER(LoadKeyCtlReg_w);
- DECLARE_WRITE16_MEMBER(KeyDataReset_w);
- DECLARE_WRITE16_MEMBER(KeyChipReset_w);
- DECLARE_READ16_MEMBER(ReadEIAStatus_r);
- DECLARE_WRITE16_MEMBER(LoadEIACtlReg_w);
- DECLARE_WRITE16_MEMBER(EIADataReset_w);
- DECLARE_WRITE16_MEMBER(EIAChipReset_w);
+ uint16_t ReadOPStatus_r();
+ void LoadKeyCtlReg_w(uint16_t data);
+ void KeyDataReset_w(uint16_t data);
+ void KeyChipReset_w(uint16_t data);
+ uint16_t ReadEIAStatus_r();
+ void LoadEIACtlReg_w(uint16_t data);
+ void EIADataReset_w(uint16_t data);
+ void EIAChipReset_w(uint16_t data);
// mem map stuff
- DECLARE_READ16_MEMBER(iop_r);
- DECLARE_WRITE16_MEMBER(iop_w);
+ uint16_t iop_r(offs_t offset);
+ void iop_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t ep_mainram_r(offs_t offset, uint16_t mem_mask);
void ep_mainram_w(offs_t offset, uint16_t data, uint16_t mem_mask);
//variables
@@ -325,7 +325,7 @@ void notetaker_state::IPConReg_w(uint16_t data)
/* handlers for the two system hd6402s (ay-5-1013 equivalent) */
/* * Keyboard hd6402 */
-READ16_MEMBER( notetaker_state::ReadOPStatus_r ) // 74ls368 hex inverter at #l7 provides 4 bits, inverted
+uint16_t notetaker_state::ReadOPStatus_r() // 74ls368 hex inverter at #l7 provides 4 bits, inverted
{
uint16_t data = 0xFFF0;
data |= (m_outfifo_count >= 1) ? 0 : 0x08; // m_FIFOOutRdy is true if the fifo has at least 1 word in it, false otherwise
@@ -339,7 +339,7 @@ READ16_MEMBER( notetaker_state::ReadOPStatus_r ) // 74ls368 hex inverter at #l7
return data;
}
-WRITE16_MEMBER( notetaker_state::LoadKeyCtlReg_w )
+void notetaker_state::LoadKeyCtlReg_w(uint16_t data)
{
m_kbduart->write_cs(0);
m_kbduart->write_np(BIT(data, 4)); // PI - pin 35
@@ -350,13 +350,13 @@ WRITE16_MEMBER( notetaker_state::LoadKeyCtlReg_w )
m_kbduart->write_cs(1);
}
-WRITE16_MEMBER( notetaker_state::KeyDataReset_w )
+void notetaker_state::KeyDataReset_w(uint16_t data)
{
m_kbduart->write_rdav(0); // DDR - pin 18
m_kbduart->write_rdav(1); // ''
}
-WRITE16_MEMBER( notetaker_state::KeyChipReset_w )
+void notetaker_state::KeyChipReset_w(uint16_t data)
{
m_kbduart->write_xr(0); // MR - pin 21
m_kbduart->write_xr(1); // ''
@@ -382,7 +382,7 @@ void notetaker_state::FIFOReg_w(uint16_t data)
logerror("Write to 0x60 FIFOReg_w of %04x; fifo timer set to %d hz\n", data, ((((960'000)/10)/4)/((m_FrSel0<<3)+(m_FrSel1<<2)+(m_FrSel2<<1)+1)));
}
-WRITE16_MEMBER(notetaker_state::FIFOBus_w)
+void notetaker_state::FIFOBus_w(uint16_t data)
{
if (m_outfifo_count == 16)
{
@@ -451,14 +451,14 @@ void notetaker_state::DiskReg_w(uint16_t data)
//TODO
}
-WRITE16_MEMBER( notetaker_state::LoadDispAddr_w )
+void notetaker_state::LoadDispAddr_w(uint16_t data)
{
m_DispAddr = data;
// for future low level emulation: clear the current counter position here as well, as well as empty/reset the display fifo, and the setmemrq state.
}
/* EIA hd6402 */
-READ16_MEMBER( notetaker_state::ReadEIAStatus_r ) // 74ls368 hex inverter at #f1 provides 2 bits, inverted
+uint16_t notetaker_state::ReadEIAStatus_r() // 74ls368 hex inverter at #f1 provides 2 bits, inverted
{
uint16_t data = 0xFFFC;
// note /SWE is permanently enabled, so we don't enable it here for HD6402 reading
@@ -467,7 +467,7 @@ READ16_MEMBER( notetaker_state::ReadEIAStatus_r ) // 74ls368 hex inverter at #f1
return data;
}
-WRITE16_MEMBER( notetaker_state::LoadEIACtlReg_w )
+void notetaker_state::LoadEIACtlReg_w(uint16_t data)
{
m_eiauart->write_cs(0);
m_eiauart->write_np(BIT(data, 4)); // PI - pin 35
@@ -478,13 +478,13 @@ WRITE16_MEMBER( notetaker_state::LoadEIACtlReg_w )
m_eiauart->write_cs(1);
}
-WRITE16_MEMBER( notetaker_state::EIADataReset_w )
+void notetaker_state::EIADataReset_w(uint16_t data)
{
m_eiauart->write_rdav(0); // DDR - pin 18
m_eiauart->write_rdav(1); // ''
}
-WRITE16_MEMBER( notetaker_state::EIAChipReset_w )
+void notetaker_state::EIAChipReset_w(uint16_t data)
{
m_eiauart->write_xr(0); // MR - pin 21
m_eiauart->write_xr(1); // ''
@@ -492,7 +492,7 @@ WRITE16_MEMBER( notetaker_state::EIAChipReset_w )
/* These next two members are memory map related for the iop */
-READ16_MEMBER(notetaker_state::iop_r)
+uint16_t notetaker_state::iop_r(offs_t offset)
{
uint16_t *rom = (uint16_t *)(memregion("iop")->base());
rom += 0x7f800;
@@ -511,7 +511,7 @@ READ16_MEMBER(notetaker_state::iop_r)
}
}
-WRITE16_MEMBER(notetaker_state::iop_w)
+void notetaker_state::iop_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
//uint16_t tempword;
uint16_t *ram = m_mainram.get();
@@ -680,7 +680,7 @@ read from 0x44 (byte wide) to check input fifo status
/* Emulator CPU */
-WRITE16_MEMBER(notetaker_state::EPConReg_w)
+void notetaker_state::EPConReg_w(uint16_t data)
{
/*m_EP_LED1 = m_EP_ParityError; // if parity checking is enabled AND the last access was to the low 8k AND there was a parity error, the parity error latch is latched here. It triggers an interrupt.
m_EP_LED2 = (data&0x40)?1:0;
diff --git a/src/mame/drivers/novag_cforte.cpp b/src/mame/drivers/novag_cforte.cpp
index c4f8885e652..5f5aa1465d2 100644
--- a/src/mame/drivers/novag_cforte.cpp
+++ b/src/mame/drivers/novag_cforte.cpp
@@ -76,10 +76,10 @@ private:
// I/O handlers
void update_display();
void lcd_output_w(u64 data);
- DECLARE_WRITE8_MEMBER(mux_w);
- DECLARE_WRITE8_MEMBER(control_w);
- DECLARE_READ8_MEMBER(input1_r);
- DECLARE_READ8_MEMBER(input2_r);
+ void mux_w(u8 data);
+ void control_w(u8 data);
+ u8 input1_r();
+ u8 input2_r();
u8 m_inp_mux;
u8 m_led_select;
@@ -134,14 +134,14 @@ void cforte_state::update_display()
m_display->matrix_partial(0, 3, m_led_select, m_inp_mux);
}
-WRITE8_MEMBER(cforte_state::mux_w)
+void cforte_state::mux_w(u8 data)
{
// d0-d7: input mux, led data
m_inp_mux = data;
update_display();
}
-WRITE8_MEMBER(cforte_state::control_w)
+void cforte_state::control_w(u8 data)
{
// d0: HLCD0538 data in
// d1: HLCD0538 clk
@@ -160,7 +160,7 @@ WRITE8_MEMBER(cforte_state::control_w)
m_beeper->set_state(data >> 7 & 1);
}
-READ8_MEMBER(cforte_state::input1_r)
+u8 cforte_state::input1_r()
{
u8 data = 0;
@@ -172,7 +172,7 @@ READ8_MEMBER(cforte_state::input1_r)
return ~data;
}
-READ8_MEMBER(cforte_state::input2_r)
+u8 cforte_state::input2_r()
{
u8 data = 0;
diff --git a/src/mame/drivers/novag_const.cpp b/src/mame/drivers/novag_const.cpp
index c8d8a667d75..b08053c59c6 100644
--- a/src/mame/drivers/novag_const.cpp
+++ b/src/mame/drivers/novag_const.cpp
@@ -126,10 +126,10 @@ private:
// I/O handlers
void update_display();
- DECLARE_WRITE8_MEMBER(mux_w);
- DECLARE_WRITE8_MEMBER(control_w);
- DECLARE_READ8_MEMBER(input1_r);
- DECLARE_READ8_MEMBER(input2_r);
+ void mux_w(u8 data);
+ void control_w(u8 data);
+ u8 input1_r();
+ u8 input2_r();
void power_off();
bool m_power = false;
@@ -171,14 +171,14 @@ void const_state::update_display()
m_display->matrix(m_led_select, m_inp_mux);
}
-WRITE8_MEMBER(const_state::mux_w)
+void const_state::mux_w(u8 data)
{
// d0-d7: input mux, led data
m_inp_mux = data;
update_display();
}
-WRITE8_MEMBER(const_state::control_w)
+void const_state::control_w(u8 data)
{
// d0-d2: ?
// d3: ? (goes high at power-off NMI)
@@ -190,7 +190,7 @@ WRITE8_MEMBER(const_state::control_w)
m_beeper->set_state(data >> 7 & 1);
}
-READ8_MEMBER(const_state::input1_r)
+u8 const_state::input1_r()
{
u8 data = 0;
@@ -202,7 +202,7 @@ READ8_MEMBER(const_state::input1_r)
return ~data;
}
-READ8_MEMBER(const_state::input2_r)
+u8 const_state::input2_r()
{
u8 data = 0;
diff --git a/src/mame/drivers/novag_diablo.cpp b/src/mame/drivers/novag_diablo.cpp
index cca701f3bf8..2b28c56d7e0 100644
--- a/src/mame/drivers/novag_diablo.cpp
+++ b/src/mame/drivers/novag_diablo.cpp
@@ -85,11 +85,11 @@ private:
// I/O handlers
void update_display();
- DECLARE_WRITE8_MEMBER(control_w);
- DECLARE_WRITE8_MEMBER(lcd_data_w);
- DECLARE_WRITE8_MEMBER(leds_w);
- DECLARE_READ8_MEMBER(input1_r);
- DECLARE_READ8_MEMBER(input2_r);
+ void control_w(u8 data);
+ void lcd_data_w(u8 data);
+ void leds_w(u8 data);
+ u8 input1_r();
+ u8 input2_r();
HD44780_PIXEL_UPDATE(lcd_pixel_update);
void lcd_palette(palette_device &palette) const;
@@ -156,7 +156,7 @@ void diablo_state::update_display()
m_display->matrix(led_select, m_led_side << 8 | m_led_data);
}
-WRITE8_MEMBER(diablo_state::control_w)
+void diablo_state::control_w(u8 data)
{
// d0: HD44780 E
// d1: HD44780 RS
@@ -175,26 +175,26 @@ WRITE8_MEMBER(diablo_state::control_w)
update_display();
}
-WRITE8_MEMBER(diablo_state::lcd_data_w)
+void diablo_state::lcd_data_w(u8 data)
{
// d0-d7: HD44780 data
m_lcd_data = data;
}
-WRITE8_MEMBER(diablo_state::leds_w)
+void diablo_state::leds_w(u8 data)
{
// d0-d7: chessboard leds
m_led_data = data;
update_display();
}
-READ8_MEMBER(diablo_state::input1_r)
+u8 diablo_state::input1_r()
{
// d0-d7: multiplexed inputs (chessboard squares)
return ~m_board->read_rank(m_inp_mux, true);
}
-READ8_MEMBER(diablo_state::input2_r)
+u8 diablo_state::input2_r()
{
// d0-d2: multiplexed inputs (side panel)
// other: ?
diff --git a/src/mame/drivers/novag_savant.cpp b/src/mame/drivers/novag_savant.cpp
index 296c40364ad..eb60ffc05d7 100644
--- a/src/mame/drivers/novag_savant.cpp
+++ b/src/mame/drivers/novag_savant.cpp
@@ -87,19 +87,19 @@ private:
void mcu_io(address_map &map);
// I/O handlers
- DECLARE_WRITE8_MEMBER(nvram_w);
- DECLARE_READ8_MEMBER(nvram_r);
- DECLARE_READ8_MEMBER(stall_r);
- DECLARE_WRITE8_MEMBER(stall_w);
- DECLARE_READ8_MEMBER(mcustatus_r);
+ void nvram_w(offs_t offset, u8 data);
+ u8 nvram_r(offs_t offset);
+ u8 stall_r(offs_t offset);
+ void stall_w(offs_t offset, u8 data);
+ u8 mcustatus_r();
void lcd1_output_w(u64 data);
void lcd2_output_w(u64 data);
- DECLARE_READ8_MEMBER(databus_r);
- DECLARE_WRITE8_MEMBER(databus_w);
- DECLARE_READ8_MEMBER(control_r);
- DECLARE_WRITE8_MEMBER(control_w);
+ u8 databus_r();
+ void databus_w(u8 data);
+ u8 control_r();
+ void control_w(u8 data);
void lcd_w(u8 data);
u8 input_r();
@@ -135,18 +135,18 @@ void savant_state::machine_start()
// Z80 side
-WRITE8_MEMBER(savant_state::nvram_w)
+void savant_state::nvram_w(offs_t offset, u8 data)
{
// nvram is only d0-d3
m_nvram[offset] = data & 0xf;
}
-READ8_MEMBER(savant_state::nvram_r)
+u8 savant_state::nvram_r(offs_t offset)
{
return m_nvram[offset] & 0xf;
}
-WRITE8_MEMBER(savant_state::stall_w)
+void savant_state::stall_w(offs_t offset, u8 data)
{
// any access to port C0 puts the Z80 into WAIT, sets BUSRQ, and sets MCU EXT INT
m_databus = offset >> 8;
@@ -155,16 +155,16 @@ WRITE8_MEMBER(savant_state::stall_w)
m_maincpu->set_input_line(Z80_INPUT_LINE_BUSRQ, ASSERT_LINE);
}
-READ8_MEMBER(savant_state::stall_r)
+u8 savant_state::stall_r(offs_t offset)
{
m_wait_in = true;
- stall_w(space, offset, 0);
+ stall_w(offset, 0);
// return value is databus (see control_w)
return 0;
}
-READ8_MEMBER(savant_state::mcustatus_r)
+u8 savant_state::mcustatus_r()
{
// d0: MCU P1.2
return BIT(~m_control, 2);
@@ -186,22 +186,22 @@ void savant_state::lcd2_output_w(u64 data)
m_lcd_data = data >> 5 & 0x7ffffff;
}
-READ8_MEMBER(savant_state::databus_r)
+u8 savant_state::databus_r()
{
return ~m_databus;
}
-WRITE8_MEMBER(savant_state::databus_w)
+void savant_state::databus_w(u8 data)
{
m_databus = ~data;
}
-READ8_MEMBER(savant_state::control_r)
+u8 savant_state::control_r()
{
return m_control;
}
-WRITE8_MEMBER(savant_state::control_w)
+void savant_state::control_w(u8 data)
{
// d0: clear EXT INT, clear Z80 WAIT
if (data & ~m_control & 1)
diff --git a/src/mame/drivers/novag_sexpert.cpp b/src/mame/drivers/novag_sexpert.cpp
index a82b622d704..ecb84be7210 100644
--- a/src/mame/drivers/novag_sexpert.cpp
+++ b/src/mame/drivers/novag_sexpert.cpp
@@ -105,12 +105,12 @@ protected:
// I/O handlers
void update_display();
- virtual DECLARE_WRITE8_MEMBER(lcd_control_w);
- virtual DECLARE_WRITE8_MEMBER(lcd_data_w);
- DECLARE_WRITE8_MEMBER(leds_w);
- DECLARE_WRITE8_MEMBER(mux_w);
- DECLARE_READ8_MEMBER(input1_r);
- DECLARE_READ8_MEMBER(input2_r);
+ virtual void lcd_control_w(u8 data);
+ virtual void lcd_data_w(u8 data);
+ void leds_w(u8 data);
+ void mux_w(u8 data);
+ u8 input1_r();
+ u8 input2_r();
HD44780_PIXEL_UPDATE(lcd_pixel_update);
void lcd_palette(palette_device &palette) const;
@@ -173,8 +173,8 @@ private:
void sforte_map(address_map &map);
// I/O handlers
- virtual DECLARE_WRITE8_MEMBER(lcd_control_w) override;
- virtual DECLARE_WRITE8_MEMBER(lcd_data_w) override;
+ virtual void lcd_control_w(u8 data) override;
+ virtual void lcd_data_w(u8 data) override;
TIMER_CALLBACK_MEMBER(beep) { m_beeper->set_state(param); }
emu_timer *m_beeptimer;
@@ -223,7 +223,7 @@ void sexpert_state::update_display()
m_display->matrix(m_inp_mux, m_led_data);
}
-WRITE8_MEMBER(sexpert_state::lcd_control_w)
+void sexpert_state::lcd_control_w(u8 data)
{
// d0: HD44780 RS
// d1: HD44780 R/W
@@ -233,20 +233,20 @@ WRITE8_MEMBER(sexpert_state::lcd_control_w)
m_lcd_control = data & 7;
}
-WRITE8_MEMBER(sexpert_state::lcd_data_w)
+void sexpert_state::lcd_data_w(u8 data)
{
// d0-d7: HD44780 data
m_lcd_data = data;
}
-WRITE8_MEMBER(sexpert_state::leds_w)
+void sexpert_state::leds_w(u8 data)
{
// d0-d7: chessboard leds
m_led_data = data;
update_display();
}
-WRITE8_MEMBER(sexpert_state::mux_w)
+void sexpert_state::mux_w(u8 data)
{
// d0: rom bankswitch
m_rombank->set_entry(data & 1);
@@ -259,7 +259,7 @@ WRITE8_MEMBER(sexpert_state::mux_w)
update_display();
}
-READ8_MEMBER(sexpert_state::input1_r)
+u8 sexpert_state::input1_r()
{
u8 data = 0;
@@ -271,7 +271,7 @@ READ8_MEMBER(sexpert_state::input1_r)
return ~data;
}
-READ8_MEMBER(sexpert_state::input2_r)
+u8 sexpert_state::input2_r()
{
u8 data = 0;
@@ -288,17 +288,17 @@ READ8_MEMBER(sexpert_state::input2_r)
// sforte-specific
-WRITE8_MEMBER(sforte_state::lcd_control_w)
+void sforte_state::lcd_control_w(u8 data)
{
// d3: rom bankswitch
m_rombank->set_entry(data >> 3 & 1);
// LCD pins: same as sexpert
- sexpert_state::lcd_control_w(space, offset, data);
- lcd_data_w(space, 0, m_lcd_data); // refresh inp mux
+ sexpert_state::lcd_control_w(data);
+ lcd_data_w(m_lcd_data); // refresh inp mux
}
-WRITE8_MEMBER(sforte_state::lcd_data_w)
+void sforte_state::lcd_data_w(u8 data)
{
// d0-d2: 74145 to input mux/led select
// 74145 D from lcd control d2 (HD44780 E)
@@ -315,7 +315,7 @@ WRITE8_MEMBER(sforte_state::lcd_data_w)
m_beeptimer->adjust(attotime::from_msec(1), param);
// LCD pins: same as sexpert
- sexpert_state::lcd_data_w(space, offset, data);
+ sexpert_state::lcd_data_w(data);
}
diff --git a/src/mame/drivers/nsm.cpp b/src/mame/drivers/nsm.cpp
index 817578bebd7..6d2ec2a095d 100644
--- a/src/mame/drivers/nsm.cpp
+++ b/src/mame/drivers/nsm.cpp
@@ -40,9 +40,9 @@ public:
private:
- DECLARE_READ8_MEMBER(ff_r);
- DECLARE_WRITE8_MEMBER(cru_w);
- DECLARE_WRITE8_MEMBER(oe_w);
+ uint8_t ff_r();
+ void cru_w(offs_t offset, uint8_t data);
+ void oe_w(uint8_t data);
void nsm_io_map(address_map &map);
void nsm_map(address_map &map);
@@ -82,14 +82,14 @@ void nsm_state::nsm_io_map(address_map &map)
static INPUT_PORTS_START( nsm )
INPUT_PORTS_END
-READ8_MEMBER( nsm_state::ff_r ) { return 1; }
+uint8_t nsm_state::ff_r() { return 1; }
-WRITE8_MEMBER( nsm_state::oe_w )
+void nsm_state::oe_w(uint8_t data)
{
m_cru_count = 9;
}
-WRITE8_MEMBER( nsm_state::cru_w )
+void nsm_state::cru_w(offs_t offset, uint8_t data)
{
offset &= 7;
if (!offset)
diff --git a/src/mame/drivers/nsmpoker.cpp b/src/mame/drivers/nsmpoker.cpp
index f61076423c9..31b21809fa4 100644
--- a/src/mame/drivers/nsmpoker.cpp
+++ b/src/mame/drivers/nsmpoker.cpp
@@ -92,9 +92,9 @@ private:
required_device<tms9995_device> m_maincpu;
required_device<gfxdecode_device> m_gfxdecode;
- DECLARE_WRITE8_MEMBER(nsmpoker_videoram_w);
- DECLARE_WRITE8_MEMBER(nsmpoker_colorram_w);
- DECLARE_READ8_MEMBER(debug_r);
+ void nsmpoker_videoram_w(offs_t offset, uint8_t data);
+ void nsmpoker_colorram_w(offs_t offset, uint8_t data);
+ uint8_t debug_r(offs_t offset);
TILE_GET_INFO_MEMBER(get_bg_tile_info);
void nsmpoker_palette(palette_device &palette) const;
uint32_t screen_update_nsmpoker(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
@@ -109,14 +109,14 @@ private:
*************************/
-WRITE8_MEMBER(nsmpoker_state::nsmpoker_videoram_w)
+void nsmpoker_state::nsmpoker_videoram_w(offs_t offset, uint8_t data)
{
m_videoram[offset] = data;
m_bg_tilemap->mark_tile_dirty(offset);
}
-WRITE8_MEMBER(nsmpoker_state::nsmpoker_colorram_w)
+void nsmpoker_state::nsmpoker_colorram_w(offs_t offset, uint8_t data)
{
m_colorram[offset] = data;
m_bg_tilemap->mark_tile_dirty(offset);
@@ -169,12 +169,12 @@ INTERRUPT_GEN_MEMBER(nsmpoker_state::nsmpoker_interrupt)
m_maincpu->set_input_line(INT_9995_INT1, CLEAR_LINE);
}
-//WRITE8_MEMBER(nsmpoker_state::debug_w)
+//void nsmpoker_state::debug_w(uint8_t data)
//{
// popmessage("written : %02X", data);
//}
-READ8_MEMBER(nsmpoker_state::debug_r)
+uint8_t nsmpoker_state::debug_r(offs_t offset)
{
return BIT(machine().rand(), offset);
}
diff --git a/src/mame/drivers/nss.cpp b/src/mame/drivers/nss.cpp
index e18a3675cea..4370d06bc32 100644
--- a/src/mame/drivers/nss.cpp
+++ b/src/mame/drivers/nss.cpp
@@ -337,18 +337,18 @@ private:
uint8_t m_cart_sel;
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
- DECLARE_READ8_MEMBER(ram_wp_r);
- DECLARE_WRITE8_MEMBER(ram_wp_w);
- DECLARE_READ8_MEMBER(nss_prot_r);
- DECLARE_WRITE8_MEMBER(nss_prot_w);
-
- DECLARE_READ8_MEMBER(port_00_r);
- DECLARE_WRITE8_MEMBER(port_00_w);
- DECLARE_WRITE8_MEMBER(port_01_w);
- DECLARE_WRITE8_MEMBER(port_02_w);
- DECLARE_WRITE8_MEMBER(port_03_w);
- DECLARE_WRITE8_MEMBER(port_04_w);
- DECLARE_WRITE8_MEMBER(port_07_w);
+ uint8_t ram_wp_r(offs_t offset);
+ void ram_wp_w(offs_t offset, uint8_t data);
+ uint8_t nss_prot_r();
+ void nss_prot_w(uint8_t data);
+
+ uint8_t port_00_r();
+ void port_00_w(uint8_t data);
+ void port_01_w(uint8_t data);
+ void port_02_w(uint8_t data);
+ void port_03_w(uint8_t data);
+ void port_04_w(uint8_t data);
+ void port_07_w(uint8_t data);
virtual void machine_start() override;
virtual void machine_reset() override;
@@ -460,19 +460,19 @@ SNES part:
*/
-READ8_MEMBER(nss_state::ram_wp_r)
+uint8_t nss_state::ram_wp_r(offs_t offset)
{
return m_wram[offset];
}
-WRITE8_MEMBER(nss_state::ram_wp_w)
+void nss_state::ram_wp_w(offs_t offset, uint8_t data)
{
if(m_wram_wp_flag)
m_wram[offset] = data;
}
-READ8_MEMBER(nss_state::nss_prot_r)
+uint8_t nss_state::nss_prot_r()
{
int data = 0xe7;
@@ -485,7 +485,7 @@ READ8_MEMBER(nss_state::nss_prot_r)
return data;
}
-WRITE8_MEMBER(nss_state::nss_prot_w)
+void nss_state::nss_prot_w(uint8_t data)
{
if (m_cart_sel == 0)
{
@@ -508,7 +508,7 @@ void nss_state::bios_map(address_map &map)
map(0xe000, 0xffff).rw(FUNC(nss_state::nss_prot_r), FUNC(nss_state::nss_prot_w));
}
-READ8_MEMBER(nss_state::port_00_r)
+uint8_t nss_state::port_00_r()
{
/*
x--- ---- SNES Watchdog (0=SNES did read Joypads, 1=Didn't do so) (ack via 07h.W)
@@ -535,7 +535,7 @@ READ8_MEMBER(nss_state::port_00_r)
return res;
}
-WRITE8_MEMBER(nss_state::port_00_w)
+void nss_state::port_00_w(uint8_t data)
{
/*
xxxx ---- Unknown/unused (should be always 0)
@@ -551,7 +551,7 @@ WRITE8_MEMBER(nss_state::port_00_w)
}
-WRITE8_MEMBER(nss_state::port_01_w)
+void nss_state::port_01_w(uint8_t data)
{
/*
x--- ---- Maybe SNES Joypad Enable? (0=Disable/Demo, 1=Enable/Game)
@@ -576,7 +576,7 @@ WRITE8_MEMBER(nss_state::port_01_w)
m_s_dsp->reset();
}
-WRITE8_MEMBER(nss_state::port_02_w)
+void nss_state::port_02_w(uint8_t data)
{
/*
x--- ---- OSD Clock ? (usually same as Bit6) ;\Chip Select when Bit6=Bit7 ?
@@ -592,7 +592,7 @@ WRITE8_MEMBER(nss_state::port_02_w)
ioport("RTC_OSD")->write(data, 0xff);
}
-WRITE8_MEMBER(nss_state::port_03_w)
+void nss_state::port_03_w(uint8_t data)
{
/*
x--- ---- Layer SNES Enable? (used by token proc, see 7A46h) SNES?
@@ -607,13 +607,13 @@ WRITE8_MEMBER(nss_state::port_03_w)
// popmessage("%02x",data);
}
-WRITE8_MEMBER(nss_state::port_04_w)
+void nss_state::port_04_w(uint8_t data)
{
machine().bookkeeping().coin_counter_w(0, (data >> 0) & 1);
machine().bookkeeping().coin_counter_w(1, (data >> 1) & 1);
}
-WRITE8_MEMBER(nss_state::port_07_w)
+void nss_state::port_07_w(uint8_t data)
{
m_joy_flag = 1;
}
diff --git a/src/mame/drivers/nwk-tr.cpp b/src/mame/drivers/nwk-tr.cpp
index 0c882968841..a13b9e17899 100644
--- a/src/mame/drivers/nwk-tr.cpp
+++ b/src/mame/drivers/nwk-tr.cpp
@@ -342,19 +342,19 @@ private:
std::unique_ptr<uint8_t[]> m_lanc2_ram;
std::unique_ptr<uint32_t[]> m_sharc0_dataram;
std::unique_ptr<uint32_t[]> m_sharc1_dataram;
- DECLARE_WRITE32_MEMBER(paletteram32_w);
- DECLARE_READ32_MEMBER(sysreg_r);
- DECLARE_WRITE32_MEMBER(sysreg_w);
- DECLARE_READ32_MEMBER(lanc1_r);
- DECLARE_WRITE32_MEMBER(lanc1_w);
- DECLARE_READ32_MEMBER(lanc2_r);
- DECLARE_WRITE32_MEMBER(lanc2_w);
- DECLARE_READ32_MEMBER(dsp_dataram0_r);
- DECLARE_WRITE32_MEMBER(dsp_dataram0_w);
- DECLARE_READ32_MEMBER(dsp_dataram1_r);
- DECLARE_WRITE32_MEMBER(dsp_dataram1_w);
- DECLARE_WRITE16_MEMBER(soundtimer_en_w);
- DECLARE_WRITE16_MEMBER(soundtimer_count_w);
+ void paletteram32_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t sysreg_r(offs_t offset, uint32_t mem_mask = ~0);
+ void sysreg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t lanc1_r(offs_t offset);
+ void lanc1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t lanc2_r(offs_t offset, uint32_t mem_mask = ~0);
+ void lanc2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t dsp_dataram0_r(offs_t offset);
+ void dsp_dataram0_w(offs_t offset, uint32_t data);
+ uint32_t dsp_dataram1_r(offs_t offset);
+ void dsp_dataram1_w(offs_t offset, uint32_t data);
+ void soundtimer_en_w(uint16_t data);
+ void soundtimer_count_w(uint16_t data);
DECLARE_WRITE_LINE_MEMBER(voodoo_vblank_0);
DECLARE_WRITE_LINE_MEMBER(voodoo_vblank_1);
double adc12138_input_callback(uint8_t input);
@@ -375,7 +375,7 @@ private:
-WRITE32_MEMBER(nwktr_state::paletteram32_w)
+void nwktr_state::paletteram32_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_generic_paletteram_32[offset]);
data = m_generic_paletteram_32[offset];
@@ -426,7 +426,7 @@ uint32_t nwktr_state::screen_update_rscreen(screen_device &screen, bitmap_rgb32
/*****************************************************************************/
-READ32_MEMBER(nwktr_state::sysreg_r)
+uint32_t nwktr_state::sysreg_r(offs_t offset, uint32_t mem_mask)
{
uint32_t r = 0;
if (offset == 0)
@@ -458,7 +458,7 @@ READ32_MEMBER(nwktr_state::sysreg_r)
return r;
}
-WRITE32_MEMBER(nwktr_state::sysreg_w)
+void nwktr_state::sysreg_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if( offset == 0 )
{
@@ -508,7 +508,7 @@ void nwktr_state::lanc2_init()
m_lanc2_ram = std::make_unique<uint8_t[]>(0x8000);
}
-READ32_MEMBER(nwktr_state::lanc1_r)
+uint32_t nwktr_state::lanc1_r(offs_t offset)
{
switch (offset)
{
@@ -530,12 +530,12 @@ READ32_MEMBER(nwktr_state::lanc1_r)
}
}
-WRITE32_MEMBER(nwktr_state::lanc1_w)
+void nwktr_state::lanc1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
//printf("lanc1_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_maincpu->pc());
}
-READ32_MEMBER(nwktr_state::lanc2_r)
+uint32_t nwktr_state::lanc2_r(offs_t offset, uint32_t mem_mask)
{
uint32_t r = 0;
@@ -565,7 +565,7 @@ READ32_MEMBER(nwktr_state::lanc2_r)
return r;
}
-WRITE32_MEMBER(nwktr_state::lanc2_w)
+void nwktr_state::lanc2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (offset == 0)
{
@@ -650,7 +650,7 @@ TIMER_CALLBACK_MEMBER(nwktr_state::sound_irq)
}
-WRITE16_MEMBER(nwktr_state::soundtimer_en_w)
+void nwktr_state::soundtimer_en_w(uint16_t data)
{
if (data & 1)
{
@@ -665,7 +665,7 @@ WRITE16_MEMBER(nwktr_state::soundtimer_en_w)
}
}
-WRITE16_MEMBER(nwktr_state::soundtimer_count_w)
+void nwktr_state::soundtimer_count_w(uint16_t data)
{
// Reset the count
m_sound_irq_timer->adjust(attotime::from_usec(m_sound_timer_usec));
@@ -719,22 +719,22 @@ void nwktr_state::sound_memmap(address_map &map)
/*****************************************************************************/
-READ32_MEMBER(nwktr_state::dsp_dataram0_r)
+uint32_t nwktr_state::dsp_dataram0_r(offs_t offset)
{
return m_sharc0_dataram[offset] & 0xffff;
}
-WRITE32_MEMBER(nwktr_state::dsp_dataram0_w)
+void nwktr_state::dsp_dataram0_w(offs_t offset, uint32_t data)
{
m_sharc0_dataram[offset] = data;
}
-READ32_MEMBER(nwktr_state::dsp_dataram1_r)
+uint32_t nwktr_state::dsp_dataram1_r(offs_t offset)
{
return m_sharc1_dataram[offset] & 0xffff;
}
-WRITE32_MEMBER(nwktr_state::dsp_dataram1_w)
+void nwktr_state::dsp_dataram1_w(offs_t offset, uint32_t data)
{
m_sharc1_dataram[offset] = data;
}
diff --git a/src/mame/drivers/nyny.cpp b/src/mame/drivers/nyny.cpp
index 77bdcaa9822..4f86a5a9cb1 100644
--- a/src/mame/drivers/nyny.cpp
+++ b/src/mame/drivers/nyny.cpp
@@ -143,11 +143,11 @@ private:
required_device<generic_latch_8_device> m_soundlatch2;
required_device<generic_latch_8_device> m_soundlatch3;
- DECLARE_WRITE8_MEMBER(audio_1_command_w);
- DECLARE_WRITE8_MEMBER(audio_1_answer_w);
+ void audio_1_command_w(uint8_t data);
+ void audio_1_answer_w(uint8_t data);
void audio_2_command_w(uint8_t data);
- DECLARE_READ8_MEMBER(nyny_pia_1_2_r);
- DECLARE_WRITE8_MEMBER(nyny_pia_1_2_w);
+ uint8_t nyny_pia_1_2_r(offs_t offset);
+ void nyny_pia_1_2_w(offs_t offset, uint8_t data);
DECLARE_WRITE_LINE_MEMBER(main_cpu_irq);
DECLARE_WRITE_LINE_MEMBER(main_cpu_firq);
void pia_2_port_a_w(uint8_t data);
@@ -369,14 +369,14 @@ MC6845_END_UPDATE( nyny_state::crtc_end_update )
*
*************************************/
-WRITE8_MEMBER(nyny_state::audio_1_command_w)
+void nyny_state::audio_1_command_w(uint8_t data)
{
m_soundlatch->write(data);
m_audiocpu->set_input_line(M6802_IRQ_LINE, HOLD_LINE);
}
-WRITE8_MEMBER(nyny_state::audio_1_answer_w)
+void nyny_state::audio_1_answer_w(uint8_t data)
{
m_soundlatch3->write(data);
m_maincpu->set_input_line(M6809_IRQ_LINE, HOLD_LINE);
@@ -410,7 +410,7 @@ void nyny_state::audio_2_command_w(uint8_t data)
*
*************************************/
-READ8_MEMBER(nyny_state::nyny_pia_1_2_r)
+uint8_t nyny_state::nyny_pia_1_2_r(offs_t offset)
{
uint8_t ret = 0;
@@ -422,7 +422,7 @@ READ8_MEMBER(nyny_state::nyny_pia_1_2_r)
}
-WRITE8_MEMBER(nyny_state::nyny_pia_1_2_w)
+void nyny_state::nyny_pia_1_2_w(offs_t offset, uint8_t data)
{
/* the address bits are directly connected to the chip selects */
if (BIT(offset, 2)) m_pia1->write(offset & 0x03, data);
diff --git a/src/mame/machine/megacd.cpp b/src/mame/machine/megacd.cpp
index 5d7a7f35e83..d8e41d48c13 100644
--- a/src/mame/machine/megacd.cpp
+++ b/src/mame/machine/megacd.cpp
@@ -1838,7 +1838,7 @@ TIMER_DEVICE_CALLBACK_MEMBER( sega_segacd_device::dma_timer_callback )
// todo: accurate timing of this!
#define RATE 256
- m_lc89510_temp->CDC_Do_DMA(machine(), RATE);
+ m_lc89510_temp->CDC_Do_DMA(RATE);
// timed reset of flags
scd_mode_dmna_ret_flags |= 0x0021;
diff --git a/src/mame/machine/megacdcd.cpp b/src/mame/machine/megacdcd.cpp
index c8b7fb440fe..59b40146773 100644
--- a/src/mame/machine/megacdcd.cpp
+++ b/src/mame/machine/megacdcd.cpp
@@ -290,7 +290,7 @@ void lc89510_temp_device::CDD_GetStatus(void)
}
-void lc89510_temp_device::CDD_Stop(running_machine &machine)
+void lc89510_temp_device::CDD_Stop()
{
CLEAR_CDD_RESULT
STOP_CDC_READ
@@ -448,7 +448,7 @@ uint32_t lc89510_temp_device::getmsf_from_regs(void)
return msf;
}
-void lc89510_temp_device::CDD_Play(running_machine &machine)
+void lc89510_temp_device::CDD_Play()
{
CLEAR_CDD_RESULT
uint32_t msf = getmsf_from_regs();
@@ -489,7 +489,7 @@ void lc89510_temp_device::CDD_Seek(void)
}
-void lc89510_temp_device::CDD_Pause(running_machine &machine)
+void lc89510_temp_device::CDD_Pause()
{
CLEAR_CDD_RESULT
STOP_CDC_READ
@@ -507,7 +507,7 @@ void lc89510_temp_device::CDD_Pause(running_machine &machine)
}
-void lc89510_temp_device::CDD_Resume(running_machine &machine)
+void lc89510_temp_device::CDD_Resume()
{
CLEAR_CDD_RESULT
STOP_CDC_READ
@@ -526,13 +526,13 @@ void lc89510_temp_device::CDD_Resume(running_machine &machine)
}
-void lc89510_temp_device::CDD_FF(running_machine &machine)
+void lc89510_temp_device::CDD_FF()
{
fatalerror("Fast Forward unsupported\n");
}
-void lc89510_temp_device::CDD_RW(running_machine &machine)
+void lc89510_temp_device::CDD_RW()
{
fatalerror("Fast Rewind unsupported\n");
}
@@ -613,7 +613,7 @@ void lc89510_temp_device::lc89510_Reset(void)
}
-void lc89510_temp_device::CDC_Do_DMA(running_machine& machine, int rate)
+void lc89510_temp_device::CDC_Do_DMA(int rate)
{
uint32_t length;
@@ -633,7 +633,7 @@ void lc89510_temp_device::CDC_Do_DMA(running_machine& machine, int rate)
if (dma_count_register <= (rate * 2))
{
length = (dma_count_register + 1) >> 1;
- CDC_End_Transfer(machine);
+ CDC_End_Transfer();
}
else
length = rate;
@@ -662,7 +662,7 @@ void lc89510_temp_device::CDC_Do_DMA(running_machine& machine, int rate)
-uint16_t lc89510_temp_device::CDC_Host_r(running_machine& machine, uint16_t type)
+uint16_t lc89510_temp_device::CDC_Host_r(uint16_t type)
{
uint16_t destination = CDC_REG0 & 0x0700;
@@ -678,7 +678,7 @@ uint16_t lc89510_temp_device::CDC_Host_r(running_machine& machine, uint16_t type
{
if (type==READ_SUB) dma_count_register = 0;
- CDC_End_Transfer(machine);
+ CDC_End_Transfer();
}
LC8951RegistersW[REG_W_DBCL] = dma_count_register & 0xff; LC8951RegistersW[REG_W_DBCH] = (dma_count_register>>8) & 0xff;
@@ -830,7 +830,7 @@ void lc89510_temp_device::CDC_Reg_w(uint8_t data)
-void lc89510_temp_device::CDD_Process(running_machine& machine, int reason)
+void lc89510_temp_device::CDD_Process(int reason)
{
CDD_Export();
CHECK_SCD_LV4_INTERRUPT
@@ -874,7 +874,7 @@ static const char *const CDD_import_cmdnames[] =
"<undefined> (f)" // F
};
-bool lc89510_temp_device::CDD_Import(running_machine& machine)
+bool lc89510_temp_device::CDD_Import()
{
// don't execute the command if the checksum isn't valid
if (!CDD_Check_TX_Checksum())
@@ -889,14 +889,14 @@ bool lc89510_temp_device::CDD_Import(running_machine& machine)
switch (CDD_TX[0])
{
case CMD_STATUS: CDD_GetStatus(); break;
- case CMD_STOPALL: CDD_Stop(machine); break;
+ case CMD_STOPALL: CDD_Stop(); break;
case CMD_GETTOC: CDD_Handle_TOC_Commands(); break;
- case CMD_READ: CDD_Play(machine); break;
+ case CMD_READ: CDD_Play(); break;
case CMD_SEEK: CDD_Seek(); break;
- case CMD_STOP: CDD_Pause(machine); break;
- case CMD_RESUME: CDD_Resume(machine); break;
- case CMD_FF: CDD_FF(machine); break;
- case CMD_RW: CDD_RW(machine); break;
+ case CMD_STOP: CDD_Pause(); break;
+ case CMD_RESUME: CDD_Resume(); break;
+ case CMD_FF: CDD_FF(); break;
+ case CMD_RW: CDD_RW(); break;
case CMD_INIT: CDD_Init(); break;
case CMD_CLOSE: CDD_Open(); break;
case CMD_OPEN: CDD_Close(); break;
@@ -914,17 +914,17 @@ bool lc89510_temp_device::CDD_Import(running_machine& machine)
-WRITE16_MEMBER( lc89510_temp_device::segacd_cdc_mode_address_w )
+void lc89510_temp_device::segacd_cdc_mode_address_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&CDC_REG0);
}
-READ16_MEMBER( lc89510_temp_device::segacd_cdc_mode_address_r )
+uint16_t lc89510_temp_device::segacd_cdc_mode_address_r()
{
return CDC_REG0;
}
-WRITE16_MEMBER( lc89510_temp_device::segacd_cdc_data_w )
+void lc89510_temp_device::segacd_cdc_data_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&CDC_REG1);
@@ -932,7 +932,7 @@ WRITE16_MEMBER( lc89510_temp_device::segacd_cdc_data_w )
CDC_Reg_w(data);
}
-READ16_MEMBER( lc89510_temp_device::segacd_cdc_data_r )
+uint16_t lc89510_temp_device::segacd_cdc_data_r(offs_t offset, uint16_t mem_mask)
{
uint16_t retdat = 0x0000;
@@ -943,25 +943,25 @@ READ16_MEMBER( lc89510_temp_device::segacd_cdc_data_r )
}
-READ16_MEMBER( lc89510_temp_device::cdc_data_sub_r )
+uint16_t lc89510_temp_device::cdc_data_sub_r()
{
- return CDC_Host_r(machine(), READ_SUB);
+ return CDC_Host_r(READ_SUB);
}
-READ16_MEMBER( lc89510_temp_device::cdc_data_main_r )
+uint16_t lc89510_temp_device::cdc_data_main_r()
{
- return CDC_Host_r(machine(), READ_MAIN);
+ return CDC_Host_r(READ_MAIN);
}
-READ16_MEMBER( lc89510_temp_device::segacd_irq_mask_r )
+uint16_t lc89510_temp_device::segacd_irq_mask_r()
{
return segacd_irq_mask;
}
-WRITE16_MEMBER( lc89510_temp_device::segacd_irq_mask_w )
+void lc89510_temp_device::segacd_irq_mask_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
{
@@ -976,7 +976,7 @@ WRITE16_MEMBER( lc89510_temp_device::segacd_irq_mask_w )
if (!(segacd_irq_mask & 0x10))
{
segacd_irq_mask = data & 0x7e;
- CDD_Process(machine(), 0);
+ CDD_Process(0);
return;
}
}
@@ -991,13 +991,13 @@ WRITE16_MEMBER( lc89510_temp_device::segacd_irq_mask_w )
}
}
-READ16_MEMBER( lc89510_temp_device::segacd_cdd_ctrl_r )
+uint16_t lc89510_temp_device::segacd_cdd_ctrl_r()
{
return CDD_CONTROL;
}
-WRITE16_MEMBER( lc89510_temp_device::segacd_cdd_ctrl_w )
+void lc89510_temp_device::segacd_cdd_ctrl_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
{
@@ -1014,7 +1014,7 @@ WRITE16_MEMBER( lc89510_temp_device::segacd_cdd_ctrl_w )
{
if (segacd_irq_mask&0x10)
{
- CDD_Process(machine(), 1);
+ CDD_Process(1);
}
}
}
@@ -1045,7 +1045,7 @@ uint8_t lc89510_temp_device::neocd_cdd_rx_r()
}
// mapped like 'ram'
-READ8_MEMBER( lc89510_temp_device::segacd_cdd_rx_r )
+uint8_t lc89510_temp_device::segacd_cdd_rx_r(offs_t offset)
{
return CDD_RX[offset];
}
@@ -1060,13 +1060,13 @@ void lc89510_temp_device::neocd_cdd_tx_w(uint8_t data)
}
}
-WRITE8_MEMBER( lc89510_temp_device::segacd_cdd_tx_w )
+void lc89510_temp_device::segacd_cdd_tx_w(offs_t offset, uint8_t data)
{
CDD_TX[offset] = data;
if(offset == 9)
{
- CDD_Import(machine());
+ CDD_Import();
}
}
@@ -1075,12 +1075,12 @@ WRITE8_MEMBER( lc89510_temp_device::segacd_cdd_tx_w )
-READ16_MEMBER( lc89510_temp_device::segacd_cdfader_r )
+uint16_t lc89510_temp_device::segacd_cdfader_r()
{
return 0;
}
-WRITE16_MEMBER( lc89510_temp_device::segacd_cdfader_w )
+void lc89510_temp_device::segacd_cdfader_w(uint16_t data)
{
static double cdfader_vol;
if(data & 0x800f)
@@ -1144,7 +1144,7 @@ TIMER_DEVICE_CALLBACK_MEMBER( lc89510_temp_device::segacd_access_timer_callback
if (SCD_READ_ENABLED) // if (nff0002 & 0x0050) if (nff0002 & 0x0500);
{
set_data_audio_mode();
- Read_LBA_To_Buffer(machine());
+ Read_LBA_To_Buffer();
}
}
@@ -1193,7 +1193,7 @@ void lc89510_temp_device::NeoCDCommsControl(uint8_t clock, uint8_t send)
{
if (CDD_TX[0])
{
- if (!CDD_Import(machine()))
+ if (!CDD_Import())
return;
CDD_Export(true); // true == neocd hack,
@@ -1264,7 +1264,7 @@ void lc89510_temp_device::LC8915EndTransfer()
}
-void lc89510_temp_device::CDC_End_Transfer(running_machine& machine)
+void lc89510_temp_device::CDC_End_Transfer()
{
STOP_CDC_DMA
CDC_REG0 |= 0x8000;
@@ -1283,7 +1283,7 @@ void lc89510_temp_device::CDC_End_Transfer(running_machine& machine)
-void lc89510_temp_device::scd_ctrl_checks(running_machine& machine)
+void lc89510_temp_device::scd_ctrl_checks()
{
LC8951RegistersR[REG_R_STAT0] = 0x80;
@@ -1327,7 +1327,7 @@ void lc89510_temp_device::scd_advance_current_readpos(void)
}
-int lc89510_temp_device::Read_LBA_To_Buffer(running_machine& machine)
+int lc89510_temp_device::Read_LBA_To_Buffer()
{
bool data_track = false;
if (CDD_CONTROL & 0x0100) data_track = true;
@@ -1380,7 +1380,7 @@ int lc89510_temp_device::Read_LBA_To_Buffer(running_machine& machine)
}
}
- scd_ctrl_checks(machine);
+ scd_ctrl_checks();
}
diff --git a/src/mame/machine/megacdcd.h b/src/mame/machine/megacdcd.h
index 3eec58bc6dd..1ee0f562094 100644
--- a/src/mame/machine/megacdcd.h
+++ b/src/mame/machine/megacdcd.h
@@ -30,23 +30,23 @@ public:
uint16_t get_segacd_irq_mask() const { return segacd_irq_mask; }
- DECLARE_READ16_MEMBER( segacd_irq_mask_r );
- DECLARE_WRITE16_MEMBER( segacd_irq_mask_w );
- DECLARE_READ16_MEMBER( segacd_cdd_ctrl_r );
- DECLARE_WRITE16_MEMBER( segacd_cdd_ctrl_w );
- DECLARE_READ8_MEMBER( segacd_cdd_rx_r );
- DECLARE_WRITE8_MEMBER( segacd_cdd_tx_w );
- READ16_MEMBER( segacd_cdfader_r );
- WRITE16_MEMBER( segacd_cdfader_w );
-
- WRITE16_MEMBER( segacd_cdc_mode_address_w );
- READ16_MEMBER( segacd_cdc_mode_address_r );
- WRITE16_MEMBER( segacd_cdc_data_w );
- READ16_MEMBER( segacd_cdc_data_r );
- READ16_MEMBER( cdc_data_sub_r );
- READ16_MEMBER( cdc_data_main_r );
-
- void CDC_Do_DMA(running_machine& machine, int rate);
+ uint16_t segacd_irq_mask_r();
+ void segacd_irq_mask_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t segacd_cdd_ctrl_r();
+ void segacd_cdd_ctrl_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint8_t segacd_cdd_rx_r(offs_t offset);
+ void segacd_cdd_tx_w(offs_t offset, uint8_t data);
+ uint16_t segacd_cdfader_r();
+ void segacd_cdfader_w(uint16_t data);
+
+ void segacd_cdc_mode_address_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t segacd_cdc_mode_address_r();
+ void segacd_cdc_data_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t segacd_cdc_data_r(offs_t offset, uint16_t mem_mask = ~0);
+ uint16_t cdc_data_sub_r();
+ uint16_t cdc_data_main_r();
+
+ void CDC_Do_DMA(int rate);
uint8_t CDC_Reg_r(void);
void CDC_Reg_w(uint8_t data);
@@ -132,11 +132,11 @@ protected:
void CDD_DoChecksum(void);
bool CDD_Check_TX_Checksum(void);
void CDD_Export(bool neocd_hack = false);
- void scd_ctrl_checks(running_machine& machine);
+ void scd_ctrl_checks();
void scd_advance_current_readpos(void);
- int Read_LBA_To_Buffer(running_machine& machine);
+ int Read_LBA_To_Buffer();
void CDD_GetStatus(void);
- void CDD_Stop(running_machine &machine);
+ void CDD_Stop();
void CDD_GetPos(void);
void CDD_GetTrackPos(void);
void CDD_GetTrack(void);
@@ -145,12 +145,12 @@ protected:
void CDD_GetTrackAdr(void);
void CDD_GetTrackType(void);
uint32_t getmsf_from_regs(void);
- void CDD_Play(running_machine &machine);
+ void CDD_Play();
void CDD_Seek(void);
- void CDD_Pause(running_machine &machine);
- void CDD_Resume(running_machine &machine);
- void CDD_FF(running_machine &machine);
- void CDD_RW(running_machine &machine);
+ void CDD_Pause();
+ void CDD_Resume();
+ void CDD_FF();
+ void CDD_RW();
void CDD_Open(void);
void CDD_Close(void);
void CDD_Init(void);
@@ -158,11 +158,11 @@ protected:
void CDD_Reset(void);
void CDC_Reset(void);
void lc89510_Reset(void);
- void CDC_End_Transfer(running_machine& machine);
- uint16_t CDC_Host_r(running_machine& machine, uint16_t type);
- void CDD_Process(running_machine& machine, int reason);
+ void CDC_End_Transfer();
+ uint16_t CDC_Host_r(uint16_t type);
+ void CDD_Process(int reason);
void CDD_Handle_TOC_Commands(void);
- bool CDD_Import(running_machine& machine);
+ bool CDD_Import();
uint16_t segacd_irq_mask;