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author AJR <ajrhacker@users.noreply.github.com>2022-10-01 23:16:47 -0400
committer AJR <ajrhacker@users.noreply.github.com>2022-10-01 23:20:08 -0400
commit9f3e4fe03aac841c2ae5440752046ad73065d23e (patch)
treeb82bfdcba91540fb3fdc1411134d81ac9b372829
parent371eede3a4becef6c2e1ccc3eecb2d87c01b394c (diff)
mn1880: Additional notes
-rw-r--r--src/devices/cpu/mn1880/mn1880.cpp11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/devices/cpu/mn1880/mn1880.cpp b/src/devices/cpu/mn1880/mn1880.cpp
index 9ea47debcb0..0a23b988918 100644
--- a/src/devices/cpu/mn1880/mn1880.cpp
+++ b/src/devices/cpu/mn1880/mn1880.cpp
@@ -64,6 +64,17 @@
contents of locations about to be written to may show misleading
values. Likewise, PCs at which watchpoint hits occur may be
incorrectly reported for writes.
+ * Due to the pipelining of writes, an interrupt may be accepted during
+ an instruction which attempts to disable interrupts by setting the
+ IEMASK bit, which may be cleared insted when control reaches the next
+ sequential instruction from a RETI. This sequencing glitch is
+ documented in the MN187XX23 user's manual, along with a failsafe way
+ of setting IEMASK, and similar workarounds in extant program code
+ suggest it is likewise present in the MN1880 series.
+ * The optional MMU, which expands the memory spaces in certain models
+ which contain neither internal ROM nor RAM, has been emulated only
+ to the extent required by psr500, though it likely has a few other
+ features and quirks.
***************************************************************************/