diff options
author | 2014-06-30 20:38:12 +0000 | |
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committer | 2014-06-30 20:38:12 +0000 | |
commit | 866e9562ddf0bf942243b77779517c00e02d10e3 (patch) | |
tree | 14dac35a024950fe5971d0d0d447a1d953abd73b | |
parent | 38d3fa734ce8111801a796c8d95d2f8862fe9d26 (diff) |
powerpc: Modernised cpu core (nw)
-rw-r--r-- | src/emu/cpu/powerpc/ppc.c | 302 | ||||
-rw-r--r-- | src/emu/cpu/powerpc/ppc.h | 649 | ||||
-rw-r--r-- | src/emu/cpu/powerpc/ppccom.c | 2222 | ||||
-rw-r--r-- | src/emu/cpu/powerpc/ppccom.h | 187 | ||||
-rw-r--r-- | src/emu/cpu/powerpc/ppcdrc.c | 2613 | ||||
-rw-r--r-- | src/emu/cpu/powerpc/ppcfe.c | 82 | ||||
-rw-r--r-- | src/emu/cpu/powerpc/ppcfe.h | 14 | ||||
-rw-r--r-- | src/emu/drivers/testcpu.c | 10 | ||||
-rw-r--r-- | src/mame/drivers/cobra.c | 32 | ||||
-rw-r--r-- | src/mame/drivers/firebeat.c | 10 | ||||
-rw-r--r-- | src/mame/drivers/gticlub.c | 6 | ||||
-rw-r--r-- | src/mame/drivers/hornet.c | 28 | ||||
-rw-r--r-- | src/mame/drivers/konamim2.c | 9 | ||||
-rw-r--r-- | src/mame/drivers/model3.c | 30 | ||||
-rw-r--r-- | src/mame/drivers/nwk-tr.c | 6 | ||||
-rw-r--r-- | src/mame/drivers/taitopjc.c | 8 | ||||
-rw-r--r-- | src/mame/drivers/taitotz.c | 14 | ||||
-rw-r--r-- | src/mame/drivers/triforce.c | 4 | ||||
-rw-r--r-- | src/mame/drivers/ultrsprt.c | 6 | ||||
-rw-r--r-- | src/mame/drivers/viper.c | 13 | ||||
-rw-r--r-- | src/mame/drivers/zr107.c | 6 | ||||
-rw-r--r-- | src/mess/drivers/dm7000.c | 11 | ||||
-rw-r--r-- | src/mess/includes/dm7000.h | 2 |
23 files changed, 2998 insertions, 3266 deletions
diff --git a/src/emu/cpu/powerpc/ppc.c b/src/emu/cpu/powerpc/ppc.c index 6aec68de555..6edbd78f3f1 100644 --- a/src/emu/cpu/powerpc/ppc.c +++ b/src/emu/cpu/powerpc/ppc.c @@ -109,34 +109,34 @@ static void ppc403_spu_w(UINT32 a, UINT8 d); #define AABIT (op & 0x2) #define LKBIT (op & 0x1) -#define REG(x) (ppc.r[x]) -#define LR (ppc.lr) -#define CTR (ppc.ctr) -#define XER (ppc.xer) -#define CR(x) (ppc.cr[x]) -#define MSR (ppc.msr) -#define SRR0 (ppc.srr0) -#define SRR1 (ppc.srr1) -#define SRR2 (ppc.srr2) -#define SRR3 (ppc.srr3) -#define EVPR (ppc.evpr) -#define EXIER (ppc.exier) -#define EXISR (ppc.exisr) -#define DEC (ppc.dec) +#define REG(x) (m_r[x]) +#define LR (m_lr) +#define CTR (m_ctr) +#define XER (m_xer) +#define CR(x) (m_cr[x]) +#define MSR (m_msr) +#define SRR0 (m_srr0) +#define SRR1 (m_srr1) +#define SRR2 (m_srr2) +#define SRR3 (m_srr3) +#define EVPR (m_evpr) +#define EXIER (m_exier) +#define EXISR (m_exisr) +#define DEC (m_dec) // Stuff added for the 6xx -#define FPR(x) (ppc.fpr[x]) +#define FPR(x) (m_fpr[x]) #define FM ((op >> 17) & 0xFF) #define SPRF (((op >> 6) & 0x3E0) | ((op >> 16) & 0x1F)) #define CHECK_SUPERVISOR() \ - if((ppc.msr & 0x4000) != 0){ \ + if((m_msr & 0x4000) != 0){ \ } #define CHECK_FPU_AVAILABLE() \ - if((ppc.msr & 0x2000) == 0){ \ + if((m_msr & 0x2000) == 0){ \ } static UINT32 ppc_field_xlat[256]; @@ -154,7 +154,7 @@ static UINT32 ppc_field_xlat[256]; #define BITMASK_0(n) (UINT32)(((UINT64)1 << n) - 1) -#define CRBIT(x) ((ppc.cr[x / 4] & (1 << (3 - (x % 4)))) ? 1 : 0) +#define CRBIT(x) ((m_cr[x / 4] & (1 << (3 - (x % 4)))) ? 1 : 0) #define _BIT(n) (1 << (n)) #define GET_ROTATE_MASK(mb,me) (ppc_rotate_mask[mb][me]) #define ADD_CA(r,a,b) ((UINT32)r < (UINT32)a) @@ -195,197 +195,127 @@ static UINT32 ppc_field_xlat[256]; #define BYTE_REVERSE16(x) ((((x) >> 8) & 0xff) | (((x) << 8) & 0xff00)) #define BYTE_REVERSE32(x) ((((x) >> 24) & 0xff) | (((x) >> 8) & 0xff00) | (((x) << 8) & 0xff0000) | (((x) << 24) & 0xff000000)) -struct DMA_REGS { - UINT32 cr; - UINT32 da; - UINT32 sa; - UINT32 ct; - UINT32 cc; -}; -struct SPU_REGS { - UINT8 spls; - UINT8 sphs; - UINT16 brd; - UINT8 spctl; - UINT8 sprc; - UINT8 sptc; - UINT8 sprb; - UINT8 sptb; - emu_timer *rx_timer; - emu_timer *tx_timer; -}; +const device_type PPC403 = &device_creator<ppc403_device>; +const device_type PPC405 = &device_creator<ppc405_device>; +const device_type PPC601 = &device_creator<ppc601_device>; +const device_type PPC602 = &device_creator<ppc602_device>; +const device_type PPC603 = &device_creator<ppc603_device>; +const device_type PPC603E = &device_creator<ppc603e_device>; +const device_type PPC603R = &device_creator<ppc603r_device>; +const device_type PPC604 = &device_creator<ppc604_device>; +const device_type MPC8240 = &device_creator<mpc8240_device>; +const device_type PPC403GA = &device_creator<ppc403ga_device>; +const device_type PPC403GCX = &device_creator<ppc403gcx_device>; +const device_type PPC405GP = &device_creator<ppc405gp_device>; -union FPR { - UINT64 id; - double fd; -}; -union FPR32 { - UINT32 i; - float f; +struct PPC_OPCODE { + int code; + int subcode; + void (* handler)(UINT32); }; -struct BATENT { - UINT32 u; - UINT32 l; -}; -struct PPC_REGS { - UINT32 r[32]; - UINT32 pc; - UINT32 npc; - - UINT32 lr; - UINT32 ctr; - UINT32 xer; - UINT32 msr; - UINT8 cr[8]; - UINT32 pvr; - UINT32 srr0; - UINT32 srr1; - UINT32 srr2; - UINT32 srr3; - UINT32 hid0; - UINT32 hid1; - UINT32 hid2; - UINT32 sdr1; - UINT32 sprg[4]; - - UINT32 dsisr; - UINT32 dar; - UINT32 ear; - UINT32 dmiss; - UINT32 dcmp; - UINT32 hash1; - UINT32 hash2; - UINT32 imiss; - UINT32 icmp; - UINT32 rpa; - - - BATENT ibat[4]; - BATENT dbat[4]; - - UINT32 evpr; - UINT32 exier; - UINT32 exisr; - UINT32 bear; - UINT32 besr; - UINT32 iocr; - UINT32 br[8]; - UINT32 iabr; - UINT32 esr; - UINT32 iccr; - UINT32 dccr; - UINT32 pit; - UINT32 pit_counter; - UINT32 pit_int_enable; - UINT32 tsr; - UINT32 dbsr; - UINT32 sgr; - UINT32 pid; - UINT32 pbl1, pbl2, pbu1, pbu2; - UINT32 fit_bit; - UINT32 fit_int_enable; - UINT32 wdt_bit; - UINT32 wdt_int_enable; - UINT32 dac1, dac2; - UINT32 iac1, iac2; - - SPU_REGS spu; - DMA_REGS dma[4]; - UINT32 dmasr; - - int reserved; - UINT32 reserved_address; - - int interrupt_pending; - - UINT64 tb; /* 56-bit timebase register */ - - device_irq_acknowledge_delegate irq_callback; - legacy_cpu_device *device; - address_space *program; - - // STUFF added for the 6xx series - UINT32 dec, dec_frac; - UINT32 fpscr; - - FPR fpr[32]; - UINT32 sr[16]; - - int is603; - int is602; - - /* PowerPC 602 specific registers */ - UINT32 lt; - UINT32 sp; - UINT32 tcr; - UINT32 ibr; - UINT32 esasrr; - UINT32 sebr; - UINT32 ser; - - /* PowerPC function pointers for memory accesses/exceptions */ - jmp_buf exception_jmpbuf; - UINT8 (*read8)(address_space &space, offs_t address); - UINT16 (*read16)(address_space &space, offs_t address); - UINT32 (*read32)(address_space &space, offs_t address); - UINT64 (*read64)(address_space &space, offs_t address); - void (*write8)(address_space &space, offs_t address, UINT8 data); - void (*write16)(address_space &space, offs_t address, UINT16 data); - void (*write32)(address_space &space, offs_t address, UINT32 data); - void (*write64)(address_space &space, offs_t address, UINT64 data); - UINT16 (*read16_unaligned)(address_space &space, offs_t address); - UINT32 (*read32_unaligned)(address_space &space, offs_t address); - UINT64 (*read64_unaligned)(address_space &space, offs_t address); - void (*write16_unaligned)(address_space &space, offs_t address, UINT16 data); - void (*write32_unaligned)(address_space &space, offs_t address, UINT32 data); - void (*write64_unaligned)(address_space &space, offs_t address, UINT64 data); - - void (* optable19[1024])(UINT32); - void (* optable31[1024])(UINT32); - void (* optable59[1024])(UINT32); - void (* optable63[1024])(UINT32); - void (* optable[64])(UINT32); -}; +static UINT32 ppc_rotate_mask[32][32]; +#define ROPCODE(pc) memory_decrypted_read_dword(m_program, pc) +#define ROPCODE64(pc) memory_decrypted_read_qword(m_program, DWORD_XOR_BE(pc)) + + +ppc_device::ppc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int address_bits, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__) + , m_program_config("program", ENDIANNESS_BIG, address_bits, 32) + , m_core(NULL) + , c_bus_frequency(0) + , m_bus_freq_multiplier(1) + , m_flavor(flavor) + , m_cap(cap) + , m_tb_divisor(tb_divisor) + , m_vtlb(NULL) + , m_cache(CACHE_SIZE + sizeof(internal_ppc_state)) +{ +} +//ppc403_device::ppc403_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) +// : ppc_device(mconfig, PPC403, "PPC403", tag, owner, clock, "ppc403", 32) +//{ +//} +// +//ppc405_device::ppc405_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) +// : ppc_device(mconfig, PPC405, "PPC405", tag, owner, clock, "ppc405", 32) +//{ +//} + +ppc603_device::ppc603_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC603", "PowerPC 603", tag, owner, clock, "ppc603", 64, PPC_MODEL_603, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4) +{ +} -struct PPC_OPCODE { - int code; - int subcode; - void (* handler)(UINT32); -}; +ppc603e_device::ppc603e_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC603E, "PowerPC 603e", tag, owner, clock, "ppc603e", 64, PPC_MODEL_603E, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4) +{ +} +ppc603r_device::ppc603r_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC603R, "PowerPC 603R", tag, owner, clock, "ppc603r", 64, PPC_MODEL_603R, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4) +{ +} +ppc602_device::ppc602_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC602, "PowerPC 602", tag, owner, clock, "ppc602", 64, PPC_MODEL_602, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4) +{ +} -static int ppc_icount; -static int ppc_tb_base_icount; -static int ppc_dec_base_icount; -static int ppc_dec_trigger_cycle; -static int bus_freq_multiplier = 1; -static PPC_REGS ppc; -static UINT32 ppc_rotate_mask[32][32]; +mpc8240_device::mpc8240_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, MPC8240, "PowerPC MPC8240", tag, owner, clock, "mpc8240", 64, PPC_MODEL_MPC8240, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4/* unknown */) +{ +} + +ppc601_device::ppc601_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC601, "PowerPC 601", tag, owner, clock, "ppc601", 64, PPC_MODEL_601, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_MFIOC | PPCCAP_601BAT, 0/* no TB */) +{ +} + +ppc604_device::ppc604_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC604, "PowerPC 604", tag, owner, clock, "ppc604", 64, PPC_MODEL_604, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_604_MMU, 4) +{ +} -#define ROPCODE(pc) memory_decrypted_read_dword(ppc.program, pc) -#define ROPCODE64(pc) memory_decrypted_read_qword(ppc.program, DWORD_XOR_BE(pc)) +ppc4xx_device::ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor) + : ppc_device(mconfig, type, name, tag, owner, clock, shortname, 64, flavor, cap, tb_divisor) // TODO address bits, ppccom has 31 address bits?? +{ +} + +ppc403ga_device::ppc403ga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc4xx_device(mconfig, PPC403GA, "PowerPC 403GA", tag, owner, clock, "ppc403ga", PPC_MODEL_403GA, PPCCAP_4XX, 1) +{ +} + +ppc403gcx_device::ppc403gcx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc4xx_device(mconfig, PPC403GCX, "PowerPC 403GCX", tag, owner, clock, "ppc403gcx", PPC_MODEL_403GCX, PPCCAP_4XX, 1) +{ +} + +ppc405gp_device::ppc405gp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc4xx_device(mconfig, PPC405GP, "PowerPC 405GP", tag, owner, clock, "ppc405gp", PPC_MODEL_405GP, PPCCAP_4XX | PPCCAP_VEA, 1) +{ +} /*********************************************************************/ -INLINE int IS_PPC602(void) +inline int ppc_device::IS_PPC602(void) { - return ppc.is602; + return m_is602; } -INLINE int IS_PPC603(void) +inline int ppc_device::IS_PPC603(void) { - return ppc.is603; + return m_is603; } -INLINE int IS_PPC403(void) +inline int ppc_device::IS_PPC403(void) { return !IS_PPC602() && !IS_PPC603(); } diff --git a/src/emu/cpu/powerpc/ppc.h b/src/emu/cpu/powerpc/ppc.h index 03fdca2ed5f..dbdf6131903 100644 --- a/src/emu/cpu/powerpc/ppc.h +++ b/src/emu/cpu/powerpc/ppc.h @@ -14,6 +14,11 @@ #ifndef __PPC_H__ #define __PPC_H__ +#include <setjmp.h> +#include "cpu/vtlb.h" +#include "cpu/drcfe.h" +#include "cpu/drcuml.h" +#include "cpu/drcumlsh.h" /*************************************************************************** @@ -162,10 +167,6 @@ enum typedef void (*ppc4xx_spu_tx_handler)(device_t *device, UINT8 data); -struct powerpc_config -{ - UINT32 bus_frequency; -}; typedef void (*ppc_dcstore_handler)(device_t *device, UINT32 address); typedef UINT32 (*ppc4xx_dma_read_handler)(device_t *device, int width); @@ -176,65 +177,643 @@ typedef void (*ppc4xx_dma_write_handler)(device_t *device, int width, UINT32 dat PUBLIC FUNCTIONS ***************************************************************************/ -void ppcdrc_set_options(device_t *device, UINT32 options); -void ppcdrc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base); -void ppcdrc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles); +#define MCFG_PPC_BUS_FREQUENCY(_frequency) \ + ppc_device::set_bus_frequency(*device, _frequency); + + +class ppc_frontend; + + +class ppc_device : public cpu_device +{ + friend class ppc_frontend; + +protected: + /* PowerPC flavors */ + enum powerpc_flavor + { + PPC_MODEL_403GA = 0x00200000, + PPC_MODEL_403GB = 0x00200100, + PPC_MODEL_403GC = 0x00200200, + PPC_MODEL_403GCX = 0x00201400, + PPC_MODEL_405GP = 0x40110000, + PPC_MODEL_601 = 0x00010000, + PPC_MODEL_603 = 0x00030000, /* "Wart" */ + PPC_MODEL_604 = 0x00040000, /* "Zephyr" */ + PPC_MODEL_602 = 0x00050200, /* "Galahad" */ + PPC_MODEL_603E = 0x00060103, /* "Stretch", version 1.3 */ + PPC_MODEL_603EV = 0x00070000, /* "Valiant" */ + PPC_MODEL_603R = 0x00071202, /* "Goldeneye", version 2.1 */ + PPC_MODEL_740 = 0x00080301, /* "Arthur", version 3.1 */ + PPC_MODEL_750 = PPC_MODEL_740, + PPC_MODEL_740P = 0x00080202, /* "Conan Doyle", version 1.2 */ + PPC_MODEL_750P = PPC_MODEL_740P, + PPC_MODEL_755 = 0x00083203, /* "Goldfinger", version 2.3 */ + PPC_MODEL_7400 = 0x000c0209, /* "Max", version 2.9 */ + PPC_MODEL_7410 = 0x800c1104, /* "Nitro", version 3.4 */ + PPC_MODEL_7450 = 0x80000201, /* "Vger", version 2.1 */ + PPC_MODEL_7451 = 0x80000203, /* "Vger", version 2.3 */ + PPC_MODEL_7441 = PPC_MODEL_7451, + PPC_MODEL_7455 = 0x80010303, /* "Apollo 6", version 3.3 */ + PPC_MODEL_7445 = PPC_MODEL_7455, + PPC_MODEL_7457 = 0x80020101, /* "Apollo 7", version 1.1 */ + PPC_MODEL_MPC8240 = 0x00810101, /* "Kahlua" */ + PPC_MODEL_MPC8241 = 0x80811014, /* "Kahlua Lt" */ + PPC_MODEL_MPC8245 = 0x80811014, /* "Kahlua II" */ + }; + +public: + // construction/destruction + ppc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int address_bits, int data_bits, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor, address_map_constructor internal_map); + + static void set_bus_frequency(device_t &device, UINT32 bus_frequency) { downcast<ppc_device &>(device).c_bus_frequency = bus_frequency; } + + void ppc_set_dcstore_callback(ppc_dcstore_handler handler); + + void ppcdrc_set_options(UINT32 options); + void ppcdrc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base); + void ppcdrc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles); + + TIMER_CALLBACK_MEMBER(decrementer_int_callback); + TIMER_CALLBACK_MEMBER(ppc4xx_buffered_dma_callback); + TIMER_CALLBACK_MEMBER(ppc4xx_fit_callback); + TIMER_CALLBACK_MEMBER(ppc4xx_pit_callback); + TIMER_CALLBACK_MEMBER(ppc4xx_spu_callback); + + void ppc_cfunc_printf_exception(); + void ppc_cfunc_printf_debug(); + void ppc_cfunc_printf_probe(); + void ppc_cfunc_unimplemented(); + void ppccom_tlb_fill(); + void ppccom_update_fprf(); + void ppccom_dcstore_callback(); + void ppccom_execute_tlbie(); + void ppccom_execute_tlbia(); + void ppccom_execute_tlbl(); + void ppccom_execute_mfspr(); + void ppccom_execute_mftb(); + void ppccom_execute_mtspr(); + void ppccom_tlb_flush(); + void ppccom_execute_mfdcr(); + void ppccom_execute_mtdcr(); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + virtual void device_stop(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 1; } + virtual UINT32 execute_max_cycles() const { return 40; } + virtual UINT32 execute_input_lines() const { return 1; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; } + virtual bool memory_translate(address_spacenum spacenum, int intention, offs_t &address); + + // device_state_interface overrides + virtual void state_export(const device_state_entry &entry); + virtual void state_import(const device_state_entry &entry); + virtual void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 4; } + virtual UINT32 disasm_max_opcode_bytes() const { return 4; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + + /* exception types */ + enum + { + EXCEPTION_RESET = 1, + EXCEPTION_MACHCHECK = 2, + EXCEPTION_DSI = 3, /* PPCCAP_OEA */ + EXCEPTION_PROTECTION = 3, /* PPCCAP_4XX */ + EXCEPTION_ISI = 4, + EXCEPTION_EI = 5, + EXCEPTION_ALIGN = 6, + EXCEPTION_PROGRAM = 7, + EXCEPTION_NOFPU = 8, + EXCEPTION_DECREMENT = 9, + EXCEPTION_SYSCALL = 12, + EXCEPTION_TRACE = 13, + EXCEPTION_FPASSIST = 14, + EXCEPTION_ITLBMISS = 16, /* PPCCAP_603_MMU */ + EXCEPTION_DTLBMISSL = 17, /* PPCCAP_603_MMU */ + EXCEPTION_DTLBMISSS = 18, /* PPCCAP_603_MMU */ + EXCEPTION_COUNT + }; + + address_space_config m_program_config; + address_space *m_program; + UINT32 c_bus_frequency; + + struct internal_ppc_state + { + UINT32 pc; + UINT32 r[32]; + double f[32]; + UINT32 cr[8]; + UINT32 fpscr; + UINT32 msr; + UINT32 xerso; + UINT32 sr[16]; + UINT32 spr[1024]; + int icount; + UINT32 mode; /* current global mode */ + UINT32 irq_pending; + /* parameters for calls */ + UINT32 param0; + UINT32 param1; + /* PowerPC 603-specific state */ + UINT32 mmu603_cmp; + UINT32 mmu603_hash[2]; + UINT32 mmu603_r[4]; + /* parameters for subroutines */ + UINT32 tempaddr; /* temporary address storage */ + drcuml_ireg tempdata; /* temporary data storage */ + UINT32 updateaddr; /* update address storage */ + UINT32 swcount; /* counter for sw instructions */ + const char * format; /* format string for printing */ + UINT32 arg0; /* print_debug argument 1 */ + double fp0; /* floating point 0 */ + }; + + internal_ppc_state *m_core; + + int m_ppc_tb_base_icount; + int m_ppc_dec_base_icount; + int m_ppc_dec_trigger_cycle; + int m_bus_freq_multiplier; + + UINT32 m_npc; + UINT32 m_dcr[256]; + + UINT32 m_lr; + UINT32 m_ctr; + UINT32 m_xer; + UINT32 m_pvr; + UINT32 m_srr0; + UINT32 m_srr1; + UINT32 m_srr2; + UINT32 m_srr3; + UINT32 m_hid0; + UINT32 m_hid1; + UINT32 m_hid2; + UINT32 m_sdr1; + UINT32 m_sprg[4]; + + UINT32 m_dsisr; + UINT32 m_dar; + UINT32 m_ear; + UINT32 m_dmiss; + UINT32 m_dcmp; + UINT32 m_hash1; + UINT32 m_hash2; + UINT32 m_imiss; + UINT32 m_icmp; + UINT32 m_rpa; + + struct BATENT { + UINT32 u; + UINT32 l; + }; + + BATENT m_ibat[4]; + BATENT m_dbat[4]; + + UINT32 m_evpr; + UINT32 m_exier; + UINT32 m_exisr; + UINT32 m_bear; + UINT32 m_besr; + UINT32 m_iocr; + UINT32 m_br[8]; + UINT32 m_iabr; + UINT32 m_esr; + UINT32 m_iccr; + UINT32 m_dccr; + UINT32 m_pit; + UINT32 m_pit_counter; + UINT32 m_pit_int_enable; + UINT32 m_tsr; + UINT32 m_dbsr; + UINT32 m_sgr; + UINT32 m_pid; + UINT32 m_pbl1; + UINT32 m_pbl2; + UINT32 m_pbu1; + UINT32 m_pbu2; + UINT32 m_fit_bit; + UINT32 m_fit_int_enable; + UINT32 m_wdt_bit; + UINT32 m_wdt_int_enable; + UINT32 m_dac1; + UINT32 m_dac2; + UINT32 m_iac1; + UINT32 m_iac2; + + struct SPU_REGS { + UINT8 spls; + UINT8 sphs; + UINT16 brd; + UINT8 spctl; + UINT8 sprc; + UINT8 sptc; + UINT8 sprb; + UINT8 sptb; + emu_timer *rx_timer; + emu_timer *tx_timer; + }; + + SPU_REGS m_spu_old; + + struct DMA_REGS { + UINT32 cr; + UINT32 da; + UINT32 sa; + UINT32 ct; + UINT32 cc; + }; + + DMA_REGS m_dma[4]; + UINT32 m_dmasr; + + int m_reserved; + UINT32 m_reserved_address; + + int m_interrupt_pending; + + UINT64 m_tb; /* 56-bit timebase register */ + + // STUFF added for the 6xx series + UINT32 m_dec, m_dec_frac; + + union FPR { + UINT64 id; + double fd; + }; + + union FPR32 { + UINT32 i; + float f; + }; + + FPR m_fpr[32]; + + int m_is603; + int m_is602; + + /* PowerPC 602 specific registers */ + UINT32 m_lt; + UINT32 m_sp; + UINT32 m_tcr; + UINT32 m_ibr; + UINT32 m_esasrr; + UINT32 m_sebr; + UINT32 m_ser; + + /* MMU */ + vtlb_state *m_vtlb; + + /* architectural distinctions */ + powerpc_flavor m_flavor; + UINT32 m_cap; + UINT8 m_cache_line_size; + UINT32 m_tb_divisor; + + /* PowerPC 4xx-specific state */ + /* PowerPC 4XX-specific serial port state */ + struct ppc4xx_spu_state + { + UINT8 regs[9]; + UINT8 txbuf; + UINT8 rxbuf; + emu_timer * timer; + UINT8 rxbuffer[256]; + UINT32 rxin, rxout; + ppc4xx_spu_tx_handler tx_handler; + }; + + ppc4xx_spu_state m_spu; + emu_timer * m_fit_timer; + emu_timer * m_pit_timer; + emu_timer * m_wdog_timer; + UINT32 m_pit_reload; + UINT32 m_irqstate; + emu_timer * m_buffered_dma_timer[4]; + int m_buffered_dma_rate[4]; + + /* internal stuff */ + direct_read_data *m_direct; + offs_t m_codexor; + UINT32 m_system_clock; + UINT32 m_cpu_clock; + UINT64 m_tb_zero_cycles; + UINT64 m_dec_zero_cycles; + emu_timer * m_decrementer_int_timer; + + read32_delegate m_dcr_read_func; + write32_delegate m_dcr_write_func; + + ppc_dcstore_handler m_dcstore_handler; + + ppc4xx_dma_read_handler m_ext_dma_read_handler[4]; + ppc4xx_dma_write_handler m_ext_dma_write_handler[4]; + + /* PowerPC function pointers for memory accesses/exceptions */ + jmp_buf m_exception_jmpbuf; + UINT8 (*m_ppcread8)(address_space &space, offs_t address); + UINT16 (*m_ppcread16)(address_space &space, offs_t address); + UINT32 (*m_ppcread32)(address_space &space, offs_t address); + UINT64 (*m_ppcread64)(address_space &space, offs_t address); + void (*m_ppcwrite8)(address_space &space, offs_t address, UINT8 data); + void (*m_ppcwrite16)(address_space &space, offs_t address, UINT16 data); + void (*m_ppcwrite32)(address_space &space, offs_t address, UINT32 data); + void (*m_ppcwrite64)(address_space &space, offs_t address, UINT64 data); + UINT16 (*m_ppcread16_unaligned)(address_space &space, offs_t address); + UINT32 (*m_ppcread32_unaligned)(address_space &space, offs_t address); + UINT64 (*m_ppcread64_unaligned)(address_space &space, offs_t address); + void (*m_ppcwrite16_unaligned)(address_space &space, offs_t address, UINT16 data); + void (*m_ppcwrite32_unaligned)(address_space &space, offs_t address, UINT32 data); + void (*m_ppcwrite64_unaligned)(address_space &space, offs_t address, UINT64 data); + + void (*m_optable19[1024])(UINT32); + void (*m_optable31[1024])(UINT32); + void (*m_optable59[1024])(UINT32); + void (*m_optable63[1024])(UINT32); + void (*m_optable[64])(UINT32); + + /* core state */ + drc_cache m_cache; /* pointer to the DRC code cache */ + drcuml_state * m_drcuml; /* DRC UML generator state */ + ppc_frontend * m_drcfe; /* pointer to the DRC front-end state */ + UINT32 m_drcoptions; /* configurable DRC options */ + + /* parameters for subroutines */ + UINT32 m_arg1; /* print_debug argument 2 */ + + /* tables */ + UINT8 m_fpmode[4]; /* FPU mode table */ + UINT8 m_sz_cr_table[32]; /* SZ CR table */ + UINT8 m_cmp_cr_table[32]; /* CMP CR table */ + UINT8 m_cmpl_cr_table[32]; /* CMPL CR table */ + UINT8 m_fcmp_cr_table[32]; /* FCMP CR table */ + + /* internal stuff */ + UINT8 m_cache_dirty; /* true if we need to flush the cache */ + + /* register mappings */ + uml::parameter m_regmap[32]; /* parameter to register mappings for all 32 integer registers */ + uml::parameter m_fdregmap[32]; /* parameter to register mappings for all 32 floating point registers */ + + /* subroutines */ + uml::code_handle * m_entry; /* entry point */ + uml::code_handle * m_nocode; /* nocode exception handler */ + uml::code_handle * m_out_of_cycles; /* out of cycles exception handler */ + uml::code_handle * m_tlb_mismatch; /* tlb mismatch handler */ + uml::code_handle * m_swap_tgpr; /* swap TGPR handler */ + uml::code_handle * m_lsw[8][32]; /* lsw entries */ + uml::code_handle * m_stsw[8][32]; /* stsw entries */ + uml::code_handle * m_read8[8]; /* read byte */ + uml::code_handle * m_write8[8]; /* write byte */ + uml::code_handle * m_read16[8]; /* read half */ + uml::code_handle * m_read16mask[8]; /* read half */ + uml::code_handle * m_write16[8]; /* write half */ + uml::code_handle * m_write16mask[8]; /* write half */ + uml::code_handle * m_read32[8]; /* read word */ + uml::code_handle * m_read32align[8]; /* read word aligned */ + uml::code_handle * m_read32mask[8]; /* read word */ + uml::code_handle * m_write32[8]; /* write word */ + uml::code_handle * m_write32align[8]; /* write word aligned */ + uml::code_handle * m_write32mask[8]; /* write word */ + uml::code_handle * m_read64[8]; /* read double */ + uml::code_handle * m_read64mask[8]; /* read double */ + uml::code_handle * m_write64[8]; /* write double */ + uml::code_handle * m_write64mask[8]; /* write double */ + uml::code_handle * m_exception[EXCEPTION_COUNT]; /* array of exception handlers */ + uml::code_handle * m_exception_norecover[EXCEPTION_COUNT]; /* array of exception handlers */ + + /* fast RAM */ + /* fast RAM info */ + struct fast_ram_info + { + offs_t start; /* start of the RAM block */ + offs_t end; /* end of the RAM block */ + UINT8 readonly; /* TRUE if read-only */ + void * base; /* base in memory where the RAM lives */ + }; + + UINT32 m_fastram_select; + fast_ram_info m_fastram[PPC_MAX_FASTRAM]; + + /* hotspots */ + /* hotspot info */ + struct hotspot_info + { + offs_t pc; /* PC to consider */ + UINT32 opcode; /* required opcode at that PC */ + UINT32 cycles; /* number of cycles to eat when hit */ + }; + UINT32 m_hotspot_select; + hotspot_info m_hotspot[PPC_MAX_HOTSPOTS]; + + UINT64 m_debugger_temp; + + /* internal compiler state */ + struct compiler_state + { + UINT32 cycles; /* accumulated cycles */ + UINT8 checkints; /* need to check interrupts before next instruction */ + UINT8 checksoftints; /* need to check software interrupts before next instruction */ + uml::code_label labelnum; /* index for local labels */ + }; + + int IS_PPC602(void); + int IS_PPC603(void); + int IS_PPC403(void); + UINT32 get_cr(); + void set_cr(UINT32 value); + UINT32 get_xer(); + void set_xer(UINT32 value); + UINT64 get_timebase(); + void set_timebase(UINT64 newtb); + UINT32 get_decrementer(); + void set_decrementer(UINT32 newdec); + UINT32 ppccom_translate_address_internal(int intention, offs_t &address); + void ppc4xx_set_irq_line(UINT32 bitmask, int state); + int ppc4xx_get_irq_line(UINT32 bitmask); + void ppc4xx_dma_update_irq_states(); + int ppc4xx_dma_decrement_count(int dmachan); + int ppc4xx_dma_fetch_transmit_byte(int dmachan, UINT8 *byte); + int ppc4xx_dma_handle_receive_byte(int dmachan, UINT8 byte); + void ppc4xx_dma_exec(int dmachan); + void ppc4xx_spu_update_irq_states(); + void ppc4xx_spu_rx_data(UINT8 data); + void ppc4xx_spu_timer_reset(); + void alloc_handle(drcuml_state *drcuml, uml::code_handle **handleptr, const char *name); + void load_fast_iregs(drcuml_block *block); + void save_fast_iregs(drcuml_block *block); + UINT32 compute_rlw_mask(UINT8 mb, UINT8 me); + UINT32 compute_crf_mask(UINT8 crm); + UINT32 compute_spr(UINT32 spr); + void code_flush_cache(); + void code_compile_block(UINT8 mode, offs_t pc); + void static_generate_entry_point(); + void static_generate_nocode_handler(); + void static_generate_out_of_cycles(); + void static_generate_tlb_mismatch(); + void static_generate_exception(UINT8 exception, int recover, const char *name); + void static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, uml::code_handle *&handleptr, uml::code_handle *masked); + void static_generate_swap_tgpr(); + void static_generate_lsw_entries(int mode); + void static_generate_stsw_entries(int mode); + void generate_update_mode(drcuml_block *block); + void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception); + void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast); + void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + void generate_compute_flags(drcuml_block *block, const opcode_desc *desc, int updatecr, UINT32 xermask, int invertcarry); + void generate_shift_flags(drcuml_block *block, const opcode_desc *desc, UINT32 op); + void generate_fp_flags(drcuml_block *block, const opcode_desc *desc, int updatefprf); + void generate_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int source, UINT8 link); + void generate_branch_bo(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 bo, UINT32 bi, int source, int link); + int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + int generate_instruction_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + int generate_instruction_1f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + int generate_instruction_3b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + int generate_instruction_3f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op); + const char *log_desc_flags_to_string(UINT32 flags); + void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist); + void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent); + +}; + + +//class ppc403_device : public ppc_device +//{ +//public: +// ppc403_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +// +//protected: +// virtual UINT32 execute_input_lines() const { return 8; } +//}; +// +// +//class ppc405_device : public ppc_device +//{ +//public: +// ppc405_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +// +//protected: +// virtual UINT32 execute_input_lines() const { return 8; } +//}; + + +class ppc603_device : public ppc_device +{ +public: + ppc603_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + +class ppc603e_device : public ppc_device +{ +public: + ppc603e_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + +class ppc603r_device : public ppc_device +{ +public: + ppc603r_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + +class ppc602_device : public ppc_device +{ +public: + ppc602_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + -void ppc4xx_spu_set_tx_handler(device_t *device, ppc4xx_spu_tx_handler handler); -void ppc4xx_spu_receive_byte(device_t *device, UINT8 byteval); +class mpc8240_device : public ppc_device +{ +public: + mpc8240_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; -void ppc_set_dcstore_callback(device_t *device, ppc_dcstore_handler handler); -void ppc4xx_set_dma_read_handler(device_t *device, int channel, ppc4xx_dma_read_handler handler, int rate); -void ppc4xx_set_dma_write_handler(device_t *device, int channel, ppc4xx_dma_write_handler handler, int rate); -void ppc4xx_set_dcr_read_handler(device_t *device, read32_delegate dcr_read_func); -void ppc4xx_set_dcr_write_handler(device_t *device, write32_delegate dcr_write_func); -class ppc4xx_device : public legacy_cpu_device +class ppc601_device : public ppc_device { public: - ppc4xx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info); + ppc601_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + +class ppc604_device : public ppc_device +{ +public: + ppc604_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + +class ppc4xx_device : public ppc_device +{ +public: + ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor); + + void ppc4xx_spu_set_tx_handler(ppc4xx_spu_tx_handler handler); + void ppc4xx_spu_receive_byte(UINT8 byteval); + + void ppc4xx_set_dma_read_handler(int channel, ppc4xx_dma_read_handler handler, int rate); + void ppc4xx_set_dma_write_handler(int channel, ppc4xx_dma_write_handler handler, int rate); + void ppc4xx_set_dcr_read_handler(read32_delegate dcr_read_func); + void ppc4xx_set_dcr_write_handler(write32_delegate dcr_write_func); + DECLARE_READ8_MEMBER( ppc4xx_spu_r ); DECLARE_WRITE8_MEMBER( ppc4xx_spu_w ); + +protected: + virtual UINT32 execute_input_lines() const { return 5; } + virtual void execute_set_input(int inputnum, int state); }; -CPU_GET_INFO( ppc403ga ); class ppc403ga_device : public ppc4xx_device { public: - ppc403ga_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock); + ppc403ga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); }; -extern const device_type PPC403GA; - -CPU_GET_INFO( ppc403gcx ); class ppc403gcx_device : public ppc4xx_device { public: - ppc403gcx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock); + ppc403gcx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); }; -extern const device_type PPC403GCX; - - -CPU_GET_INFO( ppc405gp ); class ppc405gp_device : public ppc4xx_device { public: - ppc405gp_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock); + ppc405gp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); }; -extern const device_type PPC405GP; -DECLARE_LEGACY_CPU_DEVICE(PPC601, ppc601); -DECLARE_LEGACY_CPU_DEVICE(PPC602, ppc602); -DECLARE_LEGACY_CPU_DEVICE(PPC603, ppc603); -DECLARE_LEGACY_CPU_DEVICE(PPC603E, ppc603e); -DECLARE_LEGACY_CPU_DEVICE(PPC603R, ppc603r); -DECLARE_LEGACY_CPU_DEVICE(PPC604, ppc604); -DECLARE_LEGACY_CPU_DEVICE(MPC8240, mpc8240); +extern const device_type PPC601; +extern const device_type PPC602; +extern const device_type PPC603; +extern const device_type PPC603E; +extern const device_type PPC603R; +extern const device_type PPC604; +extern const device_type MPC8240; +extern const device_type PPC403GA; +extern const device_type PPC403GCX; +extern const device_type PPC405GP; #endif /* __PPC_H__ */ diff --git a/src/emu/cpu/powerpc/ppccom.c b/src/emu/cpu/powerpc/ppccom.c index 790b8b7d571..263b9618ad2 100644 --- a/src/emu/cpu/powerpc/ppccom.c +++ b/src/emu/cpu/powerpc/ppccom.c @@ -10,6 +10,7 @@ #include "emu.h" #include "ppccom.h" +#include "ppcfe.h" /*************************************************************************** @@ -33,26 +34,269 @@ /*************************************************************************** - FUNCTION PROTOTYPES + PRIVATE GLOBAL VARIABLES ***************************************************************************/ -static TIMER_CALLBACK( ppc4xx_fit_callback ); -static TIMER_CALLBACK( ppc4xx_pit_callback ); -static TIMER_CALLBACK( ppc4xx_spu_callback ); -static TIMER_CALLBACK( decrementer_int_callback ); +/* lookup table for FP modes */ +static const UINT8 fpmode_source[4] = +{ + uml::ROUND_ROUND, + uml::ROUND_TRUNC, + uml::ROUND_CEIL, + uml::ROUND_FLOOR +}; + +/* flag lookup table for SZ */ +static const UINT8 sz_cr_table_source[32] = +{ + /* ..... */ 0x4, + /* ....C */ 0x4, + /* ...V. */ 0x4, + /* ...VC */ 0x4, + /* ..Z.. */ 0x2, + /* ..Z.C */ 0x2, + /* ..ZV. */ 0x2, + /* ..ZVC */ 0x2, + /* .S... */ 0x8, + /* .S..C */ 0x8, + /* .S.V. */ 0x8, + /* .S.VC */ 0x8, + /* .SZ.. */ 0x2, + /* .SZ.C */ 0x2, + /* .SZV. */ 0x2, + /* .SZVC */ 0x2, + /* U.... */ 0x4, + /* U...C */ 0x4, + /* U..V. */ 0x4, + /* U..VC */ 0x4, + /* U.Z.. */ 0x2, + /* U.Z.C */ 0x2, + /* U.ZV. */ 0x2, + /* U.ZVC */ 0x2, + /* US... */ 0x8, + /* US..C */ 0x8, + /* US.V. */ 0x8, + /* US.VC */ 0x8, + /* USZ.. */ 0x2, + /* USZ.C */ 0x2, + /* USZV. */ 0x2, + /* USZVC */ 0x2 +}; + +/* flag lookup table for CMP */ +static const UINT8 cmp_cr_table_source[32] = +{ + /* ..... */ 0x4, + /* ....C */ 0x4, + /* ...V. */ 0x8, + /* ...VC */ 0x8, + /* ..Z.. */ 0x2, + /* ..Z.C */ 0x2, + /* ..ZV. */ 0x2, + /* ..ZVC */ 0x2, + /* .S... */ 0x8, + /* .S..C */ 0x8, + /* .S.V. */ 0x4, + /* .S.VC */ 0x4, + /* .SZ.. */ 0x2, + /* .SZ.C */ 0x2, + /* .SZV. */ 0x2, + /* .SZVC */ 0x2, + /* U.... */ 0x4, + /* U...C */ 0x4, + /* U..V. */ 0x8, + /* U..VC */ 0x8, + /* U.Z.. */ 0x2, + /* U.Z.C */ 0x2, + /* U.ZV. */ 0x2, + /* U.ZVC */ 0x2, + /* US... */ 0x8, + /* US..C */ 0x8, + /* US.V. */ 0x4, + /* US.VC */ 0x4, + /* USZ.. */ 0x2, + /* USZ.C */ 0x2, + /* USZV. */ 0x2, + /* USZVC */ 0x2 +}; + +/* flag lookup table for CMPL */ +static const UINT8 cmpl_cr_table_source[32] = +{ + /* ..... */ 0x4, + /* ....C */ 0x8, + /* ...V. */ 0x4, + /* ...VC */ 0x8, + /* ..Z.. */ 0x2, + /* ..Z.C */ 0x2, + /* ..ZV. */ 0x2, + /* ..ZVC */ 0x2, + /* .S... */ 0x4, + /* .S..C */ 0x8, + /* .S.V. */ 0x4, + /* .S.VC */ 0x8, + /* .SZ.. */ 0x2, + /* .SZ.C */ 0x2, + /* .SZV. */ 0x2, + /* .SZVC */ 0x2, + /* U.... */ 0x4, + /* U...C */ 0x8, + /* U..V. */ 0x4, + /* U..VC */ 0x8, + /* U.Z.. */ 0x2, + /* U.Z.C */ 0x2, + /* U.ZV. */ 0x2, + /* U.ZVC */ 0x2, + /* US... */ 0x4, + /* US..C */ 0x8, + /* US.V. */ 0x4, + /* US.VC */ 0x8, + /* USZ.. */ 0x2, + /* USZ.C */ 0x2, + /* USZV. */ 0x2, + /* USZVC */ 0x2 +}; + +/* flag lookup table for FCMP */ +static const UINT8 fcmp_cr_table_source[32] = +{ + /* ..... */ 0x4, + /* ....C */ 0x8, + /* ...V. */ 0x4, + /* ...VC */ 0x8, + /* ..Z.. */ 0x2, + /* ..Z.C */ 0xa, + /* ..ZV. */ 0x2, + /* ..ZVC */ 0xa, + /* .S... */ 0x4, + /* .S..C */ 0x8, + /* .S.V. */ 0x4, + /* .S.VC */ 0x8, + /* .SZ.. */ 0x2, + /* .SZ.C */ 0xa, + /* .SZV. */ 0x2, + /* .SZVC */ 0xa, + /* U.... */ 0x5, + /* U...C */ 0x9, + /* U..V. */ 0x5, + /* U..VC */ 0x9, + /* U.Z.. */ 0x3, + /* U.Z.C */ 0xb, + /* U.ZV. */ 0x3, + /* U.ZVC */ 0xb, + /* US... */ 0x5, + /* US..C */ 0x9, + /* US.V. */ 0x5, + /* US.VC */ 0x9, + /* USZ.. */ 0x3, + /* USZ.C */ 0xb, + /* USZV. */ 0x3, + /* USZVC */ 0xb +}; + + +const device_type PPC601 = &device_creator<ppc601_device>; +const device_type PPC602 = &device_creator<ppc602_device>; +const device_type PPC603 = &device_creator<ppc603_device>; +const device_type PPC603E = &device_creator<ppc603e_device>; +const device_type PPC603R = &device_creator<ppc603r_device>; +const device_type PPC604 = &device_creator<ppc604_device>; +const device_type MPC8240 = &device_creator<mpc8240_device>; +const device_type PPC403GA = &device_creator<ppc403ga_device>; +const device_type PPC403GCX = &device_creator<ppc403gcx_device>; +const device_type PPC405GP = &device_creator<ppc405gp_device>; + + +ppc_device::ppc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int address_bits, int data_bits, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor, address_map_constructor internal_map) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__) + , m_program_config("program", ENDIANNESS_BIG, data_bits, address_bits, 0, internal_map) + , c_bus_frequency(0) + , m_core(NULL) + , m_bus_freq_multiplier(1) + , m_vtlb(NULL) + , m_flavor(flavor) + , m_cap(cap) + , m_tb_divisor(tb_divisor) + , m_dcstore_handler(NULL) + , m_cache(CACHE_SIZE + sizeof(internal_ppc_state)) + , m_drcuml(NULL) + , m_drcfe(NULL) + , m_drcoptions(0) +{ + m_program_config.m_logaddr_width = 32; + m_program_config.m_page_shift = POWERPC_MIN_PAGE_SHIFT; + memset(m_ext_dma_read_handler, 0, sizeof(m_ext_dma_read_handler)); + memset(m_ext_dma_write_handler, 0, sizeof(m_ext_dma_write_handler)); +} -static TIMER_CALLBACK( ppc4xx_buffered_dma_callback ); +//ppc403_device::ppc403_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) +// : ppc_device(mconfig, PPC403, "PPC403", tag, owner, clock, "ppc403", 32?, 64?) +//{ +//} +// +//ppc405_device::ppc405_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) +// : ppc_device(mconfig, PPC405, "PPC405", tag, owner, clock, "ppc405", 32?, 64?) +//{ +//} + +ppc603_device::ppc603_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC603, "PowerPC 603", tag, owner, clock, "ppc603", 32, 64, PPC_MODEL_603, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, NULL) +{ +} -static void ppc4xx_set_irq_line(powerpc_state *ppc, UINT32 bitmask, int state); +ppc603e_device::ppc603e_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC603E, "PowerPC 603e", tag, owner, clock, "ppc603e", 32, 64, PPC_MODEL_603E, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, NULL) +{ +} -static void ppc4xx_dma_update_irq_states(powerpc_state *ppc); -static int ppc4xx_dma_fetch_transmit_byte(powerpc_state *ppc, int dmachan, UINT8 *byte); -static int ppc4xx_dma_handle_receive_byte(powerpc_state *ppc, int dmachan, UINT8 byte); -static void ppc4xx_dma_exec(powerpc_state *ppc, int dmachan); +ppc603r_device::ppc603r_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC603R, "PowerPC 603R", tag, owner, clock, "ppc603r", 32, 64, PPC_MODEL_603R, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, NULL) +{ +} -static void ppc4xx_spu_update_irq_states(powerpc_state *ppc); -static void ppc4xx_spu_timer_reset(powerpc_state *ppc); +ppc602_device::ppc602_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC602, "PowerPC 602", tag, owner, clock, "ppc602", 32, 64, PPC_MODEL_602, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, NULL) +{ +} +mpc8240_device::mpc8240_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, MPC8240, "PowerPC MPC8240", tag, owner, clock, "mpc8240", 32, 64, PPC_MODEL_MPC8240, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4/* unknown */, NULL) +{ +} + +ppc601_device::ppc601_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC601, "PowerPC 601", tag, owner, clock, "ppc601", 32, 64, PPC_MODEL_601, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_MFIOC | PPCCAP_601BAT, 0/* no TB */, NULL) +{ +} + +ppc604_device::ppc604_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc_device(mconfig, PPC604, "PowerPC 604", tag, owner, clock, "ppc604", 32, 64, PPC_MODEL_604, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_604_MMU, 4, NULL) +{ +} + +static ADDRESS_MAP_START( internal_ppc4xx, AS_PROGRAM, 32, ppc4xx_device ) + AM_RANGE(0x40000000, 0x4000000f) AM_READWRITE8(ppc4xx_spu_r, ppc4xx_spu_w, 0xffffffff) +ADDRESS_MAP_END + +ppc4xx_device::ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor) + : ppc_device(mconfig, type, name, tag, owner, clock, shortname, 31, 32, flavor, cap, tb_divisor, ADDRESS_MAP_NAME(internal_ppc4xx)) +{ +} + +ppc403ga_device::ppc403ga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc4xx_device(mconfig, PPC403GA, "PowerPC 403GA", tag, owner, clock, "ppc403ga", PPC_MODEL_403GA, PPCCAP_4XX, 1) +{ +} + +ppc403gcx_device::ppc403gcx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc4xx_device(mconfig, PPC403GCX, "PowerPC 403GCX", tag, owner, clock, "ppc403gcx", PPC_MODEL_403GCX, PPCCAP_4XX, 1) +{ +} + +ppc405gp_device::ppc405gp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : ppc4xx_device(mconfig, PPC405GP, "PowerPC 405GP", tag, owner, clock, "ppc405gp", PPC_MODEL_405GP, PPCCAP_4XX | PPCCAP_VEA, 1) +{ +} /*************************************************************************** @@ -78,16 +322,16 @@ INLINE int page_access_allowed(int transtype, UINT8 key, UINT8 protbits) get_cr - return the current CR value -------------------------------------------------*/ -INLINE UINT32 get_cr(powerpc_state *ppc) +inline UINT32 ppc_device::get_cr() { - return ((ppc->cr[0] & 0x0f) << 28) | - ((ppc->cr[1] & 0x0f) << 24) | - ((ppc->cr[2] & 0x0f) << 20) | - ((ppc->cr[3] & 0x0f) << 16) | - ((ppc->cr[4] & 0x0f) << 12) | - ((ppc->cr[5] & 0x0f) << 8) | - ((ppc->cr[6] & 0x0f) << 4) | - ((ppc->cr[7] & 0x0f) << 0); + return ((m_core->cr[0] & 0x0f) << 28) | + ((m_core->cr[1] & 0x0f) << 24) | + ((m_core->cr[2] & 0x0f) << 20) | + ((m_core->cr[3] & 0x0f) << 16) | + ((m_core->cr[4] & 0x0f) << 12) | + ((m_core->cr[5] & 0x0f) << 8) | + ((m_core->cr[6] & 0x0f) << 4) | + ((m_core->cr[7] & 0x0f) << 0); } @@ -95,16 +339,16 @@ INLINE UINT32 get_cr(powerpc_state *ppc) set_cr - set the current CR value -------------------------------------------------*/ -INLINE void set_cr(powerpc_state *ppc, UINT32 value) +inline void ppc_device::set_cr(UINT32 value) { - ppc->cr[0] = value >> 28; - ppc->cr[1] = value >> 24; - ppc->cr[2] = value >> 20; - ppc->cr[3] = value >> 16; - ppc->cr[4] = value >> 12; - ppc->cr[5] = value >> 8; - ppc->cr[6] = value >> 4; - ppc->cr[7] = value >> 0; + m_core->cr[0] = value >> 28; + m_core->cr[1] = value >> 24; + m_core->cr[2] = value >> 20; + m_core->cr[3] = value >> 16; + m_core->cr[4] = value >> 12; + m_core->cr[5] = value >> 8; + m_core->cr[6] = value >> 4; + m_core->cr[7] = value >> 0; } @@ -112,9 +356,9 @@ INLINE void set_cr(powerpc_state *ppc, UINT32 value) get_xer - return the current XER value -------------------------------------------------*/ -INLINE UINT32 get_xer(powerpc_state *ppc) +inline UINT32 ppc_device::get_xer() { - return ppc->spr[SPR_XER] | (ppc->xerso << 31); + return m_core->spr[SPR_XER] | (m_core->xerso << 31); } @@ -122,10 +366,10 @@ INLINE UINT32 get_xer(powerpc_state *ppc) set_xer - set the current XER value -------------------------------------------------*/ -INLINE void set_xer(powerpc_state *ppc, UINT32 value) +inline void ppc_device::set_xer(UINT32 value) { - ppc->spr[SPR_XER] = value & ~XER_SO; - ppc->xerso = value >> 31; + m_core->spr[SPR_XER] = value & ~XER_SO; + m_core->xerso = value >> 31; } @@ -134,14 +378,14 @@ INLINE void set_xer(powerpc_state *ppc, UINT32 value) value -------------------------------------------------*/ -INLINE UINT64 get_timebase(powerpc_state *ppc) +inline UINT64 ppc_device::get_timebase() { - if (!ppc->tb_divisor) + if (!m_tb_divisor) { - return (ppc->device->total_cycles() - ppc->tb_zero_cycles); + return (total_cycles() - m_tb_zero_cycles); } - return (ppc->device->total_cycles() - ppc->tb_zero_cycles) / ppc->tb_divisor; + return (total_cycles() - m_tb_zero_cycles) / m_tb_divisor; } @@ -149,9 +393,9 @@ INLINE UINT64 get_timebase(powerpc_state *ppc) set_timebase - set the timebase -------------------------------------------------*/ -INLINE void set_timebase(powerpc_state *ppc, UINT64 newtb) +inline void ppc_device::set_timebase(UINT64 newtb) { - ppc->tb_zero_cycles = ppc->device->total_cycles() - newtb * ppc->tb_divisor; + m_tb_zero_cycles = total_cycles() - newtb * m_tb_divisor; } @@ -160,17 +404,17 @@ INLINE void set_timebase(powerpc_state *ppc, UINT64 newtb) decrementer value -------------------------------------------------*/ -INLINE UINT32 get_decrementer(powerpc_state *ppc) +inline UINT32 ppc_device::get_decrementer() { - INT64 cycles_until_zero = ppc->dec_zero_cycles - ppc->device->total_cycles(); + INT64 cycles_until_zero = m_dec_zero_cycles - total_cycles(); cycles_until_zero = MAX(cycles_until_zero, 0); - if (!ppc->tb_divisor) + if (!m_tb_divisor) { return 0; } - return cycles_until_zero / ppc->tb_divisor; + return cycles_until_zero / m_tb_divisor; } @@ -178,29 +422,29 @@ INLINE UINT32 get_decrementer(powerpc_state *ppc) set_decrementer - set the decremeter -------------------------------------------------*/ -INLINE void set_decrementer(powerpc_state *ppc, UINT32 newdec) +inline void ppc_device::set_decrementer(UINT32 newdec) { - UINT64 cycles_until_done = ((UINT64)newdec + 1) * ppc->tb_divisor; - UINT32 curdec = get_decrementer(ppc); + UINT64 cycles_until_done = ((UINT64)newdec + 1) * m_tb_divisor; + UINT32 curdec = get_decrementer(); - if (!ppc->tb_divisor) + if (!m_tb_divisor) { return; } if (PRINTF_DECREMENTER) { - UINT64 total = ppc->device->total_cycles(); + UINT64 total = total_cycles(); osd_printf_debug("set_decrementer: olddec=%08X newdec=%08X divisor=%d totalcyc=%08X%08X timer=%08X%08X\n", - curdec, newdec, ppc->tb_divisor, + curdec, newdec, m_tb_divisor, (UINT32)(total >> 32), (UINT32)total, (UINT32)(cycles_until_done >> 32), (UINT32)cycles_until_done); } - ppc->dec_zero_cycles = ppc->device->total_cycles() + cycles_until_done; - ppc->decrementer_int_timer->adjust(ppc->device->cycles_to_attotime(cycles_until_done)); + m_dec_zero_cycles = total_cycles() + cycles_until_done; + m_decrementer_int_timer->adjust(cycles_to_attotime(cycles_until_done)); if ((INT32)curdec >= 0 && (INT32)newdec < 0) - ppc->irq_pending |= 0x02; + m_core->irq_pending |= 0x02; } @@ -306,93 +550,600 @@ INLINE int sign_double(double x) ***************************************************************************/ /*------------------------------------------------- - ppccom_init - initialize the powerpc_state + device_start - initialize the powerpc_state structure based on the configured type -------------------------------------------------*/ -void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT32 cap, int tb_divisor, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback) +void ppc_device::device_start() { - const powerpc_config *config = (const powerpc_config *)device->static_config(); + /* allocate the core from the near cache */ + m_core = (internal_ppc_state *)m_cache.alloc_near(sizeof(internal_ppc_state)); + memset(m_core, 0, sizeof(internal_ppc_state)); + + m_entry = NULL; + m_nocode = NULL; + m_out_of_cycles = NULL; + m_tlb_mismatch = NULL; + m_swap_tgpr = NULL; + memset(m_lsw, 0, sizeof(m_lsw)); + memset(m_stsw, 0, sizeof(m_stsw)); + memset(m_read8, 0, sizeof(m_read8)); + memset(m_write8, 0, sizeof(m_write8)); + memset(m_read16, 0, sizeof(m_read16)); + memset(m_read16mask, 0, sizeof(m_read16mask)); + memset(m_write16, 0, sizeof(m_write16)); + memset(m_write16mask, 0, sizeof(m_write16mask)); + memset(m_read32, 0, sizeof(m_read32)); + memset(m_read32align, 0, sizeof(m_read32align)); + memset(m_read32mask, 0, sizeof(m_read32mask)); + memset(m_write32, 0, sizeof(m_write32)); + memset(m_write32align, 0, sizeof(m_write32align)); + memset(m_write32mask, 0, sizeof(m_write32mask)); + memset(m_read64, 0, sizeof(m_read64)); + memset(m_read64mask, 0, sizeof(m_read64mask)); + memset(m_write64, 0, sizeof(m_write64)); + memset(m_write64mask, 0, sizeof(m_write64mask)); + memset(m_exception, 0, sizeof(m_exception)); + memset(m_exception_norecover, 0, sizeof(m_exception_norecover)); + + /* initialize the implementation state tables */ + memcpy(m_fpmode, fpmode_source, sizeof(fpmode_source)); + memcpy(m_sz_cr_table, sz_cr_table_source, sizeof(sz_cr_table_source)); + memcpy(m_cmp_cr_table, cmp_cr_table_source, sizeof(cmp_cr_table_source)); + memcpy(m_cmpl_cr_table, cmpl_cr_table_source, sizeof(cmpl_cr_table_source)); + memcpy(m_fcmp_cr_table, fcmp_cr_table_source, sizeof(fcmp_cr_table_source)); /* initialize based on the config */ - memset(ppc, 0, sizeof(*ppc)); - ppc->flavor = flavor; - ppc->cap = cap; - ppc->cache_line_size = 32; - ppc->tb_divisor = tb_divisor; - ppc->cpu_clock = device->clock(); - ppc->irq_callback = irqcallback; - ppc->device = device; - ppc->program = &device->space(AS_PROGRAM); - ppc->direct = &ppc->program->direct(); - ppc->system_clock = (config != NULL) ? config->bus_frequency : device->clock(); - ppc->dcr_read_func = read32_delegate(); - ppc->dcr_write_func = write32_delegate(); - - ppc->tb_divisor = (ppc->tb_divisor * device->clock() + ppc->system_clock / 2 - 1) / ppc->system_clock; - ppc->codexor = 0; - if (!(cap & PPCCAP_4XX) && device->space_config()->m_endianness != ENDIANNESS_NATIVE) - ppc->codexor = 4; + m_ppc_tb_base_icount = 0; + m_ppc_dec_base_icount = 0; + m_ppc_dec_trigger_cycle = 0; + m_bus_freq_multiplier = 0; + + m_npc = 0; + memset(m_dcr, 0, sizeof(m_dcr)); + + m_lr = 0; + m_ctr = 0; + m_xer = 0; + m_pvr = 0; + m_srr0 = 0; + m_srr1 = 0; + m_srr2 = 0; + m_srr3 = 0; + m_hid0 = 0; + m_hid1 = 0; + m_hid2 = 0; + m_sdr1 = 0; + memset(m_sprg, 0, sizeof(m_sprg)); + + m_dsisr = 0; + m_dar = 0; + m_ear = 0; + m_dmiss = 0; + m_dcmp = 0; + m_hash1 = 0; + m_hash2 = 0; + m_imiss = 0; + m_icmp = 0; + m_rpa = 0; + + memset(m_ibat, 0, sizeof(m_ibat)); + memset(m_dbat, 0, sizeof(m_dbat)); + + m_evpr = 0; + m_exier = 0; + m_exisr = 0; + m_bear = 0; + m_besr = 0; + m_iocr = 0; + memset(m_br, 0, sizeof(m_br)); + m_iabr = 0; + m_esr = 0; + m_iccr = 0; + m_dccr = 0; + m_pit = 0; + m_pit_counter = 0; + m_pit_int_enable = 0; + m_tsr = 0; + m_dbsr = 0; + m_sgr = 0; + m_pid = 0; + m_pbl1 = 0; + m_pbl2 = 0; + m_pbu1 = 0; + m_pbu2 = 0; + m_fit_bit = 0; + m_fit_int_enable = 0; + m_wdt_bit = 0; + m_wdt_int_enable = 0; + m_dac1 = 0; + m_dac2 = 0; + m_iac1 = 0; + m_iac2 = 0; + + memset(&m_spu_old, 0, sizeof(m_spu_old)); + memset(m_dma, 0, sizeof(m_dma)); + m_dmasr = 0; + + m_reserved = 0; + m_reserved_address = 0; + m_interrupt_pending = 0; + m_tb = 0; + m_dec = 0; + m_dec_frac = 0; + memset(m_fpr, 0, sizeof(m_fpr)); + m_lt = 0; + m_sp = 0; + m_tcr = 0; + m_ibr = 0; + m_esasrr = 0; + m_sebr = 0; + m_ser = 0; + + memset(&m_spu, 0, sizeof(m_spu)); + m_pit_reload = 0; + m_irqstate = 0; + memset(m_buffered_dma_rate, 0, sizeof(m_buffered_dma_rate)); + m_codexor = 0; + m_system_clock = 0; + m_cpu_clock = 0; + m_tb_zero_cycles = 0; + m_dec_zero_cycles = 0; + + m_arg1 = 0; + m_fastram_select = 0; + memset(m_fastram, 0, sizeof(m_fastram)); + m_hotspot_select = 0; + memset(m_hotspot, 0, sizeof(m_hotspot)); + + m_cache_line_size = 32; + m_cpu_clock = clock(); + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); + m_system_clock = c_bus_frequency != 0 ? c_bus_frequency : clock(); + m_dcr_read_func = read32_delegate(); + m_dcr_write_func = write32_delegate(); + + m_tb_divisor = (m_tb_divisor * clock() + m_system_clock / 2 - 1) / m_system_clock; + m_codexor = 0; + if (!(m_cap & PPCCAP_4XX) && space_config()->m_endianness != ENDIANNESS_NATIVE) + m_codexor = 4; /* allocate the virtual TLB */ - ppc->vtlb = vtlb_alloc(device, AS_PROGRAM, (cap & PPCCAP_603_MMU) ? PPC603_FIXED_TLB_ENTRIES : 0, POWERPC_TLB_ENTRIES); + m_vtlb = vtlb_alloc(this, AS_PROGRAM, (m_cap & PPCCAP_603_MMU) ? PPC603_FIXED_TLB_ENTRIES : 0, POWERPC_TLB_ENTRIES); /* allocate a timer for the compare interrupt */ - if ((cap & PPCCAP_OEA) && (ppc->tb_divisor)) - ppc->decrementer_int_timer = device->machine().scheduler().timer_alloc(FUNC(decrementer_int_callback), ppc); + if ((m_cap & PPCCAP_OEA) && (m_tb_divisor)) + m_decrementer_int_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ppc_device::decrementer_int_callback), this)); /* and for the 4XX interrupts if needed */ - if (cap & PPCCAP_4XX) + if (m_cap & PPCCAP_4XX) { - ppc->fit_timer = device->machine().scheduler().timer_alloc(FUNC(ppc4xx_fit_callback), ppc); - ppc->pit_timer = device->machine().scheduler().timer_alloc(FUNC(ppc4xx_pit_callback), ppc); - ppc->spu.timer = device->machine().scheduler().timer_alloc(FUNC(ppc4xx_spu_callback), ppc); + m_fit_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ppc_device::ppc4xx_fit_callback), this)); + m_pit_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ppc_device::ppc4xx_pit_callback), this)); + m_spu.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ppc_device::ppc4xx_spu_callback), this)); } - if (cap & PPCCAP_4XX) + if (m_cap & PPCCAP_4XX) { - ppc->buffered_dma_timer[0] = device->machine().scheduler().timer_alloc(FUNC(ppc4xx_buffered_dma_callback), ppc); - ppc->buffered_dma_timer[1] = device->machine().scheduler().timer_alloc(FUNC(ppc4xx_buffered_dma_callback), ppc); - ppc->buffered_dma_timer[2] = device->machine().scheduler().timer_alloc(FUNC(ppc4xx_buffered_dma_callback), ppc); - ppc->buffered_dma_timer[3] = device->machine().scheduler().timer_alloc(FUNC(ppc4xx_buffered_dma_callback), ppc); - - ppc->buffered_dma_rate[0] = 10000; - ppc->buffered_dma_rate[1] = 10000; - ppc->buffered_dma_rate[2] = 10000; - ppc->buffered_dma_rate[3] = 10000; + m_buffered_dma_timer[0] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ppc_device::ppc4xx_buffered_dma_callback), this)); + m_buffered_dma_timer[1] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ppc_device::ppc4xx_buffered_dma_callback), this)); + m_buffered_dma_timer[2] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ppc_device::ppc4xx_buffered_dma_callback), this)); + m_buffered_dma_timer[3] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ppc_device::ppc4xx_buffered_dma_callback), this)); + + m_buffered_dma_rate[0] = 10000; + m_buffered_dma_rate[1] = 10000; + m_buffered_dma_rate[2] = 10000; + m_buffered_dma_rate[3] = 10000; } /* register for save states */ - device->save_item(NAME(ppc->pc)); - device->save_item(NAME(ppc->r)); - device->save_item(NAME(ppc->f)); - device->save_item(NAME(ppc->cr)); - device->save_item(NAME(ppc->xerso)); - device->save_item(NAME(ppc->fpscr)); - device->save_item(NAME(ppc->msr)); - device->save_item(NAME(ppc->sr)); - device->save_item(NAME(ppc->spr)); - device->save_item(NAME(ppc->dcr)); - if (cap & PPCCAP_4XX) + save_item(NAME(m_core->pc)); + save_item(NAME(m_core->r)); + save_item(NAME(m_core->f)); + save_item(NAME(m_core->cr)); + save_item(NAME(m_core->xerso)); + save_item(NAME(m_core->fpscr)); + save_item(NAME(m_core->msr)); + save_item(NAME(m_core->sr)); + save_item(NAME(m_core->spr)); + save_item(NAME(m_dcr)); + if (m_cap & PPCCAP_4XX) + { + save_item(NAME(m_spu.regs)); + save_item(NAME(m_spu.txbuf)); + save_item(NAME(m_spu.rxbuf)); + save_item(NAME(m_spu.rxbuffer)); + save_item(NAME(m_spu.rxin)); + save_item(NAME(m_spu.rxout)); + save_item(NAME(m_pit_reload)); + save_item(NAME(m_irqstate)); + } + if (m_cap & PPCCAP_603_MMU) + { + save_item(NAME(m_core->mmu603_cmp)); + save_item(NAME(m_core->mmu603_hash)); + save_item(NAME(m_core->mmu603_r)); + } + save_item(NAME(m_core->irq_pending)); + save_item(NAME(m_tb_zero_cycles)); + save_item(NAME(m_dec_zero_cycles)); + + // Register debugger state + state_add(PPC_PC, "PC", m_core->pc).formatstr("%08X"); + state_add(PPC_MSR, "MSR", m_core->msr).formatstr("%08X"); + state_add(PPC_CR, "CR", m_debugger_temp).callimport().callexport().formatstr("%08X"); + state_add(PPC_LR, "LR", m_core->spr[SPR_LR]).formatstr("%08X"); + state_add(PPC_CTR, "CTR", m_core->spr[SPR_CTR]).formatstr("%08X"); + state_add(PPC_XER, "XER", m_debugger_temp).callimport().callexport().formatstr("%08X"); + state_add(PPC_SRR0, "SRR0", m_core->spr[SPROEA_SRR0]).formatstr("%08X"); + state_add(PPC_SRR1, "SRR1", m_core->spr[SPROEA_SRR1]).formatstr("%08X"); + state_add(PPC_SPRG0, "SPRG0", m_core->spr[SPROEA_SPRG0]).formatstr("%08X"); + state_add(PPC_SPRG1, "SPRG1", m_core->spr[SPROEA_SPRG1]).formatstr("%08X"); + state_add(PPC_SPRG2, "SPRG2", m_core->spr[SPROEA_SPRG2]).formatstr("%08X"); + state_add(PPC_SPRG3, "SPRG3", m_core->spr[SPROEA_SPRG3]).formatstr("%08X"); + state_add(PPC_SDR1, "SDR1", m_core->spr[SPROEA_SDR1]).formatstr("%08X"); + state_add(PPC_EXIER, "EXIER", m_dcr[DCR4XX_EXIER]).formatstr("%08X"); + state_add(PPC_EXISR, "EXISR", m_dcr[DCR4XX_EXISR]).formatstr("%08X"); + state_add(PPC_EVPR, "EVPR", m_core->spr[SPR4XX_EVPR]).formatstr("%08X"); + state_add(PPC_IOCR, "IOCR", m_dcr[DCR4XX_EXISR]).formatstr("%08X"); + state_add(PPC_TBH, "TBH", m_debugger_temp).callimport().callexport().formatstr("%08X"); + state_add(PPC_TBL, "TBL", m_debugger_temp).callimport().callexport().formatstr("%08X"); + state_add(PPC_DEC, "DEC", m_debugger_temp).callimport().callexport().formatstr("%08X"); + + state_add(PPC_SR0, "SR0", m_core->sr[0]).formatstr("%08X"); + state_add(PPC_SR1, "SR1", m_core->sr[1]).formatstr("%08X"); + state_add(PPC_SR2, "SR2", m_core->sr[2]).formatstr("%08X"); + state_add(PPC_SR3, "SR3", m_core->sr[3]).formatstr("%08X"); + state_add(PPC_SR4, "SR4", m_core->sr[4]).formatstr("%08X"); + state_add(PPC_SR5, "SR5", m_core->sr[5]).formatstr("%08X"); + state_add(PPC_SR6, "SR6", m_core->sr[6]).formatstr("%08X"); + state_add(PPC_SR7, "SR7", m_core->sr[7]).formatstr("%08X"); + state_add(PPC_SR8, "SR8", m_core->sr[8]).formatstr("%08X"); + state_add(PPC_SR9, "SR9", m_core->sr[9]).formatstr("%08X"); + state_add(PPC_SR10, "SR10", m_core->sr[10]).formatstr("%08X"); + state_add(PPC_SR11, "SR11", m_core->sr[11]).formatstr("%08X"); + state_add(PPC_SR12, "SR12", m_core->sr[12]).formatstr("%08X"); + state_add(PPC_SR13, "SR13", m_core->sr[13]).formatstr("%08X"); + state_add(PPC_SR14, "SR14", m_core->sr[14]).formatstr("%08X"); + state_add(PPC_SR15, "SR15", m_core->sr[15]).formatstr("%08X"); + + state_add(PPC_R0, "R0", m_core->r[0]).formatstr("%08X"); + state_add(PPC_R1, "R1", m_core->r[1]).formatstr("%08X"); + state_add(PPC_R2, "R2", m_core->r[2]).formatstr("%08X"); + state_add(PPC_R3, "R3", m_core->r[3]).formatstr("%08X"); + state_add(PPC_R4, "R4", m_core->r[4]).formatstr("%08X"); + state_add(PPC_R5, "R5", m_core->r[5]).formatstr("%08X"); + state_add(PPC_R6, "R6", m_core->r[6]).formatstr("%08X"); + state_add(PPC_R7, "R7", m_core->r[7]).formatstr("%08X"); + state_add(PPC_R8, "R8", m_core->r[8]).formatstr("%08X"); + state_add(PPC_R9, "R9", m_core->r[9]).formatstr("%08X"); + state_add(PPC_R10, "R10", m_core->r[10]).formatstr("%08X"); + state_add(PPC_R11, "R11", m_core->r[11]).formatstr("%08X"); + state_add(PPC_R12, "R12", m_core->r[12]).formatstr("%08X"); + state_add(PPC_R13, "R13", m_core->r[13]).formatstr("%08X"); + state_add(PPC_R14, "R14", m_core->r[14]).formatstr("%08X"); + state_add(PPC_R15, "R15", m_core->r[15]).formatstr("%08X"); + state_add(PPC_R16, "R16", m_core->r[16]).formatstr("%08X"); + state_add(PPC_R17, "R17", m_core->r[17]).formatstr("%08X"); + state_add(PPC_R18, "R18", m_core->r[18]).formatstr("%08X"); + state_add(PPC_R19, "R19", m_core->r[19]).formatstr("%08X"); + state_add(PPC_R20, "R20", m_core->r[20]).formatstr("%08X"); + state_add(PPC_R21, "R21", m_core->r[21]).formatstr("%08X"); + state_add(PPC_R22, "R22", m_core->r[22]).formatstr("%08X"); + state_add(PPC_R23, "R23", m_core->r[23]).formatstr("%08X"); + state_add(PPC_R24, "R24", m_core->r[24]).formatstr("%08X"); + state_add(PPC_R25, "R25", m_core->r[25]).formatstr("%08X"); + state_add(PPC_R26, "R26", m_core->r[26]).formatstr("%08X"); + state_add(PPC_R27, "R27", m_core->r[27]).formatstr("%08X"); + state_add(PPC_R28, "R28", m_core->r[28]).formatstr("%08X"); + state_add(PPC_R29, "R29", m_core->r[29]).formatstr("%08X"); + state_add(PPC_R30, "R30", m_core->r[30]).formatstr("%08X"); + state_add(PPC_R31, "R31", m_core->r[31]).formatstr("%08X"); + + state_add(PPC_F0, "F0", m_core->f[0]).formatstr("%12s"); + state_add(PPC_F1, "F1", m_core->f[1]).formatstr("%12s"); + state_add(PPC_F2, "F2", m_core->f[2]).formatstr("%12s"); + state_add(PPC_F3, "F3", m_core->f[3]).formatstr("%12s"); + state_add(PPC_F4, "F4", m_core->f[4]).formatstr("%12s"); + state_add(PPC_F5, "F5", m_core->f[5]).formatstr("%12s"); + state_add(PPC_F6, "F6", m_core->f[6]).formatstr("%12s"); + state_add(PPC_F7, "F7", m_core->f[7]).formatstr("%12s"); + state_add(PPC_F8, "F8", m_core->f[8]).formatstr("%12s"); + state_add(PPC_F9, "F9", m_core->f[9]).formatstr("%12s"); + state_add(PPC_F10, "F10", m_core->f[10]).formatstr("%12s"); + state_add(PPC_F11, "F11", m_core->f[11]).formatstr("%12s"); + state_add(PPC_F12, "F12", m_core->f[12]).formatstr("%12s"); + state_add(PPC_F13, "F13", m_core->f[13]).formatstr("%12s"); + state_add(PPC_F14, "F14", m_core->f[14]).formatstr("%12s"); + state_add(PPC_F15, "F15", m_core->f[15]).formatstr("%12s"); + state_add(PPC_F16, "F16", m_core->f[16]).formatstr("%12s"); + state_add(PPC_F17, "F17", m_core->f[17]).formatstr("%12s"); + state_add(PPC_F18, "F18", m_core->f[18]).formatstr("%12s"); + state_add(PPC_F19, "F19", m_core->f[19]).formatstr("%12s"); + state_add(PPC_F20, "F20", m_core->f[20]).formatstr("%12s"); + state_add(PPC_F21, "F21", m_core->f[21]).formatstr("%12s"); + state_add(PPC_F22, "F22", m_core->f[22]).formatstr("%12s"); + state_add(PPC_F23, "F23", m_core->f[23]).formatstr("%12s"); + state_add(PPC_F24, "F24", m_core->f[24]).formatstr("%12s"); + state_add(PPC_F25, "F25", m_core->f[25]).formatstr("%12s"); + state_add(PPC_F26, "F26", m_core->f[26]).formatstr("%12s"); + state_add(PPC_F27, "F27", m_core->f[27]).formatstr("%12s"); + state_add(PPC_F28, "F28", m_core->f[28]).formatstr("%12s"); + state_add(PPC_F29, "F29", m_core->f[29]).formatstr("%12s"); + state_add(PPC_F30, "F30", m_core->f[30]).formatstr("%12s"); + state_add(PPC_F31, "F31", m_core->f[31]).formatstr("%12s"); + state_add(PPC_FPSCR, "FPSCR", m_core->fpscr).formatstr("%08X"); + + state_add(STATE_GENPC, "GENPC", m_core->pc).noshow(); + state_add(STATE_GENSP, "GENSP", m_core->r[31]).noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_debugger_temp).noshow().formatstr("%1s"); + + m_icountptr = &m_core->icount; + + UINT32 flags = 0; + /* initialize the UML generator */ + if (LOG_UML) + flags |= DRCUML_OPTION_LOG_UML; + if (LOG_NATIVE) + flags |= DRCUML_OPTION_LOG_NATIVE; + m_drcuml = auto_alloc(machine(), drcuml_state(*this, m_cache, flags, 8, 32, 2)); + + /* add symbols for our stuff */ + m_drcuml->symbol_add(&m_core->pc, sizeof(m_core->pc), "pc"); + m_drcuml->symbol_add(&m_core->icount, sizeof(m_core->icount), "icount"); + for (int regnum = 0; regnum < 32; regnum++) { - device->save_item(NAME(ppc->spu.regs)); - device->save_item(NAME(ppc->spu.txbuf)); - device->save_item(NAME(ppc->spu.rxbuf)); - device->save_item(NAME(ppc->spu.rxbuffer)); - device->save_item(NAME(ppc->spu.rxin)); - device->save_item(NAME(ppc->spu.rxout)); - device->save_item(NAME(ppc->pit_reload)); - device->save_item(NAME(ppc->irqstate)); + char buf[10]; + sprintf(buf, "r%d", regnum); + m_drcuml->symbol_add(&m_core->r[regnum], sizeof(m_core->r[regnum]), buf); + sprintf(buf, "fpr%d", regnum); + m_drcuml->symbol_add(&m_core->f[regnum], sizeof(m_core->f[regnum]), buf); } - if (cap & PPCCAP_603_MMU) + for (int regnum = 0; regnum < 8; regnum++) { - device->save_item(NAME(ppc->mmu603_cmp)); - device->save_item(NAME(ppc->mmu603_hash)); - device->save_item(NAME(ppc->mmu603_r)); + char buf[10]; + sprintf(buf, "cr%d", regnum); + m_drcuml->symbol_add(&m_core->cr[regnum], sizeof(m_core->cr[regnum]), buf); + } + m_drcuml->symbol_add(&m_core->xerso, sizeof(m_core->xerso), "xerso"); + m_drcuml->symbol_add(&m_core->fpscr, sizeof(m_core->fpscr), "fpscr"); + m_drcuml->symbol_add(&m_core->msr, sizeof(m_core->msr), "msr"); + m_drcuml->symbol_add(&m_core->sr, sizeof(m_core->sr), "sr"); + m_drcuml->symbol_add(&m_core->spr[SPR_XER], sizeof(m_core->spr[SPR_XER]), "xer"); + m_drcuml->symbol_add(&m_core->spr[SPR_LR], sizeof(m_core->spr[SPR_LR]), "lr"); + m_drcuml->symbol_add(&m_core->spr[SPR_CTR], sizeof(m_core->spr[SPR_CTR]), "ctr"); + m_drcuml->symbol_add(&m_core->spr, sizeof(m_core->spr), "spr"); + m_drcuml->symbol_add(&m_dcr, sizeof(m_dcr), "dcr"); + m_drcuml->symbol_add(&m_core->param0, sizeof(m_core->param0), "param0"); + m_drcuml->symbol_add(&m_core->param1, sizeof(m_core->param1), "param1"); + m_drcuml->symbol_add(&m_core->irq_pending, sizeof(m_core->irq_pending), "irq_pending"); + m_drcuml->symbol_add(&m_core->mode, sizeof(m_core->mode), "mode"); + m_drcuml->symbol_add(&m_core->arg0, sizeof(m_core->arg0), "arg0"); + m_drcuml->symbol_add(&m_arg1, sizeof(m_arg1), "arg1"); + m_drcuml->symbol_add(&m_core->updateaddr, sizeof(m_core->updateaddr), "updateaddr"); + m_drcuml->symbol_add(&m_core->swcount, sizeof(m_core->swcount), "swcount"); + m_drcuml->symbol_add(&m_core->tempaddr, sizeof(m_core->tempaddr), "tempaddr"); + m_drcuml->symbol_add(&m_core->tempdata, sizeof(m_core->tempdata), "tempdata"); + m_drcuml->symbol_add(&m_core->fp0, sizeof(m_core->fp0), "fp0"); + m_drcuml->symbol_add(&m_fpmode, sizeof(m_fpmode), "fpmode"); + m_drcuml->symbol_add(&m_sz_cr_table, sizeof(m_sz_cr_table), "sz_cr_table"); + m_drcuml->symbol_add(&m_cmp_cr_table, sizeof(m_cmp_cr_table), "cmp_cr_table"); + m_drcuml->symbol_add(&m_cmpl_cr_table, sizeof(m_cmpl_cr_table), "cmpl_cr_table"); + m_drcuml->symbol_add(&m_fcmp_cr_table, sizeof(m_fcmp_cr_table), "fcmp_cr_table"); + + /* initialize the front-end helper */ + m_drcfe = auto_alloc(machine(), ppc_frontend(this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE)); + + /* compute the register parameters */ + for (int regnum = 0; regnum < 32; regnum++) + { + m_regmap[regnum] = uml::mem(&m_core->r[regnum]); + m_fdregmap[regnum] = uml::mem(&m_core->f[regnum]); + } + + /* if we have registers to spare, assign r0, r1, r2 to leftovers */ + if (!DISABLE_FAST_REGISTERS) + { + drcbe_info beinfo; + m_drcuml->get_backend_info(beinfo); + if (beinfo.direct_iregs > 5) + m_regmap[0] = uml::I5; + if (beinfo.direct_iregs > 6) + m_regmap[1] = uml::I6; + if (beinfo.direct_iregs > 7) + m_regmap[2] = uml::I7; + } + + /* mark the cache dirty so it is updated on next execute */ + m_cache_dirty = TRUE; +} + +void ppc_device::state_export(const device_state_entry &entry) +{ + switch (entry.index()) + { + case PPC_CR: + m_debugger_temp = get_cr(); + break; + + case PPC_XER: + m_debugger_temp = get_xer(); + break; + + case PPC_TBH: + m_debugger_temp = get_timebase() >> 32; + break; + + case PPC_TBL: + m_debugger_temp = (UINT32)get_timebase(); + break; + + case PPC_DEC: + m_debugger_temp = get_decrementer(); + break; + } +} + +void ppc_device::state_import(const device_state_entry &entry) +{ + switch (entry.index()) + { + case PPC_CR: + set_cr(m_debugger_temp); + break; + + case PPC_XER: + set_xer(m_debugger_temp); + break; + + case PPC_TBL: + set_timebase((get_timebase() & ~U64(0x00ffffff00000000)) | m_debugger_temp); + break; + + case PPC_TBH: + set_timebase((get_timebase() & ~U64(0x00000000ffffffff)) | ((UINT64)(m_debugger_temp & 0x00ffffff) << 32)); + break; + + case PPC_DEC: + set_decrementer(m_debugger_temp); + break; + } +} + + +void ppc_device::state_string_export(const device_state_entry &entry, astring &string) +{ + switch (entry.index()) + { + case PPC_F0: + string.printf("%12f", m_core->f[0]); + break; + + case PPC_F1: + string.printf("%12f", m_core->f[1]); + break; + + case PPC_F2: + string.printf("%12f", m_core->f[2]); + break; + + case PPC_F3: + string.printf("%12f", m_core->f[3]); + break; + + case PPC_F4: + string.printf("%12f", m_core->f[4]); + break; + + case PPC_F5: + string.printf("%12f", m_core->f[5]); + break; + + case PPC_F6: + string.printf("%12f", m_core->f[6]); + break; + + case PPC_F7: + string.printf("%12f", m_core->f[7]); + break; + + case PPC_F8: + string.printf("%12f", m_core->f[8]); + break; + + case PPC_F9: + string.printf("%12f", m_core->f[9]); + break; + + case PPC_F10: + string.printf("%12f", m_core->f[10]); + break; + + case PPC_F11: + string.printf("%12f", m_core->f[11]); + break; + + case PPC_F12: + string.printf("%12f", m_core->f[12]); + break; + + case PPC_F13: + string.printf("%12f", m_core->f[13]); + break; + + case PPC_F14: + string.printf("%12f", m_core->f[14]); + break; + + case PPC_F15: + string.printf("%12f", m_core->f[15]); + break; + + case PPC_F16: + string.printf("%12f", m_core->f[16]); + break; + + case PPC_F17: + string.printf("%12f", m_core->f[17]); + break; + + case PPC_F18: + string.printf("%12f", m_core->f[18]); + break; + + case PPC_F19: + string.printf("%12f", m_core->f[19]); + break; + + case PPC_F20: + string.printf("%12f", m_core->f[20]); + break; + + case PPC_F21: + string.printf("%12f", m_core->f[21]); + break; + + case PPC_F22: + string.printf("%12f", m_core->f[22]); + break; + + case PPC_F23: + string.printf("%12f", m_core->f[23]); + break; + + case PPC_F24: + string.printf("%12f", m_core->f[24]); + break; + + case PPC_F25: + string.printf("%12f", m_core->f[25]); + break; + + case PPC_F26: + string.printf("%12f", m_core->f[26]); + break; + + case PPC_F27: + string.printf("%12f", m_core->f[27]); + break; + + case PPC_F28: + string.printf("%12f", m_core->f[28]); + break; + + case PPC_F29: + string.printf("%12f", m_core->f[29]); + break; + + case PPC_F30: + string.printf("%12f", m_core->f[30]); + break; + + case PPC_F31: + string.printf("%12f", m_core->f[31]); + break; } - device->save_item(NAME(ppc->irq_pending)); - device->save_item(NAME(ppc->tb_zero_cycles)); - device->save_item(NAME(ppc->dec_zero_cycles)); } @@ -400,10 +1151,15 @@ void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT32 cap, int tb_d ppccom_exit - common cleanup/exit -------------------------------------------------*/ -void ppccom_exit(powerpc_state *ppc) +void ppc_device::device_stop() { - if (ppc->vtlb != NULL) - vtlb_free(ppc->vtlb); + if (m_vtlb != NULL) + vtlb_free(m_vtlb); + m_vtlb = NULL; + + /* clean up the DRC */ + auto_free(machine(), m_drcfe); + auto_free(machine(), m_drcuml); } @@ -412,52 +1168,58 @@ void ppccom_exit(powerpc_state *ppc) registers -------------------------------------------------*/ -void ppccom_reset(powerpc_state *ppc) +void ppc_device::device_reset() { - int tlbindex; - /* initialize the OEA state */ - if (ppc->cap & PPCCAP_OEA) + if (m_cap & PPCCAP_OEA) { /* PC to the reset vector; MSR has IP set to start */ - ppc->pc = 0xfff00100; - ppc->msr = MSROEA_IP; + m_core->pc = 0xfff00100; + m_core->msr = MSROEA_IP; /* reset the decrementer */ - ppc->dec_zero_cycles = ppc->device->total_cycles(); - if (ppc->tb_divisor) + m_dec_zero_cycles = total_cycles(); + if (m_tb_divisor) { - decrementer_int_callback(ppc->device->machine(), ppc, 0); + decrementer_int_callback(NULL, 0); } } /* initialize the 4XX state */ - if (ppc->cap & PPCCAP_4XX) + if (m_cap & PPCCAP_4XX) { /* PC to the last word; MSR to 0 */ - ppc->pc = 0xfffffffc; - ppc->msr = 0; + m_core->pc = 0xfffffffc; + m_core->msr = 0; /* reset the SPU status */ - ppc->spr[SPR4XX_TCR] &= ~PPC4XX_TCR_WRC_MASK; - ppc->spu.regs[SPU4XX_LINE_STATUS] = 0x06; + m_core->spr[SPR4XX_TCR] &= ~PPC4XX_TCR_WRC_MASK; + m_spu.regs[SPU4XX_LINE_STATUS] = 0x06; } /* initialize the 602 HID0 register */ - if (ppc->flavor == PPC_MODEL_602) - ppc->spr[SPR603_HID0] = 1; + if (m_flavor == PPC_MODEL_602) + m_core->spr[SPR603_HID0] = 1; /* time base starts here */ - ppc->tb_zero_cycles = ppc->device->total_cycles(); + m_tb_zero_cycles = total_cycles(); /* clear interrupts */ - ppc->irq_pending = 0; + m_core->irq_pending = 0; /* flush the TLB */ - vtlb_flush_dynamic(ppc->vtlb); - if (ppc->cap & PPCCAP_603_MMU) - for (tlbindex = 0; tlbindex < PPC603_FIXED_TLB_ENTRIES; tlbindex++) - vtlb_load(ppc->vtlb, tlbindex, 0, 0, 0); + vtlb_flush_dynamic(m_vtlb); + if (m_cap & PPCCAP_603_MMU) + { + for (int tlbindex = 0; tlbindex < PPC603_FIXED_TLB_ENTRIES; tlbindex++) + { + vtlb_load(m_vtlb, tlbindex, 0, 0, 0); + } + } + + /* Mark the cache dirty */ + m_core->mode = 0; + m_cache_dirty = TRUE; } @@ -466,7 +1228,7 @@ void ppccom_reset(powerpc_state *ppc) CPU -------------------------------------------------*/ -offs_t ppccom_dasm(powerpc_state *ppc, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram) +offs_t ppc_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { extern offs_t ppc_dasm_one(char *buffer, UINT32 pc, UINT32 op); UINT32 op = *(UINT32 *)oprom; @@ -480,11 +1242,11 @@ offs_t ppccom_dasm(powerpc_state *ppc, char *buffer, offs_t pc, const UINT8 *opr callback if installed -------------------------------------------------*/ -void ppccom_dcstore_callback(powerpc_state *ppc) +void ppc_device::ppccom_dcstore_callback() { - if (ppc->dcstore_handler != NULL) + if (m_dcstore_handler != NULL) { - ppc->dcstore_handler(ppc->device, ppc->param0); + m_dcstore_handler(this, m_core->param0); } } @@ -500,7 +1262,7 @@ void ppccom_dcstore_callback(powerpc_state *ppc) filling -------------------------------------------------*/ -static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intention, offs_t *address) +UINT32 ppc_device::ppccom_translate_address_internal(int intention, offs_t &address) { int transpriv = ((intention & TRANSLATE_USER_MASK) == 0); // 1 for supervisor, 0 for user int transtype = intention & TRANSLATE_TYPE_MASK; @@ -509,42 +1271,42 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio UINT32 segreg; /* 4xx case: "TLB" really just caches writes and checks compare registers */ - if (ppc->cap & PPCCAP_4XX) + if (m_cap & PPCCAP_4XX) { /* we don't support the MMU of the 403GCX */ - if (ppc->flavor == PPC_MODEL_403GCX && (ppc->msr & MSROEA_DR)) + if (m_flavor == PPC_MODEL_403GCX && (m_core->msr & MSROEA_DR)) fatalerror("MMU enabled but not supported!\n"); /* only check if PE is enabled */ - if (transtype == TRANSLATE_WRITE && (ppc->msr & MSR4XX_PE)) + if (transtype == TRANSLATE_WRITE && (m_core->msr & MSR4XX_PE)) { /* are we within one of the protection ranges? */ - int inrange1 = ((*address >> 12) >= (ppc->spr[SPR4XX_PBL1] >> 12) && (*address >> 12) < (ppc->spr[SPR4XX_PBU1] >> 12)); - int inrange2 = ((*address >> 12) >= (ppc->spr[SPR4XX_PBL2] >> 12) && (*address >> 12) < (ppc->spr[SPR4XX_PBU2] >> 12)); + int inrange1 = ((address >> 12) >= (m_core->spr[SPR4XX_PBL1] >> 12) && (address >> 12) < (m_core->spr[SPR4XX_PBU1] >> 12)); + int inrange2 = ((address >> 12) >= (m_core->spr[SPR4XX_PBL2] >> 12) && (address >> 12) < (m_core->spr[SPR4XX_PBU2] >> 12)); /* if PX == 1, writes are only allowed OUTSIDE of the bounds */ - if (((ppc->msr & MSR4XX_PX) && (inrange1 || inrange2)) || (!(ppc->msr & MSR4XX_PX) && (!inrange1 && !inrange2))) + if (((m_core->msr & MSR4XX_PX) && (inrange1 || inrange2)) || (!(m_core->msr & MSR4XX_PX) && (!inrange1 && !inrange2))) return 0x002; } - *address &= 0x7fffffff; + address &= 0x7fffffff; return 0x001; } /* only applies if we support the OEA */ - if (!(ppc->cap & PPCCAP_OEA)) + if (!(m_cap & PPCCAP_OEA)) return 0x001; /* also no translation necessary if translation is disabled */ - if ((transtype == TRANSLATE_FETCH && (ppc->msr & MSROEA_IR) == 0) || (transtype != TRANSLATE_FETCH && (ppc->msr & MSROEA_DR) == 0)) + if ((transtype == TRANSLATE_FETCH && (m_core->msr & MSROEA_IR) == 0) || (transtype != TRANSLATE_FETCH && (m_core->msr & MSROEA_DR) == 0)) return 0x001; /* first scan the appropriate BAT */ - if (ppc->cap & PPCCAP_601BAT) + if (m_cap & PPCCAP_601BAT) { for (batnum = 0; batnum < 4; batnum++) { - UINT32 upper = ppc->spr[SPROEA_IBAT0U + 2*batnum + 0]; - UINT32 lower = ppc->spr[SPROEA_IBAT0U + 2*batnum + 1]; + UINT32 upper = m_core->spr[SPROEA_IBAT0U + 2*batnum + 0]; + UINT32 lower = m_core->spr[SPROEA_IBAT0U + 2*batnum + 1]; int privbit = ((intention & TRANSLATE_USER_MASK) == 0) ? 3 : 2; // printf("bat %d upper = %08x privbit %d\n", batnum, upper, privbit); @@ -557,7 +1319,7 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio UINT32 key = (upper >> privbit) & 1; /* check for a hit against this bucket */ - if ((*address & mask) == (upper & mask)) + if ((address & mask) == (upper & mask)) { /* verify protection; if we fail, return false and indicate a protection violation */ if (!page_access_allowed(transtype, key, upper & 3)) @@ -566,8 +1328,8 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio } /* otherwise we're good */ - addrout = (lower & mask) | (*address & ~mask); - *address = addrout; // top 9 bits from top 9 of PBN + addrout = (lower & mask) | (address & ~mask); + address = addrout; // top 9 bits from top 9 of PBN return 0x001; } } @@ -579,7 +1341,7 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio for (batnum = 0; batnum < 4; batnum++) { - UINT32 upper = ppc->spr[batbase + 2*batnum + 0]; + UINT32 upper = m_core->spr[batbase + 2*batnum + 0]; /* check user/supervisor valid bit */ if ((upper >> transpriv) & 0x01) @@ -587,9 +1349,9 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio UINT32 mask = (~upper << 15) & 0xfffe0000; /* check for a hit against this bucket */ - if ((*address & mask) == (upper & mask)) + if ((address & mask) == (upper & mask)) { - UINT32 lower = ppc->spr[batbase + 2*batnum + 1]; + UINT32 lower = m_core->spr[batbase + 2*batnum + 1]; /* verify protection; if we fail, return false and indicate a protection violation */ if (!page_access_allowed(transtype, 1, lower & 3)) @@ -598,7 +1360,7 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio } /* otherwise we're good */ - *address = (lower & mask) | (*address & ~mask); + address = (lower & mask) | (address & ~mask); return 0x001; } } @@ -606,16 +1368,16 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio } /* look up the segment register */ - segreg = ppc->sr[*address >> 28]; + segreg = m_core->sr[address >> 28]; if (transtype == TRANSLATE_FETCH && (segreg & 0x10000000)) return DSISR_PROTECTED | ((transtype == TRANSLATE_WRITE) ? DSISR_STORE : 0); /* check for memory-forced I/O */ - if (ppc->cap & PPCCAP_MFIOC) + if (m_cap & PPCCAP_MFIOC) { if ((transtype != TRANSLATE_FETCH) && ((segreg & 0x87f00000) == 0x87f00000)) { - *address = ((segreg & 0xf)<<28) | (*address & 0x0fffffff); + address = ((segreg & 0xf)<<28) | (address & 0x0fffffff); return 1; } else if (segreg & 0x80000000) @@ -625,20 +1387,20 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio } /* get hash table information from SD1 */ - hashbase = ppc->spr[SPROEA_SDR1] & 0xffff0000; - hashmask = ((ppc->spr[SPROEA_SDR1] & 0x1ff) << 16) | 0xffff; - hash = (segreg & 0x7ffff) ^ ((*address >> 12) & 0xffff); + hashbase = m_core->spr[SPROEA_SDR1] & 0xffff0000; + hashmask = ((m_core->spr[SPROEA_SDR1] & 0x1ff) << 16) | 0xffff; + hash = (segreg & 0x7ffff) ^ ((address >> 12) & 0xffff); /* if we're simulating the 603 MMU, fill in the data and stop here */ - if (ppc->cap & PPCCAP_603_MMU) + if (m_cap & PPCCAP_603_MMU) { - UINT32 entry = vtlb_table(ppc->vtlb)[*address >> 12]; - ppc->mmu603_cmp = 0x80000000 | ((segreg & 0xffffff) << 7) | (0 << 6) | ((*address >> 22) & 0x3f); - ppc->mmu603_hash[0] = hashbase | ((hash << 6) & hashmask); - ppc->mmu603_hash[1] = hashbase | ((~hash << 6) & hashmask); + UINT32 entry = vtlb_table(m_vtlb)[address >> 12]; + m_core->mmu603_cmp = 0x80000000 | ((segreg & 0xffffff) << 7) | (0 << 6) | ((address >> 22) & 0x3f); + m_core->mmu603_hash[0] = hashbase | ((hash << 6) & hashmask); + m_core->mmu603_hash[1] = hashbase | ((~hash << 6) & hashmask); if ((entry & (VTLB_FLAG_FIXED | VTLB_FLAG_VALID)) == (VTLB_FLAG_FIXED | VTLB_FLAG_VALID)) { - *address = (entry & 0xfffff000) | (*address & 0x00000fff); + address = (entry & 0xfffff000) | (address & 0x00000fff); return 0x001; } return DSISR_NOT_FOUND | ((transtype == TRANSLATE_WRITE) ? DSISR_STORE : 0); @@ -648,12 +1410,12 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio for (hashnum = 0; hashnum < 2; hashnum++) { offs_t ptegaddr = hashbase | ((hash << 6) & hashmask); - UINT32 *ptegptr = (UINT32 *)ppc->program->get_read_ptr(ptegaddr); + UINT32 *ptegptr = (UINT32 *)m_program->get_read_ptr(ptegaddr); /* should only have valid memory here, but make sure */ if (ptegptr != NULL) { - UINT32 targetupper = 0x80000000 | ((segreg & 0xffffff) << 7) | (hashnum << 6) | ((*address >> 22) & 0x3f); + UINT32 targetupper = 0x80000000 | ((segreg & 0xffffff) << 7) | (hashnum << 6) | ((address >> 22) & 0x3f); int ptenum; /* scan PTEs */ @@ -676,7 +1438,7 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio } /* otherwise we're good */ - *address = (pteglower & 0xfffff000) | (*address & 0x00000fff); + address = (pteglower & 0xfffff000) | (address & 0x00000fff); return (pteglower >> 7) & 1; } } @@ -695,14 +1457,14 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio from logical to physical -------------------------------------------------*/ -int ppccom_translate_address(powerpc_state *ppc, address_spacenum space, int intention, offs_t *address) +bool ppc_device::memory_translate(address_spacenum spacenum, int intention, offs_t &address) { /* only applies to the program address space */ - if (space != AS_PROGRAM) + if (spacenum != AS_PROGRAM) return TRUE; /* translation is successful if the internal routine returns 0 or 1 */ - return (ppccom_translate_address_internal(ppc, intention, address) <= 1); + return (ppccom_translate_address_internal(intention, address) <= 1); } @@ -710,9 +1472,9 @@ int ppccom_translate_address(powerpc_state *ppc, address_spacenum space, int int ppccom_tlb_fill - handle a missing TLB entry -------------------------------------------------*/ -void ppccom_tlb_fill(powerpc_state *ppc) +void ppc_device::ppccom_tlb_fill() { - vtlb_fill(ppc->vtlb, ppc->param0, ppc->param1); + vtlb_fill(m_vtlb, m_core->param0, m_core->param1); } @@ -721,9 +1483,9 @@ void ppccom_tlb_fill(powerpc_state *ppc) including fixed entries -------------------------------------------------*/ -void ppccom_tlb_flush(powerpc_state *ppc) +void ppc_device::ppccom_tlb_flush() { - vtlb_flush_dynamic(ppc->vtlb); + vtlb_flush_dynamic(m_vtlb); } @@ -737,9 +1499,9 @@ void ppccom_tlb_flush(powerpc_state *ppc) instruction -------------------------------------------------*/ -void ppccom_execute_tlbie(powerpc_state *ppc) +void ppc_device::ppccom_execute_tlbie() { - vtlb_flush_address(ppc->vtlb, ppc->param0); + vtlb_flush_address(m_vtlb, m_core->param0); } @@ -748,9 +1510,9 @@ void ppccom_execute_tlbie(powerpc_state *ppc) instruction -------------------------------------------------*/ -void ppccom_execute_tlbia(powerpc_state *ppc) +void ppc_device::ppccom_execute_tlbia() { - vtlb_flush_dynamic(ppc->vtlb); + vtlb_flush_dynamic(m_vtlb); } @@ -759,25 +1521,25 @@ void ppccom_execute_tlbia(powerpc_state *ppc) instruction -------------------------------------------------*/ -void ppccom_execute_tlbl(powerpc_state *ppc) +void ppc_device::ppccom_execute_tlbl() { - UINT32 address = ppc->param0; - int isitlb = ppc->param1; + UINT32 address = m_core->param0; + int isitlb = m_core->param1; vtlb_entry flags = 0; int entrynum; /* determine entry number; we use rand() for associativity */ - entrynum = ((address >> 12) & 0x1f) | (ppc->device->machine().rand() & 0x20) | (isitlb ? 0x40 : 0); + entrynum = ((address >> 12) & 0x1f) | (machine().rand() & 0x20) | (isitlb ? 0x40 : 0); /* determine the flags */ flags = VTLB_FLAG_VALID | VTLB_READ_ALLOWED | VTLB_FETCH_ALLOWED; - if (ppc->spr[SPR603_RPA] & 0x80) + if (m_core->spr[SPR603_RPA] & 0x80) flags |= VTLB_WRITE_ALLOWED; if (isitlb) flags |= VTLB_FETCH_ALLOWED; /* load the entry */ - vtlb_load(ppc->vtlb, entrynum, 1, address, (ppc->spr[SPR603_RPA] & 0xfffff000) | flags); + vtlb_load(m_vtlb, entrynum, 1, address, (m_core->spr[SPR603_RPA] & 0xfffff000) | flags); } @@ -786,16 +1548,16 @@ void ppccom_execute_tlbl(powerpc_state *ppc) instruction -------------------------------------------------*/ -void ppccom_execute_mftb(powerpc_state *ppc) +void ppc_device::ppccom_execute_mftb() { - switch (ppc->param0) + switch (m_core->param0) { /* user mode timebase read */ case SPRVEA_TBL_R: - ppc->param1 = get_timebase(ppc); + m_core->param1 = get_timebase(); break; case SPRVEA_TBU_R: - ppc->param1 = get_timebase(ppc) >> 32; + m_core->param1 = get_timebase() >> 32; break; } } @@ -806,12 +1568,12 @@ void ppccom_execute_mftb(powerpc_state *ppc) instruction -------------------------------------------------*/ -void ppccom_execute_mfspr(powerpc_state *ppc) +void ppc_device::ppccom_execute_mfspr() { /* handle OEA SPRs */ - if (ppc->cap & PPCCAP_OEA) + if (m_cap & PPCCAP_OEA) { - switch (ppc->param0) + switch (m_core->param0) { /* read-through no-ops */ case SPROEA_DSISR: @@ -837,20 +1599,20 @@ void ppccom_execute_mfspr(powerpc_state *ppc) case SPROEA_DBAT3L: case SPROEA_DBAT3U: case SPROEA_DABR: - ppc->param1 = ppc->spr[ppc->param0]; + m_core->param1 = m_core->spr[m_core->param0]; return; /* decrementer */ case SPROEA_DEC: - ppc->param1 = get_decrementer(ppc); + m_core->param1 = get_decrementer(); return; } } /* handle 603 SPRs */ - if (ppc->cap & PPCCAP_603_MMU) + if (m_cap & PPCCAP_603_MMU) { - switch (ppc->param0) + switch (m_core->param0) { /* read-through no-ops */ case SPR603_DMISS: @@ -864,23 +1626,23 @@ void ppccom_execute_mfspr(powerpc_state *ppc) case SPR603_HID1: case SPR603_IABR: case SPR603_HID2: - ppc->param1 = ppc->spr[ppc->param0]; + m_core->param1 = m_core->spr[m_core->param0]; return; /* timebase */ case SPR603_TBL_R: - ppc->param1 = get_timebase(ppc); + m_core->param1 = get_timebase(); return; case SPR603_TBU_R: - ppc->param1 = (get_timebase(ppc) >> 32) & 0xffffff; + m_core->param1 = (get_timebase() >> 32) & 0xffffff; return; } } /* handle 4XX SPRs */ - if (ppc->cap & PPCCAP_4XX) + if (m_cap & PPCCAP_4XX) { - switch (ppc->param0) + switch (m_core->param0) { /* read-through no-ops */ case SPR4XX_EVPR: @@ -901,24 +1663,24 @@ void ppccom_execute_mfspr(powerpc_state *ppc) case SPR4XX_PBU1: case SPR4XX_PBL2: case SPR4XX_PBU2: - ppc->param1 = ppc->spr[ppc->param0]; + m_core->param1 = m_core->spr[m_core->param0]; return; /* timebase */ case SPR4XX_TBLO: case SPR4XX_TBLU: - ppc->param1 = get_timebase(ppc); + m_core->param1 = get_timebase(); return; case SPR4XX_TBHI: case SPR4XX_TBHU: - ppc->param1 = (get_timebase(ppc) >> 32) & 0xffffff; + m_core->param1 = (get_timebase() >> 32) & 0xffffff; return; } } /* default handling */ - osd_printf_debug("SPR %03X read\n", ppc->param0); - ppc->param1 = ppc->spr[ppc->param0]; + osd_printf_debug("SPR %03X read\n", m_core->param0); + m_core->param1 = m_core->spr[m_core->param0]; } @@ -927,12 +1689,12 @@ void ppccom_execute_mfspr(powerpc_state *ppc) instruction -------------------------------------------------*/ -void ppccom_execute_mtspr(powerpc_state *ppc) +void ppc_device::ppccom_execute_mtspr() { /* handle OEA SPRs */ - if (ppc->cap & PPCCAP_OEA) + if (m_cap & PPCCAP_OEA) { - switch (ppc->param0) + switch (m_core->param0) { /* write-through no-ops */ case SPROEA_DSISR: @@ -941,7 +1703,7 @@ void ppccom_execute_mtspr(powerpc_state *ppc) case SPROEA_SRR1: case SPROEA_EAR: case SPROEA_DABR: - ppc->spr[ppc->param0] = ppc->param1; + m_core->spr[m_core->param0] = m_core->param1; return; /* registers that affect the memory map */ @@ -962,21 +1724,21 @@ void ppccom_execute_mtspr(powerpc_state *ppc) case SPROEA_DBAT2U: case SPROEA_DBAT3L: case SPROEA_DBAT3U: - ppc->spr[ppc->param0] = ppc->param1; - ppccom_tlb_flush(ppc); + m_core->spr[m_core->param0] = m_core->param1; + ppccom_tlb_flush(); return; /* decrementer */ case SPROEA_DEC: - set_decrementer(ppc, ppc->param1); + set_decrementer(m_core->param1); return; } } /* handle 603 SPRs */ - if (ppc->cap & PPCCAP_603_MMU) + if (m_cap & PPCCAP_603_MMU) { - switch (ppc->param0) + switch (m_core->param0) { /* read-only */ case SPR603_DMISS: @@ -993,24 +1755,24 @@ void ppccom_execute_mtspr(powerpc_state *ppc) case SPR603_HID1: case SPR603_IABR: case SPR603_HID2: - ppc->spr[ppc->param0] = ppc->param1; + m_core->spr[m_core->param0] = m_core->param1; return; /* timebase */ case SPR603_TBL_W: - set_timebase(ppc, (get_timebase(ppc) & ~U64(0xffffffff00000000)) | ppc->param1); + set_timebase((get_timebase() & ~U64(0xffffffff00000000)) | m_core->param1); return; case SPR603_TBU_W: - set_timebase(ppc, (get_timebase(ppc) & ~U64(0x00000000ffffffff)) | ((UINT64)ppc->param1 << 32)); + set_timebase((get_timebase() & ~U64(0x00000000ffffffff)) | ((UINT64)m_core->param1 << 32)); return; } } /* handle 4XX SPRs */ - if (ppc->cap & PPCCAP_4XX) + if (m_cap & PPCCAP_4XX) { - UINT32 oldval = ppc->spr[ppc->param0]; - switch (ppc->param0) + UINT32 oldval = m_core->spr[m_core->param0]; + switch (m_core->param0) { /* write-through no-ops */ case SPR4XX_EVPR: @@ -1021,7 +1783,7 @@ void ppccom_execute_mtspr(powerpc_state *ppc) case SPR4XX_SRR1: case SPR4XX_SRR2: case SPR4XX_SRR3: - ppc->spr[ppc->param0] = ppc->param1; + m_core->spr[m_core->param0] = m_core->param1; return; /* registers that affect the memory map */ @@ -1029,45 +1791,45 @@ void ppccom_execute_mtspr(powerpc_state *ppc) case SPR4XX_PBU1: case SPR4XX_PBL2: case SPR4XX_PBU2: - ppc->spr[ppc->param0] = ppc->param1; - ppccom_tlb_flush(ppc); + m_core->spr[m_core->param0] = m_core->param1; + ppccom_tlb_flush(); return; /* timer control register */ case SPR4XX_TCR: - ppc->spr[SPR4XX_TCR] = ppc->param1 | (oldval & PPC4XX_TCR_WRC_MASK); - if ((oldval ^ ppc->spr[SPR4XX_TCR]) & PPC4XX_TCR_FIE) - ppc4xx_fit_callback(ppc->device->machine(), ppc, FALSE); - if ((oldval ^ ppc->spr[SPR4XX_TCR]) & PPC4XX_TCR_PIE) - ppc4xx_pit_callback(ppc->device->machine(), ppc, FALSE); + m_core->spr[SPR4XX_TCR] = m_core->param1 | (oldval & PPC4XX_TCR_WRC_MASK); + if ((oldval ^ m_core->spr[SPR4XX_TCR]) & PPC4XX_TCR_FIE) + ppc4xx_fit_callback(NULL, FALSE); + if ((oldval ^ m_core->spr[SPR4XX_TCR]) & PPC4XX_TCR_PIE) + ppc4xx_pit_callback(NULL, FALSE); return; /* timer status register */ case SPR4XX_TSR: - ppc->spr[SPR4XX_TSR] &= ~ppc->param1; - ppc4xx_set_irq_line(ppc, 0, 0); + m_core->spr[SPR4XX_TSR] &= ~m_core->param1; + ppc4xx_set_irq_line(0, 0); return; /* PIT */ case SPR4XX_PIT: - ppc->spr[SPR4XX_PIT] = ppc->param1; - ppc->pit_reload = ppc->param1; - ppc4xx_pit_callback(ppc->device->machine(), ppc, FALSE); + m_core->spr[SPR4XX_PIT] = m_core->param1; + m_pit_reload = m_core->param1; + ppc4xx_pit_callback(NULL, FALSE); return; /* timebase */ case SPR4XX_TBLO: - set_timebase(ppc, (get_timebase(ppc) & ~U64(0x00ffffff00000000)) | ppc->param1); + set_timebase((get_timebase() & ~U64(0x00ffffff00000000)) | m_core->param1); return; case SPR4XX_TBHI: - set_timebase(ppc, (get_timebase(ppc) & ~U64(0x00000000ffffffff)) | ((UINT64)(ppc->param1 & 0x00ffffff) << 32)); + set_timebase((get_timebase() & ~U64(0x00000000ffffffff)) | ((UINT64)(m_core->param1 & 0x00ffffff) << 32)); return; } } /* default handling */ - osd_printf_debug("SPR %03X write = %08X\n", ppc->param0, ppc->param1); - ppc->spr[ppc->param0] = ppc->param1; + osd_printf_debug("SPR %03X write = %08X\n", m_core->param0, m_core->param1); + m_core->spr[m_core->param0] = m_core->param1; } @@ -1076,10 +1838,10 @@ void ppccom_execute_mtspr(powerpc_state *ppc) instruction -------------------------------------------------*/ -void ppccom_execute_mfdcr(powerpc_state *ppc) +void ppc_device::ppccom_execute_mfdcr() { /* handle various DCRs */ - switch (ppc->param0) + switch (m_core->param0) { /* read-through no-ops */ case DCR4XX_BR0: @@ -1115,19 +1877,19 @@ void ppccom_execute_mfdcr(powerpc_state *ppc) case DCR4XX_EXIER: case DCR4XX_EXISR: case DCR4XX_IOCR: - ppc->param1 = ppc->dcr[ppc->param0]; + m_core->param1 = m_dcr[m_core->param0]; return; } /* default handling */ - if (ppc->dcr_read_func.isnull()) { - osd_printf_debug("DCR %03X read\n", ppc->param0); - if (ppc->param0 < ARRAY_LENGTH(ppc->dcr)) - ppc->param1 = ppc->dcr[ppc->param0]; + if (m_dcr_read_func.isnull()) { + osd_printf_debug("DCR %03X read\n", m_core->param0); + if (m_core->param0 < ARRAY_LENGTH(m_dcr)) + m_core->param1 = m_dcr[m_core->param0]; else - ppc->param1 = 0; + m_core->param1 = 0; } else { - ppc->param1 = ppc->dcr_read_func(*ppc->program,ppc->param0,0xffffffff); + m_core->param1 = m_dcr_read_func(*m_program,m_core->param0,0xffffffff); } } @@ -1137,12 +1899,12 @@ void ppccom_execute_mfdcr(powerpc_state *ppc) instruction -------------------------------------------------*/ -void ppccom_execute_mtdcr(powerpc_state *ppc) +void ppc_device::ppccom_execute_mtdcr() { UINT8 oldval; /* handle various DCRs */ - switch (ppc->param0) + switch (m_core->param0) { /* write-through no-ops */ case DCR4XX_BR0: @@ -1170,25 +1932,25 @@ void ppccom_execute_mtdcr(powerpc_state *ppc) case DCR4XX_DMADA3: case DCR4XX_DMASA3: case DCR4XX_DMACC3: - ppc->dcr[ppc->param0] = ppc->param1; + m_dcr[m_core->param0] = m_core->param1; return; /* DMA status */ case DCR4XX_DMASR: - ppc->dcr[DCR4XX_DMASR] &= ~(ppc->param1 & 0xfff80070); - ppc4xx_dma_update_irq_states(ppc); + m_dcr[DCR4XX_DMASR] &= ~(m_core->param1 & 0xfff80070); + ppc4xx_dma_update_irq_states(); return; /* interrupt enables */ case DCR4XX_EXIER: - ppc->dcr[DCR4XX_EXIER] = ppc->param1; - ppc4xx_set_irq_line(ppc, 0, 0); + m_dcr[DCR4XX_EXIER] = m_core->param1; + ppc4xx_set_irq_line(0, 0); return; /* interrupt clear */ case DCR4XX_EXISR: - ppc->dcr[ppc->param0] &= ~ppc->param1; - ppc4xx_set_irq_line(ppc, 0, 0); + m_dcr[m_core->param0] &= ~m_core->param1; + ppc4xx_set_irq_line(0, 0); return; /* DMA controls */ @@ -1196,28 +1958,28 @@ void ppccom_execute_mtdcr(powerpc_state *ppc) case DCR4XX_DMACR1: case DCR4XX_DMACR2: case DCR4XX_DMACR3: - ppc->dcr[ppc->param0] = ppc->param1; - if (ppc->param1 & PPC4XX_DMACR_CE) - ppc4xx_dma_exec(ppc, (ppc->param0 - DCR4XX_DMACR0) / 8); - ppc4xx_dma_update_irq_states(ppc); + m_dcr[m_core->param0] = m_core->param1; + if (m_core->param1 & PPC4XX_DMACR_CE) + ppc4xx_dma_exec((m_core->param0 - DCR4XX_DMACR0) / 8); + ppc4xx_dma_update_irq_states(); return; /* I/O control */ case DCR4XX_IOCR: - oldval = ppc->dcr[ppc->param0]; - ppc->dcr[ppc->param0] = ppc->param1; - if ((oldval ^ ppc->param1) & 0x02) - ppc4xx_spu_timer_reset(ppc); + oldval = m_dcr[m_core->param0]; + m_dcr[m_core->param0] = m_core->param1; + if ((oldval ^ m_core->param1) & 0x02) + ppc4xx_spu_timer_reset(); return; } /* default handling */ - if (ppc->dcr_write_func.isnull()) { - osd_printf_debug("DCR %03X write = %08X\n", ppc->param0, ppc->param1); - if (ppc->param0 < ARRAY_LENGTH(ppc->dcr)) - ppc->dcr[ppc->param0] = ppc->param1; + if (m_dcr_write_func.isnull()) { + osd_printf_debug("DCR %03X write = %08X\n", m_core->param0, m_core->param1); + if (m_core->param0 < ARRAY_LENGTH(m_dcr)) + m_dcr[m_core->param0] = m_core->param1; } else { - ppc->dcr_write_func(*ppc->program,ppc->param0,ppc->param1,0xffffffff); + m_dcr_write_func(*m_program,m_core->param0,m_core->param1,0xffffffff); } } @@ -1232,10 +1994,10 @@ void ppccom_execute_mtdcr(powerpc_state *ppc) of the FPSCR register -------------------------------------------------*/ -void ppccom_update_fprf(powerpc_state *ppc) +void ppc_device::ppccom_update_fprf() { UINT32 fprf; - double f = ppc->f[ppc->param0]; + double f = m_core->f[m_core->param0]; if (is_qnan_double(f)) { @@ -1270,405 +2032,11 @@ void ppccom_update_fprf(powerpc_state *ppc) fprf = 0x02; } - ppc->fpscr &= ~0x0001f000; - ppc->fpscr |= fprf << 12; + m_core->fpscr &= ~0x0001f000; + m_core->fpscr |= fprf << 12; } - -/*************************************************************************** - COMMON GET/SET INFO -***************************************************************************/ - -/*------------------------------------------------- - ppccom_set_info - set information about - a PowerPC CPU --------------------------------------------------*/ - -void ppccom_set_info(powerpc_state *ppc, UINT32 state, cpuinfo *info) -{ - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + PPC_IRQ: ppc->irq_pending = (ppc->irq_pending & ~1) | (info->i != CLEAR_LINE); break; - - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + PPC_PC: ppc->pc = info->i; break; - case CPUINFO_INT_REGISTER + PPC_MSR: ppc->msr = info->i; break; - case CPUINFO_INT_REGISTER + PPC_CR: set_cr(ppc, info->i); break; - case CPUINFO_INT_REGISTER + PPC_LR: ppc->spr[SPR_LR] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_CTR: ppc->spr[SPR_CTR] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_XER: set_xer(ppc, info->i); break; - case CPUINFO_INT_REGISTER + PPC_SRR0: ppc->spr[SPROEA_SRR0] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SRR1: ppc->spr[SPROEA_SRR1] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SPRG0: ppc->spr[SPROEA_SPRG0] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SPRG1: ppc->spr[SPROEA_SPRG1] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SPRG2: ppc->spr[SPROEA_SPRG2] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SPRG3: ppc->spr[SPROEA_SPRG3] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SDR1: ppc->spr[SPROEA_SDR1] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_EXIER: ppc->dcr[DCR4XX_EXIER] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_EXISR: ppc->dcr[DCR4XX_EXISR] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_EVPR: ppc->spr[SPR4XX_EVPR] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_IOCR: ppc->dcr[DCR4XX_IOCR] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_TBL: set_timebase(ppc, (get_timebase(ppc) & ~U64(0x00ffffff00000000)) | info->i); break; - case CPUINFO_INT_REGISTER + PPC_TBH: set_timebase(ppc, (get_timebase(ppc) & ~U64(0x00000000ffffffff)) | ((UINT64)(ppc->param1 & 0x00ffffff) << 32)); break; - case CPUINFO_INT_REGISTER + PPC_DEC: set_decrementer(ppc, info->i); break; - - case CPUINFO_INT_REGISTER + PPC_SR0: ppc->sr[0] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR1: ppc->sr[1] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR2: ppc->sr[2] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR3: ppc->sr[3] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR4: ppc->sr[4] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR5: ppc->sr[5] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR6: ppc->sr[6] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR7: ppc->sr[7] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR8: ppc->sr[8] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR9: ppc->sr[9] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR10: ppc->sr[10] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR11: ppc->sr[11] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR12: ppc->sr[12] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR13: ppc->sr[13] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR14: ppc->sr[14] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_SR15: ppc->sr[15] = info->i; break; - - case CPUINFO_INT_REGISTER + PPC_R0: ppc->r[0] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R1: ppc->r[1] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R2: ppc->r[2] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R3: ppc->r[3] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R4: ppc->r[4] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R5: ppc->r[5] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R6: ppc->r[6] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R7: ppc->r[7] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R8: ppc->r[8] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R9: ppc->r[9] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R10: ppc->r[10] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R11: ppc->r[11] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R12: ppc->r[12] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R13: ppc->r[13] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R14: ppc->r[14] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R15: ppc->r[15] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R16: ppc->r[16] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R17: ppc->r[17] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R18: ppc->r[18] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R19: ppc->r[19] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R20: ppc->r[20] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R21: ppc->r[21] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R22: ppc->r[22] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R23: ppc->r[23] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R24: ppc->r[24] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R25: ppc->r[25] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R26: ppc->r[26] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R27: ppc->r[27] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R28: ppc->r[28] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R29: ppc->r[29] = info->i; break; - case CPUINFO_INT_REGISTER + PPC_R30: ppc->r[30] = info->i; break; - case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + PPC_R31: ppc->r[31] = info->i; break; - - case CPUINFO_INT_REGISTER + PPC_F0: ppc->f[0] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F1: ppc->f[1] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F2: ppc->f[2] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F3: ppc->f[3] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F4: ppc->f[4] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F5: ppc->f[5] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F6: ppc->f[6] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F7: ppc->f[7] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F8: ppc->f[8] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F9: ppc->f[9] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F10: ppc->f[10] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F11: ppc->f[11] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F12: ppc->f[12] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F13: ppc->f[13] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F14: ppc->f[14] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F15: ppc->f[15] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F16: ppc->f[16] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F17: ppc->f[17] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F18: ppc->f[18] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F19: ppc->f[19] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F20: ppc->f[20] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F21: ppc->f[21] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F22: ppc->f[22] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F23: ppc->f[23] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F24: ppc->f[24] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F25: ppc->f[25] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F26: ppc->f[26] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F27: ppc->f[27] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F28: ppc->f[28] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F29: ppc->f[29] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F30: ppc->f[30] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_F31: ppc->f[31] = *(double *)&info->i; break; - case CPUINFO_INT_REGISTER + PPC_FPSCR: ppc->fpscr = info->i; break; - } -} - - -/*------------------------------------------------- - ppccom_get_info - get information about - a PowerPC CPU --------------------------------------------------*/ - -void ppccom_get_info(powerpc_state *ppc, UINT32 state, cpuinfo *info) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: /* provided by core */ break; - case CPUINFO_INT_INPUT_LINES: info->i = 1; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 40; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 64; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_LOGADDR_WIDTH_PROGRAM: info->i = 32; break; - case CPUINFO_INT_PAGE_SHIFT_PROGRAM: info->i = POWERPC_MIN_PAGE_SHIFT;break; - - case CPUINFO_INT_INPUT_STATE + PPC_IRQ: info->i = ppc->irq_pending ? ASSERT_LINE : CLEAR_LINE; break; - - case CPUINFO_INT_PREVIOUSPC: /* optionally implemented */ break; - - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + PPC_PC: info->i = ppc->pc; break; - case CPUINFO_INT_REGISTER + PPC_MSR: info->i = ppc->msr; break; - case CPUINFO_INT_REGISTER + PPC_CR: info->i = get_cr(ppc); break; - case CPUINFO_INT_REGISTER + PPC_LR: info->i = ppc->spr[SPR_LR]; break; - case CPUINFO_INT_REGISTER + PPC_CTR: info->i = ppc->spr[SPR_CTR]; break; - case CPUINFO_INT_REGISTER + PPC_XER: info->i = get_xer(ppc); break; - case CPUINFO_INT_REGISTER + PPC_SRR0: info->i = ppc->spr[SPROEA_SRR0]; break; - case CPUINFO_INT_REGISTER + PPC_SRR1: info->i = ppc->spr[SPROEA_SRR1]; break; - case CPUINFO_INT_REGISTER + PPC_SPRG0: info->i = ppc->spr[SPROEA_SPRG0]; break; - case CPUINFO_INT_REGISTER + PPC_SPRG1: info->i = ppc->spr[SPROEA_SPRG1]; break; - case CPUINFO_INT_REGISTER + PPC_SPRG2: info->i = ppc->spr[SPROEA_SPRG2]; break; - case CPUINFO_INT_REGISTER + PPC_SPRG3: info->i = ppc->spr[SPROEA_SPRG3]; break; - case CPUINFO_INT_REGISTER + PPC_SDR1: info->i = ppc->spr[SPROEA_SDR1]; break; - case CPUINFO_INT_REGISTER + PPC_EXIER: info->i = ppc->dcr[DCR4XX_EXIER]; break; - case CPUINFO_INT_REGISTER + PPC_EXISR: info->i = ppc->dcr[DCR4XX_EXISR]; break; - case CPUINFO_INT_REGISTER + PPC_EVPR: info->i = ppc->spr[SPR4XX_EVPR]; break; - case CPUINFO_INT_REGISTER + PPC_IOCR: info->i = ppc->dcr[DCR4XX_IOCR]; break; - case CPUINFO_INT_REGISTER + PPC_TBH: info->i = get_timebase(ppc) >> 32; break; - case CPUINFO_INT_REGISTER + PPC_TBL: info->i = (UINT32)get_timebase(ppc); break; - case CPUINFO_INT_REGISTER + PPC_DEC: info->i = get_decrementer(ppc); break; - - case CPUINFO_INT_REGISTER + PPC_SR0: info->i = ppc->sr[0]; break; - case CPUINFO_INT_REGISTER + PPC_SR1: info->i = ppc->sr[1]; break; - case CPUINFO_INT_REGISTER + PPC_SR2: info->i = ppc->sr[2]; break; - case CPUINFO_INT_REGISTER + PPC_SR3: info->i = ppc->sr[3]; break; - case CPUINFO_INT_REGISTER + PPC_SR4: info->i = ppc->sr[4]; break; - case CPUINFO_INT_REGISTER + PPC_SR5: info->i = ppc->sr[5]; break; - case CPUINFO_INT_REGISTER + PPC_SR6: info->i = ppc->sr[6]; break; - case CPUINFO_INT_REGISTER + PPC_SR7: info->i = ppc->sr[7]; break; - case CPUINFO_INT_REGISTER + PPC_SR8: info->i = ppc->sr[8]; break; - case CPUINFO_INT_REGISTER + PPC_SR9: info->i = ppc->sr[9]; break; - case CPUINFO_INT_REGISTER + PPC_SR10: info->i = ppc->sr[10]; break; - case CPUINFO_INT_REGISTER + PPC_SR11: info->i = ppc->sr[11]; break; - case CPUINFO_INT_REGISTER + PPC_SR12: info->i = ppc->sr[12]; break; - case CPUINFO_INT_REGISTER + PPC_SR13: info->i = ppc->sr[13]; break; - case CPUINFO_INT_REGISTER + PPC_SR14: info->i = ppc->sr[14]; break; - case CPUINFO_INT_REGISTER + PPC_SR15: info->i = ppc->sr[15]; break; - - case CPUINFO_INT_REGISTER + PPC_R0: info->i = ppc->r[0]; break; - case CPUINFO_INT_REGISTER + PPC_R1: info->i = ppc->r[1]; break; - case CPUINFO_INT_REGISTER + PPC_R2: info->i = ppc->r[2]; break; - case CPUINFO_INT_REGISTER + PPC_R3: info->i = ppc->r[3]; break; - case CPUINFO_INT_REGISTER + PPC_R4: info->i = ppc->r[4]; break; - case CPUINFO_INT_REGISTER + PPC_R5: info->i = ppc->r[5]; break; - case CPUINFO_INT_REGISTER + PPC_R6: info->i = ppc->r[6]; break; - case CPUINFO_INT_REGISTER + PPC_R7: info->i = ppc->r[7]; break; - case CPUINFO_INT_REGISTER + PPC_R8: info->i = ppc->r[8]; break; - case CPUINFO_INT_REGISTER + PPC_R9: info->i = ppc->r[9]; break; - case CPUINFO_INT_REGISTER + PPC_R10: info->i = ppc->r[10]; break; - case CPUINFO_INT_REGISTER + PPC_R11: info->i = ppc->r[11]; break; - case CPUINFO_INT_REGISTER + PPC_R12: info->i = ppc->r[12]; break; - case CPUINFO_INT_REGISTER + PPC_R13: info->i = ppc->r[13]; break; - case CPUINFO_INT_REGISTER + PPC_R14: info->i = ppc->r[14]; break; - case CPUINFO_INT_REGISTER + PPC_R15: info->i = ppc->r[15]; break; - case CPUINFO_INT_REGISTER + PPC_R16: info->i = ppc->r[16]; break; - case CPUINFO_INT_REGISTER + PPC_R17: info->i = ppc->r[17]; break; - case CPUINFO_INT_REGISTER + PPC_R18: info->i = ppc->r[18]; break; - case CPUINFO_INT_REGISTER + PPC_R19: info->i = ppc->r[19]; break; - case CPUINFO_INT_REGISTER + PPC_R20: info->i = ppc->r[20]; break; - case CPUINFO_INT_REGISTER + PPC_R21: info->i = ppc->r[21]; break; - case CPUINFO_INT_REGISTER + PPC_R22: info->i = ppc->r[22]; break; - case CPUINFO_INT_REGISTER + PPC_R23: info->i = ppc->r[23]; break; - case CPUINFO_INT_REGISTER + PPC_R24: info->i = ppc->r[24]; break; - case CPUINFO_INT_REGISTER + PPC_R25: info->i = ppc->r[25]; break; - case CPUINFO_INT_REGISTER + PPC_R26: info->i = ppc->r[26]; break; - case CPUINFO_INT_REGISTER + PPC_R27: info->i = ppc->r[27]; break; - case CPUINFO_INT_REGISTER + PPC_R28: info->i = ppc->r[28]; break; - case CPUINFO_INT_REGISTER + PPC_R29: info->i = ppc->r[29]; break; - case CPUINFO_INT_REGISTER + PPC_R30: info->i = ppc->r[30]; break; - case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + PPC_R31: info->i = ppc->r[31]; break; - - case CPUINFO_INT_REGISTER + PPC_F0: info->i = *(UINT64 *)&ppc->f[0]; break; - case CPUINFO_INT_REGISTER + PPC_F1: info->i = *(UINT64 *)&ppc->f[1]; break; - case CPUINFO_INT_REGISTER + PPC_F2: info->i = *(UINT64 *)&ppc->f[2]; break; - case CPUINFO_INT_REGISTER + PPC_F3: info->i = *(UINT64 *)&ppc->f[3]; break; - case CPUINFO_INT_REGISTER + PPC_F4: info->i = *(UINT64 *)&ppc->f[4]; break; - case CPUINFO_INT_REGISTER + PPC_F5: info->i = *(UINT64 *)&ppc->f[5]; break; - case CPUINFO_INT_REGISTER + PPC_F6: info->i = *(UINT64 *)&ppc->f[6]; break; - case CPUINFO_INT_REGISTER + PPC_F7: info->i = *(UINT64 *)&ppc->f[7]; break; - case CPUINFO_INT_REGISTER + PPC_F8: info->i = *(UINT64 *)&ppc->f[8]; break; - case CPUINFO_INT_REGISTER + PPC_F9: info->i = *(UINT64 *)&ppc->f[9]; break; - case CPUINFO_INT_REGISTER + PPC_F10: info->i = *(UINT64 *)&ppc->f[10]; break; - case CPUINFO_INT_REGISTER + PPC_F11: info->i = *(UINT64 *)&ppc->f[11]; break; - case CPUINFO_INT_REGISTER + PPC_F12: info->i = *(UINT64 *)&ppc->f[12]; break; - case CPUINFO_INT_REGISTER + PPC_F13: info->i = *(UINT64 *)&ppc->f[13]; break; - case CPUINFO_INT_REGISTER + PPC_F14: info->i = *(UINT64 *)&ppc->f[14]; break; - case CPUINFO_INT_REGISTER + PPC_F15: info->i = *(UINT64 *)&ppc->f[15]; break; - case CPUINFO_INT_REGISTER + PPC_F16: info->i = *(UINT64 *)&ppc->f[16]; break; - case CPUINFO_INT_REGISTER + PPC_F17: info->i = *(UINT64 *)&ppc->f[17]; break; - case CPUINFO_INT_REGISTER + PPC_F18: info->i = *(UINT64 *)&ppc->f[18]; break; - case CPUINFO_INT_REGISTER + PPC_F19: info->i = *(UINT64 *)&ppc->f[19]; break; - case CPUINFO_INT_REGISTER + PPC_F20: info->i = *(UINT64 *)&ppc->f[20]; break; - case CPUINFO_INT_REGISTER + PPC_F21: info->i = *(UINT64 *)&ppc->f[21]; break; - case CPUINFO_INT_REGISTER + PPC_F22: info->i = *(UINT64 *)&ppc->f[22]; break; - case CPUINFO_INT_REGISTER + PPC_F23: info->i = *(UINT64 *)&ppc->f[23]; break; - case CPUINFO_INT_REGISTER + PPC_F24: info->i = *(UINT64 *)&ppc->f[24]; break; - case CPUINFO_INT_REGISTER + PPC_F25: info->i = *(UINT64 *)&ppc->f[25]; break; - case CPUINFO_INT_REGISTER + PPC_F26: info->i = *(UINT64 *)&ppc->f[26]; break; - case CPUINFO_INT_REGISTER + PPC_F27: info->i = *(UINT64 *)&ppc->f[27]; break; - case CPUINFO_INT_REGISTER + PPC_F28: info->i = *(UINT64 *)&ppc->f[28]; break; - case CPUINFO_INT_REGISTER + PPC_F29: info->i = *(UINT64 *)&ppc->f[29]; break; - case CPUINFO_INT_REGISTER + PPC_F30: info->i = *(UINT64 *)&ppc->f[30]; break; - case CPUINFO_INT_REGISTER + PPC_F31: info->i = *(UINT64 *)&ppc->f[31]; break; - case CPUINFO_INT_REGISTER + PPC_FPSCR: info->i = ppc->fpscr; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: /* provided by core */ break; - case CPUINFO_FCT_INIT: /* provided by core */ break; - case CPUINFO_FCT_RESET: /* provided by core */ break; - case CPUINFO_FCT_EXIT: /* provided by core */ break; - case CPUINFO_FCT_EXECUTE: /* provided by core */ break; - case CPUINFO_FCT_TRANSLATE: /* provided by core */ break; - case CPUINFO_FCT_DISASSEMBLE: /* provided by core */ break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &ppc->icount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "ppc"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "PowerPC"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "2.0"); break; - case CPUINFO_STR_SOURCE_FILE: /* provided by core */ break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Aaron Giles"); break; - - case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break; - - case CPUINFO_STR_REGISTER + PPC_PC: sprintf(info->s, "PC: %08X", ppc->pc); break; - case CPUINFO_STR_REGISTER + PPC_MSR: sprintf(info->s, "MSR:%08X", ppc->msr); break; - case CPUINFO_STR_REGISTER + PPC_CR: sprintf(info->s, "CR: %08X", get_cr(ppc)); break; - case CPUINFO_STR_REGISTER + PPC_LR: sprintf(info->s, "LR: %08X", ppc->spr[SPR_LR]); break; - case CPUINFO_STR_REGISTER + PPC_CTR: sprintf(info->s, "CTR:%08X", ppc->spr[SPR_CTR]); break; - case CPUINFO_STR_REGISTER + PPC_XER: sprintf(info->s, "XER:%08X", get_xer(ppc)); break; - case CPUINFO_STR_REGISTER + PPC_SRR0: sprintf(info->s, "SRR0: %08X", ppc->spr[SPROEA_SRR0]); break; - case CPUINFO_STR_REGISTER + PPC_SRR1: sprintf(info->s, "SRR1: %08X", ppc->spr[SPROEA_SRR1]); break; - case CPUINFO_STR_REGISTER + PPC_SPRG0: sprintf(info->s, "SPRG0: %08X", ppc->spr[SPROEA_SPRG0]); break; - case CPUINFO_STR_REGISTER + PPC_SPRG1: sprintf(info->s, "SPRG1: %08X", ppc->spr[SPROEA_SPRG1]); break; - case CPUINFO_STR_REGISTER + PPC_SPRG2: sprintf(info->s, "SPRG2: %08X", ppc->spr[SPROEA_SPRG2]); break; - case CPUINFO_STR_REGISTER + PPC_SPRG3: sprintf(info->s, "SPRG3: %08X", ppc->spr[SPROEA_SPRG3]); break; - case CPUINFO_STR_REGISTER + PPC_SDR1: sprintf(info->s, "SDR1: %08X", ppc->spr[SPROEA_SDR1]); break; - case CPUINFO_STR_REGISTER + PPC_EXIER: sprintf(info->s, "EXIER: %08X", ppc->dcr[DCR4XX_EXIER]); break; - case CPUINFO_STR_REGISTER + PPC_EXISR: sprintf(info->s, "EXISR: %08X", ppc->dcr[DCR4XX_EXISR]); break; - case CPUINFO_STR_REGISTER + PPC_EVPR: sprintf(info->s, "EVPR: %08X", ppc->spr[SPR4XX_EVPR]); break; - case CPUINFO_STR_REGISTER + PPC_IOCR: sprintf(info->s, "IOCR: %08X", ppc->dcr[DCR4XX_EXISR]); break; - case CPUINFO_STR_REGISTER + PPC_TBH: sprintf(info->s, "TBH: %08X", (UINT32)(get_timebase(ppc) >> 32)); break; - case CPUINFO_STR_REGISTER + PPC_TBL: sprintf(info->s, "TBL: %08X", (UINT32)get_timebase(ppc)); break; - case CPUINFO_STR_REGISTER + PPC_DEC: sprintf(info->s, "DEC: %08X", get_decrementer(ppc)); break; - - case CPUINFO_STR_REGISTER + PPC_SR0: sprintf(info->s, "SR0: %08X", ppc->sr[0]); break; - case CPUINFO_STR_REGISTER + PPC_SR1: sprintf(info->s, "SR1: %08X", ppc->sr[1]); break; - case CPUINFO_STR_REGISTER + PPC_SR2: sprintf(info->s, "SR2: %08X", ppc->sr[2]); break; - case CPUINFO_STR_REGISTER + PPC_SR3: sprintf(info->s, "SR3: %08X", ppc->sr[3]); break; - case CPUINFO_STR_REGISTER + PPC_SR4: sprintf(info->s, "SR4: %08X", ppc->sr[4]); break; - case CPUINFO_STR_REGISTER + PPC_SR5: sprintf(info->s, "SR5: %08X", ppc->sr[5]); break; - case CPUINFO_STR_REGISTER + PPC_SR6: sprintf(info->s, "SR6: %08X", ppc->sr[6]); break; - case CPUINFO_STR_REGISTER + PPC_SR7: sprintf(info->s, "SR7: %08X", ppc->sr[7]); break; - case CPUINFO_STR_REGISTER + PPC_SR8: sprintf(info->s, "SR8: %08X", ppc->sr[8]); break; - case CPUINFO_STR_REGISTER + PPC_SR9: sprintf(info->s, "SR9: %08X", ppc->sr[9]); break; - case CPUINFO_STR_REGISTER + PPC_SR10: sprintf(info->s, "SR10: %08X", ppc->sr[10]); break; - case CPUINFO_STR_REGISTER + PPC_SR11: sprintf(info->s, "SR11: %08X", ppc->sr[11]); break; - case CPUINFO_STR_REGISTER + PPC_SR12: sprintf(info->s, "SR12: %08X", ppc->sr[12]); break; - case CPUINFO_STR_REGISTER + PPC_SR13: sprintf(info->s, "SR13: %08X", ppc->sr[13]); break; - case CPUINFO_STR_REGISTER + PPC_SR14: sprintf(info->s, "SR14: %08X", ppc->sr[14]); break; - case CPUINFO_STR_REGISTER + PPC_SR15: sprintf(info->s, "SR15: %08X", ppc->sr[15]); break; - - case CPUINFO_STR_REGISTER + PPC_R0: sprintf(info->s, "R0: %08X", ppc->r[0]); break; - case CPUINFO_STR_REGISTER + PPC_R1: sprintf(info->s, "R1: %08X", ppc->r[1]); break; - case CPUINFO_STR_REGISTER + PPC_R2: sprintf(info->s, "R2: %08X", ppc->r[2]); break; - case CPUINFO_STR_REGISTER + PPC_R3: sprintf(info->s, "R3: %08X", ppc->r[3]); break; - case CPUINFO_STR_REGISTER + PPC_R4: sprintf(info->s, "R4: %08X", ppc->r[4]); break; - case CPUINFO_STR_REGISTER + PPC_R5: sprintf(info->s, "R5: %08X", ppc->r[5]); break; - case CPUINFO_STR_REGISTER + PPC_R6: sprintf(info->s, "R6: %08X", ppc->r[6]); break; - case CPUINFO_STR_REGISTER + PPC_R7: sprintf(info->s, "R7: %08X", ppc->r[7]); break; - case CPUINFO_STR_REGISTER + PPC_R8: sprintf(info->s, "R8: %08X", ppc->r[8]); break; - case CPUINFO_STR_REGISTER + PPC_R9: sprintf(info->s, "R9: %08X", ppc->r[9]); break; - case CPUINFO_STR_REGISTER + PPC_R10: sprintf(info->s, "R10:%08X", ppc->r[10]); break; - case CPUINFO_STR_REGISTER + PPC_R11: sprintf(info->s, "R11:%08X", ppc->r[11]); break; - case CPUINFO_STR_REGISTER + PPC_R12: sprintf(info->s, "R12:%08X", ppc->r[12]); break; - case CPUINFO_STR_REGISTER + PPC_R13: sprintf(info->s, "R13:%08X", ppc->r[13]); break; - case CPUINFO_STR_REGISTER + PPC_R14: sprintf(info->s, "R14:%08X", ppc->r[14]); break; - case CPUINFO_STR_REGISTER + PPC_R15: sprintf(info->s, "R15:%08X", ppc->r[15]); break; - case CPUINFO_STR_REGISTER + PPC_R16: sprintf(info->s, "R16:%08X", ppc->r[16]); break; - case CPUINFO_STR_REGISTER + PPC_R17: sprintf(info->s, "R17:%08X", ppc->r[17]); break; - case CPUINFO_STR_REGISTER + PPC_R18: sprintf(info->s, "R18:%08X", ppc->r[18]); break; - case CPUINFO_STR_REGISTER + PPC_R19: sprintf(info->s, "R19:%08X", ppc->r[19]); break; - case CPUINFO_STR_REGISTER + PPC_R20: sprintf(info->s, "R20:%08X", ppc->r[20]); break; - case CPUINFO_STR_REGISTER + PPC_R21: sprintf(info->s, "R21:%08X", ppc->r[21]); break; - case CPUINFO_STR_REGISTER + PPC_R22: sprintf(info->s, "R22:%08X", ppc->r[22]); break; - case CPUINFO_STR_REGISTER + PPC_R23: sprintf(info->s, "R23:%08X", ppc->r[23]); break; - case CPUINFO_STR_REGISTER + PPC_R24: sprintf(info->s, "R24:%08X", ppc->r[24]); break; - case CPUINFO_STR_REGISTER + PPC_R25: sprintf(info->s, "R25:%08X", ppc->r[25]); break; - case CPUINFO_STR_REGISTER + PPC_R26: sprintf(info->s, "R26:%08X", ppc->r[26]); break; - case CPUINFO_STR_REGISTER + PPC_R27: sprintf(info->s, "R27:%08X", ppc->r[27]); break; - case CPUINFO_STR_REGISTER + PPC_R28: sprintf(info->s, "R28:%08X", ppc->r[28]); break; - case CPUINFO_STR_REGISTER + PPC_R29: sprintf(info->s, "R29:%08X", ppc->r[29]); break; - case CPUINFO_STR_REGISTER + PPC_R30: sprintf(info->s, "R30:%08X", ppc->r[30]); break; - case CPUINFO_STR_REGISTER + PPC_R31: sprintf(info->s, "R31:%08X", ppc->r[31]); break; - - case CPUINFO_STR_REGISTER + PPC_F0: sprintf(info->s, "F0: %12f", ppc->f[0]); break; - case CPUINFO_STR_REGISTER + PPC_F1: sprintf(info->s, "F1: %12f", ppc->f[1]); break; - case CPUINFO_STR_REGISTER + PPC_F2: sprintf(info->s, "F2: %12f", ppc->f[2]); break; - case CPUINFO_STR_REGISTER + PPC_F3: sprintf(info->s, "F3: %12f", ppc->f[3]); break; - case CPUINFO_STR_REGISTER + PPC_F4: sprintf(info->s, "F4: %12f", ppc->f[4]); break; - case CPUINFO_STR_REGISTER + PPC_F5: sprintf(info->s, "F5: %12f", ppc->f[5]); break; - case CPUINFO_STR_REGISTER + PPC_F6: sprintf(info->s, "F6: %12f", ppc->f[6]); break; - case CPUINFO_STR_REGISTER + PPC_F7: sprintf(info->s, "F7: %12f", ppc->f[7]); break; - case CPUINFO_STR_REGISTER + PPC_F8: sprintf(info->s, "F8: %12f", ppc->f[8]); break; - case CPUINFO_STR_REGISTER + PPC_F9: sprintf(info->s, "F9: %12f", ppc->f[9]); break; - case CPUINFO_STR_REGISTER + PPC_F10: sprintf(info->s, "F10:%12f", ppc->f[10]); break; - case CPUINFO_STR_REGISTER + PPC_F11: sprintf(info->s, "F11:%12f", ppc->f[11]); break; - case CPUINFO_STR_REGISTER + PPC_F12: sprintf(info->s, "F12:%12f", ppc->f[12]); break; - case CPUINFO_STR_REGISTER + PPC_F13: sprintf(info->s, "F13:%12f", ppc->f[13]); break; - case CPUINFO_STR_REGISTER + PPC_F14: sprintf(info->s, "F14:%12f", ppc->f[14]); break; - case CPUINFO_STR_REGISTER + PPC_F15: sprintf(info->s, "F15:%12f", ppc->f[15]); break; - case CPUINFO_STR_REGISTER + PPC_F16: sprintf(info->s, "F16:%12f", ppc->f[16]); break; - case CPUINFO_STR_REGISTER + PPC_F17: sprintf(info->s, "F17:%12f", ppc->f[17]); break; - case CPUINFO_STR_REGISTER + PPC_F18: sprintf(info->s, "F18:%12f", ppc->f[18]); break; - case CPUINFO_STR_REGISTER + PPC_F19: sprintf(info->s, "F19:%12f", ppc->f[19]); break; - case CPUINFO_STR_REGISTER + PPC_F20: sprintf(info->s, "F20:%12f", ppc->f[20]); break; - case CPUINFO_STR_REGISTER + PPC_F21: sprintf(info->s, "F21:%12f", ppc->f[21]); break; - case CPUINFO_STR_REGISTER + PPC_F22: sprintf(info->s, "F22:%12f", ppc->f[22]); break; - case CPUINFO_STR_REGISTER + PPC_F23: sprintf(info->s, "F23:%12f", ppc->f[23]); break; - case CPUINFO_STR_REGISTER + PPC_F24: sprintf(info->s, "F24:%12f", ppc->f[24]); break; - case CPUINFO_STR_REGISTER + PPC_F25: sprintf(info->s, "F25:%12f", ppc->f[25]); break; - case CPUINFO_STR_REGISTER + PPC_F26: sprintf(info->s, "F26:%12f", ppc->f[26]); break; - case CPUINFO_STR_REGISTER + PPC_F27: sprintf(info->s, "F27:%12f", ppc->f[27]); break; - case CPUINFO_STR_REGISTER + PPC_F28: sprintf(info->s, "F28:%12f", ppc->f[28]); break; - case CPUINFO_STR_REGISTER + PPC_F29: sprintf(info->s, "F29:%12f", ppc->f[29]); break; - case CPUINFO_STR_REGISTER + PPC_F30: sprintf(info->s, "F30:%12f", ppc->f[30]); break; - case CPUINFO_STR_REGISTER + PPC_F31: sprintf(info->s, "F31:%12f", ppc->f[31]); break; - case CPUINFO_STR_REGISTER + PPC_FPSCR: sprintf(info->s, "FPSCR:%08X", ppc->fpscr); break; - } -} - - - /*************************************************************************** OEA HELPERS ***************************************************************************/ @@ -1678,18 +2046,17 @@ void ppccom_get_info(powerpc_state *ppc, UINT32 state, cpuinfo *info) whenever a decrementer interrupt is generated -------------------------------------------------*/ -static TIMER_CALLBACK( decrementer_int_callback ) +TIMER_CALLBACK_MEMBER( ppc_device::decrementer_int_callback ) { - powerpc_state *ppc = (powerpc_state *)ptr; UINT64 cycles_until_next; /* set the decrementer IRQ state */ - ppc->irq_pending |= 0x02; + m_core->irq_pending |= 0x02; /* advance by another full rev */ - ppc->dec_zero_cycles += (UINT64)ppc->tb_divisor << 32; - cycles_until_next = ppc->dec_zero_cycles - ppc->device->total_cycles(); - ppc->decrementer_int_timer->adjust(ppc->device->cycles_to_attotime(cycles_until_next)); + m_dec_zero_cycles += (UINT64)m_tb_divisor << 32; + cycles_until_next = m_dec_zero_cycles - total_cycles(); + m_decrementer_int_timer->adjust(cycles_to_attotime(cycles_until_next)); } /*------------------------------------------------- @@ -1697,10 +2064,47 @@ static TIMER_CALLBACK( decrementer_int_callback ) for detecting datacache stores with dcbst -------------------------------------------------*/ -void ppc_set_dcstore_callback(device_t *device, ppc_dcstore_handler handler) +void ppc_device::ppc_set_dcstore_callback(ppc_dcstore_handler handler) +{ + m_dcstore_handler = handler; +} + + +void ppc_device::execute_set_input(int inputnum, int state) +{ + switch (inputnum) + { + case PPC_IRQ: + m_core->irq_pending = (m_core->irq_pending & ~1) | ((state != CLEAR_LINE) ? 1 : 0); + break; + } +} + + +void ppc4xx_device::execute_set_input(int inputnum, int state) { - powerpc_state *ppc = *(powerpc_state **)downcast<legacy_cpu_device *>(device)->token(); - ppc->dcstore_handler = handler; + switch (inputnum) + { + case PPC_IRQ_LINE_0: + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_EXT0, state); + break; + + case PPC_IRQ_LINE_1: + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_EXT1, state); + break; + + case PPC_IRQ_LINE_2: + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_EXT2, state); + break; + + case PPC_IRQ_LINE_3: + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_EXT3, state); + break; + + case PPC_IRQ_LINE_4: + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_EXT4, state); + break; + } } @@ -1713,38 +2117,38 @@ void ppc_set_dcstore_callback(device_t *device, ppc_dcstore_handler handler) IRQ line management -------------------------------------------------*/ -static void ppc4xx_set_irq_line(powerpc_state *ppc, UINT32 bitmask, int state) +void ppc_device::ppc4xx_set_irq_line(UINT32 bitmask, int state) { - UINT32 oldstate = ppc->irqstate; + UINT32 oldstate = m_irqstate; UINT32 levelmask; /* set or clear the appropriate bit */ if (state != CLEAR_LINE) - ppc->irqstate |= bitmask; + m_irqstate |= bitmask; else - ppc->irqstate &= ~bitmask; + m_irqstate &= ~bitmask; /* if the state changed to on, edge trigger the interrupt */ - if (((ppc->irqstate ^ oldstate) & bitmask) && (ppc->irqstate & bitmask)) - ppc->dcr[DCR4XX_EXISR] |= bitmask; + if (((m_irqstate ^ oldstate) & bitmask) && (m_irqstate & bitmask)) + m_dcr[DCR4XX_EXISR] |= bitmask; /* pass through all level-triggered interrupts */ levelmask = PPC4XX_IRQ_BIT_CRITICAL | PPC4XX_IRQ_BIT_SPUR | PPC4XX_IRQ_BIT_SPUT; levelmask |= PPC4XX_IRQ_BIT_JTAGR | PPC4XX_IRQ_BIT_JTAGT; levelmask |= PPC4XX_IRQ_BIT_DMA0 | PPC4XX_IRQ_BIT_DMA1 | PPC4XX_IRQ_BIT_DMA2 | PPC4XX_IRQ_BIT_DMA3; - if (!(ppc->dcr[DCR4XX_IOCR] & 0x80000000)) levelmask |= PPC4XX_IRQ_BIT_EXT0; - if (!(ppc->dcr[DCR4XX_IOCR] & 0x20000000)) levelmask |= PPC4XX_IRQ_BIT_EXT1; - if (!(ppc->dcr[DCR4XX_IOCR] & 0x08000000)) levelmask |= PPC4XX_IRQ_BIT_EXT2; - if (!(ppc->dcr[DCR4XX_IOCR] & 0x02000000)) levelmask |= PPC4XX_IRQ_BIT_EXT3; - if (!(ppc->dcr[DCR4XX_IOCR] & 0x00800000)) levelmask |= PPC4XX_IRQ_BIT_EXT4; - ppc->dcr[DCR4XX_EXISR] = (ppc->dcr[DCR4XX_EXISR] & ~levelmask) | (ppc->irqstate & levelmask); + if (!(m_dcr[DCR4XX_IOCR] & 0x80000000)) levelmask |= PPC4XX_IRQ_BIT_EXT0; + if (!(m_dcr[DCR4XX_IOCR] & 0x20000000)) levelmask |= PPC4XX_IRQ_BIT_EXT1; + if (!(m_dcr[DCR4XX_IOCR] & 0x08000000)) levelmask |= PPC4XX_IRQ_BIT_EXT2; + if (!(m_dcr[DCR4XX_IOCR] & 0x02000000)) levelmask |= PPC4XX_IRQ_BIT_EXT3; + if (!(m_dcr[DCR4XX_IOCR] & 0x00800000)) levelmask |= PPC4XX_IRQ_BIT_EXT4; + m_dcr[DCR4XX_EXISR] = (m_dcr[DCR4XX_EXISR] & ~levelmask) | (m_irqstate & levelmask); /* update the IRQ status */ - ppc->irq_pending = ((ppc->dcr[DCR4XX_EXISR] & ppc->dcr[DCR4XX_EXIER]) != 0); - if ((ppc->spr[SPR4XX_TCR] & PPC4XX_TCR_FIE) && (ppc->spr[SPR4XX_TSR] & PPC4XX_TSR_FIS)) - ppc->irq_pending = TRUE; - if ((ppc->spr[SPR4XX_TCR] & PPC4XX_TCR_PIE) && (ppc->spr[SPR4XX_TSR] & PPC4XX_TSR_PIS)) - ppc->irq_pending = TRUE; + m_core->irq_pending = ((m_dcr[DCR4XX_EXISR] & m_dcr[DCR4XX_EXIER]) != 0); + if ((m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_FIE) && (m_core->spr[SPR4XX_TSR] & PPC4XX_TSR_FIS)) + m_core->irq_pending = TRUE; + if ((m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_PIE) && (m_core->spr[SPR4XX_TSR] & PPC4XX_TSR_PIS)) + m_core->irq_pending = TRUE; } @@ -1753,9 +2157,9 @@ static void ppc4xx_set_irq_line(powerpc_state *ppc, UINT32 bitmask, int state) IRQ line state getter -------------------------------------------------*/ -static int ppc4xx_get_irq_line(powerpc_state *ppc, UINT32 bitmask) +int ppc_device::ppc4xx_get_irq_line(UINT32 bitmask) { - return (ppc->irqstate & bitmask) ? ASSERT_LINE : CLEAR_LINE; + return (m_irqstate & bitmask) ? ASSERT_LINE : CLEAR_LINE; } @@ -1764,7 +2168,7 @@ static int ppc4xx_get_irq_line(powerpc_state *ppc, UINT32 bitmask) state for each DMA channel -------------------------------------------------*/ -static void ppc4xx_dma_update_irq_states(powerpc_state *ppc) +void ppc_device::ppc4xx_dma_update_irq_states() { /* update the IRQ state for each DMA channel */ for (int dmachan = 0; dmachan < 4; dmachan++) @@ -1772,7 +2176,7 @@ static void ppc4xx_dma_update_irq_states(powerpc_state *ppc) bool irq_pending = false; // Channel interrupt enabled? - if ((ppc->dcr[DCR4XX_DMACR0 + 8 * dmachan] & PPC4XX_DMACR_CIE)) + if ((m_dcr[DCR4XX_DMACR0 + 8 * dmachan] & PPC4XX_DMACR_CIE)) { // Terminal count and end-of-transfer status bits int bitmask = 0x11 << (27 - dmachan); @@ -1791,10 +2195,10 @@ static void ppc4xx_dma_update_irq_states(powerpc_state *ppc) break; } - irq_pending = (ppc->dcr[DCR4XX_DMASR] & bitmask) != 0; + irq_pending = (m_dcr[DCR4XX_DMASR] & bitmask) != 0; } - ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_DMA(dmachan), irq_pending ? ASSERT_LINE : CLEAR_LINE); + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_DMA(dmachan), irq_pending ? ASSERT_LINE : CLEAR_LINE); } } @@ -1805,9 +2209,9 @@ static void ppc4xx_dma_update_irq_states(powerpc_state *ppc) to do so -------------------------------------------------*/ -static int ppc4xx_dma_decrement_count(powerpc_state *ppc, int dmachan) +int ppc_device::ppc4xx_dma_decrement_count(int dmachan) { - UINT32 *dmaregs = &ppc->dcr[8 * dmachan]; + UINT32 *dmaregs = &m_dcr[8 * dmachan]; /* decrement the counter */ dmaregs[DCR4XX_DMACT0]--; @@ -1826,34 +2230,34 @@ static int ppc4xx_dma_decrement_count(powerpc_state *ppc, int dmachan) switch (dmachan) { case 0: - ppc->dcr[DCR4XX_DMASR] |= 0x00080000; + m_dcr[DCR4XX_DMASR] |= 0x00080000; break; case 1: case 2: case 3: - ppc->dcr[DCR4XX_DMASR] |= 1 << (7 - dmachan); + m_dcr[DCR4XX_DMASR] |= 1 << (7 - dmachan); break; } - ppc4xx_dma_update_irq_states(ppc); + ppc4xx_dma_update_irq_states(); INT64 numdata = dmaregs[DCR4XX_DMACT0]; if (numdata == 0) numdata = 65536; - INT64 time = (numdata * 1000000) / ppc->buffered_dma_rate[dmachan]; + INT64 time = (numdata * 1000000) / m_buffered_dma_rate[dmachan]; - ppc->buffered_dma_timer[dmachan]->adjust(attotime::from_usec(time), dmachan); + m_buffered_dma_timer[dmachan]->adjust(attotime::from_usec(time), dmachan); } else { /* set the complete bit and handle interrupts */ - ppc->dcr[DCR4XX_DMASR] |= 1 << (31 - dmachan); - // ppc->dcr[DCR4XX_DMASR] |= 1 << (27 - dmachan); - ppc4xx_dma_update_irq_states(ppc); + m_dcr[DCR4XX_DMASR] |= 1 << (31 - dmachan); + // m_dcr[DCR4XX_DMASR] |= 1 << (27 - dmachan); + ppc4xx_dma_update_irq_states(); - ppc->buffered_dma_timer[dmachan]->adjust(attotime::never, FALSE); + m_buffered_dma_timer[dmachan]->adjust(attotime::never, FALSE); } return TRUE; } @@ -1864,13 +2268,12 @@ static int ppc4xx_dma_decrement_count(powerpc_state *ppc, int dmachan) when buffered DMA transfer is ready -------------------------------------------------*/ -static TIMER_CALLBACK( ppc4xx_buffered_dma_callback ) +TIMER_CALLBACK_MEMBER( ppc_device::ppc4xx_buffered_dma_callback ) { - powerpc_state *ppc = (powerpc_state *)ptr; int dmachan = param; static const UINT8 dma_transfer_width[4] = { 1, 2, 4, 16 }; - UINT32 *dmaregs = &ppc->dcr[8 * dmachan]; + UINT32 *dmaregs = &m_dcr[8 * dmachan]; INT32 destinc; UINT8 width; @@ -1888,11 +2291,11 @@ static TIMER_CALLBACK( ppc4xx_buffered_dma_callback ) do { UINT8 data = 0; - if (ppc->ext_dma_read_handler[dmachan] != NULL) - data = (*ppc->ext_dma_read_handler[dmachan])(ppc->device, 1); - ppc->program->write_byte(dmaregs[DCR4XX_DMADA0], data); + if (m_ext_dma_read_handler[dmachan] != NULL) + data = (*m_ext_dma_read_handler[dmachan])(this, 1); + m_program->write_byte(dmaregs[DCR4XX_DMADA0], data); dmaregs[DCR4XX_DMADA0] += destinc; - } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); + } while (!ppc4xx_dma_decrement_count(dmachan)); break; /* word transfer */ @@ -1900,11 +2303,11 @@ static TIMER_CALLBACK( ppc4xx_buffered_dma_callback ) do { UINT16 data = 0; - if (ppc->ext_dma_read_handler[dmachan] != NULL) - data = (*ppc->ext_dma_read_handler[dmachan])(ppc->device, 2); - ppc->program->write_word(dmaregs[DCR4XX_DMADA0], data); + if (m_ext_dma_read_handler[dmachan] != NULL) + data = (*m_ext_dma_read_handler[dmachan])(this, 2); + m_program->write_word(dmaregs[DCR4XX_DMADA0], data); dmaregs[DCR4XX_DMADA0] += destinc; - } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); + } while (!ppc4xx_dma_decrement_count(dmachan)); break; /* dword transfer */ @@ -1912,11 +2315,11 @@ static TIMER_CALLBACK( ppc4xx_buffered_dma_callback ) do { UINT32 data = 0; - if (ppc->ext_dma_read_handler[dmachan] != NULL) - data = (*ppc->ext_dma_read_handler[dmachan])(ppc->device, 4); - ppc->program->write_dword(dmaregs[DCR4XX_DMADA0], data); + if (m_ext_dma_read_handler[dmachan] != NULL) + data = (*m_ext_dma_read_handler[dmachan])(this, 4); + m_program->write_dword(dmaregs[DCR4XX_DMADA0], data); dmaregs[DCR4XX_DMADA0] += destinc; - } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); + } while (!ppc4xx_dma_decrement_count(dmachan)); break; } } @@ -1931,33 +2334,33 @@ static TIMER_CALLBACK( ppc4xx_buffered_dma_callback ) case 1: do { - UINT8 data = ppc->program->read_byte(dmaregs[DCR4XX_DMADA0]); - if (ppc->ext_dma_write_handler[dmachan] != NULL) - (*ppc->ext_dma_write_handler[dmachan])(ppc->device, 1, data); + UINT8 data = m_program->read_byte(dmaregs[DCR4XX_DMADA0]); + if (m_ext_dma_write_handler[dmachan] != NULL) + (*m_ext_dma_write_handler[dmachan])(this, 1, data); dmaregs[DCR4XX_DMADA0] += destinc; - } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); + } while (!ppc4xx_dma_decrement_count(dmachan)); break; /* word transfer */ case 2: do { - UINT16 data = ppc->program->read_word(dmaregs[DCR4XX_DMADA0]); - if (ppc->ext_dma_write_handler[dmachan] != NULL) - (*ppc->ext_dma_write_handler[dmachan])(ppc->device, 2, data); + UINT16 data = m_program->read_word(dmaregs[DCR4XX_DMADA0]); + if (m_ext_dma_write_handler[dmachan] != NULL) + (*m_ext_dma_write_handler[dmachan])(this, 2, data); dmaregs[DCR4XX_DMADA0] += destinc; - } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); + } while (!ppc4xx_dma_decrement_count(dmachan)); break; /* dword transfer */ case 4: do { - UINT32 data = ppc->program->read_dword(dmaregs[DCR4XX_DMADA0]); - if (ppc->ext_dma_write_handler[dmachan] != NULL) - (*ppc->ext_dma_write_handler[dmachan])(ppc->device, 4, data); + UINT32 data = m_program->read_dword(dmaregs[DCR4XX_DMADA0]); + if (m_ext_dma_write_handler[dmachan] != NULL) + (*m_ext_dma_write_handler[dmachan])(this, 4, data); dmaregs[DCR4XX_DMADA0] += destinc; - } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); + } while (!ppc4xx_dma_decrement_count(dmachan)); break; } } @@ -1969,9 +2372,9 @@ static TIMER_CALLBACK( ppc4xx_buffered_dma_callback ) to send to a peripheral -------------------------------------------------*/ -static int ppc4xx_dma_fetch_transmit_byte(powerpc_state *ppc, int dmachan, UINT8 *byte) +int ppc_device::ppc4xx_dma_fetch_transmit_byte(int dmachan, UINT8 *byte) { - UINT32 *dmaregs = &ppc->dcr[8 * dmachan]; + UINT32 *dmaregs = &m_dcr[8 * dmachan]; /* if the channel is not enabled, fail */ if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CE)) @@ -1982,8 +2385,8 @@ static int ppc4xx_dma_fetch_transmit_byte(powerpc_state *ppc, int dmachan, UINT8 return FALSE; /* fetch the data */ - *byte = ppc->program->read_byte(dmaregs[DCR4XX_DMADA0]++); - ppc4xx_dma_decrement_count(ppc, dmachan); + *byte = m_program->read_byte(dmaregs[DCR4XX_DMADA0]++); + ppc4xx_dma_decrement_count(dmachan); return TRUE; } @@ -1993,9 +2396,9 @@ static int ppc4xx_dma_fetch_transmit_byte(powerpc_state *ppc, int dmachan, UINT8 transmitted by a peripheral -------------------------------------------------*/ -static int ppc4xx_dma_handle_receive_byte(powerpc_state *ppc, int dmachan, UINT8 byte) +int ppc_device::ppc4xx_dma_handle_receive_byte(int dmachan, UINT8 byte) { - UINT32 *dmaregs = &ppc->dcr[8 * dmachan]; + UINT32 *dmaregs = &m_dcr[8 * dmachan]; /* if the channel is not enabled, fail */ if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CE)) @@ -2006,8 +2409,8 @@ static int ppc4xx_dma_handle_receive_byte(powerpc_state *ppc, int dmachan, UINT8 return FALSE; /* store the data */ - ppc->program->write_byte(dmaregs[DCR4XX_DMADA0]++, byte); - ppc4xx_dma_decrement_count(ppc, dmachan); + m_program->write_byte(dmaregs[DCR4XX_DMADA0]++, byte); + ppc4xx_dma_decrement_count(dmachan); return TRUE; } @@ -2017,10 +2420,10 @@ static int ppc4xx_dma_handle_receive_byte(powerpc_state *ppc, int dmachan, UINT8 if one is pending -------------------------------------------------*/ -static void ppc4xx_dma_exec(powerpc_state *ppc, int dmachan) +void ppc_device::ppc4xx_dma_exec(int dmachan) { static const UINT8 dma_transfer_width[4] = { 1, 2, 4, 16 }; - UINT32 *dmaregs = &ppc->dcr[8 * dmachan]; + UINT32 *dmaregs = &m_dcr[8 * dmachan]; INT32 destinc, srcinc; UINT8 width; @@ -2048,14 +2451,14 @@ static void ppc4xx_dma_exec(powerpc_state *ppc, int dmachan) INT64 time; if (numdata > 100) { - time = (numdata * 1000000) / ppc->buffered_dma_rate[dmachan]; + time = (numdata * 1000000) / m_buffered_dma_rate[dmachan]; } else { time = 0; // let very short transfers occur instantly } - ppc->buffered_dma_timer[dmachan]->adjust(attotime::from_usec(time), dmachan); + m_buffered_dma_timer[dmachan]->adjust(attotime::from_usec(time), dmachan); } else /* buffered DMA with internal peripheral (SPU) */ { @@ -2080,41 +2483,41 @@ static void ppc4xx_dma_exec(powerpc_state *ppc, int dmachan) case 1: do { - ppc->program->write_byte(dmaregs[DCR4XX_DMADA0], ppc->program->read_byte(dmaregs[DCR4XX_DMASA0])); + m_program->write_byte(dmaregs[DCR4XX_DMADA0], m_program->read_byte(dmaregs[DCR4XX_DMASA0])); dmaregs[DCR4XX_DMASA0] += srcinc; dmaregs[DCR4XX_DMADA0] += destinc; - } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); + } while (!ppc4xx_dma_decrement_count(dmachan)); break; /* word transfer */ case 2: do { - ppc->program->write_word(dmaregs[DCR4XX_DMADA0], ppc->program->read_word(dmaregs[DCR4XX_DMASA0])); + m_program->write_word(dmaregs[DCR4XX_DMADA0], m_program->read_word(dmaregs[DCR4XX_DMASA0])); dmaregs[DCR4XX_DMASA0] += srcinc; dmaregs[DCR4XX_DMADA0] += destinc; - } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); + } while (!ppc4xx_dma_decrement_count(dmachan)); break; /* dword transfer */ case 4: do { - ppc->program->write_dword(dmaregs[DCR4XX_DMADA0], ppc->program->read_dword(dmaregs[DCR4XX_DMASA0])); + m_program->write_dword(dmaregs[DCR4XX_DMADA0], m_program->read_dword(dmaregs[DCR4XX_DMASA0])); dmaregs[DCR4XX_DMASA0] += srcinc; dmaregs[DCR4XX_DMADA0] += destinc; - } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); + } while (!ppc4xx_dma_decrement_count(dmachan)); break; /* 16-byte transfer */ case 16: do { - ppc->program->write_qword(dmaregs[DCR4XX_DMADA0], ppc->program->read_qword(dmaregs[DCR4XX_DMASA0])); - ppc->program->write_qword(dmaregs[DCR4XX_DMADA0] + 8, ppc->program->read_qword(dmaregs[DCR4XX_DMASA0] + 8)); + m_program->write_qword(dmaregs[DCR4XX_DMADA0], m_program->read_qword(dmaregs[DCR4XX_DMASA0])); + m_program->write_qword(dmaregs[DCR4XX_DMADA0] + 8, m_program->read_qword(dmaregs[DCR4XX_DMASA0] + 8)); dmaregs[DCR4XX_DMASA0] += srcinc; dmaregs[DCR4XX_DMADA0] += destinc; - } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); + } while (!ppc4xx_dma_decrement_count(dmachan)); break; } break; @@ -2131,29 +2534,27 @@ static void ppc4xx_dma_exec(powerpc_state *ppc, int dmachan) ppc4xx_fit_callback - FIT timer callback -------------------------------------------------*/ -static TIMER_CALLBACK( ppc4xx_fit_callback ) +TIMER_CALLBACK_MEMBER( ppc_device::ppc4xx_fit_callback ) { - powerpc_state *ppc = (powerpc_state *)ptr; - /* if this is a real callback and we are enabled, signal an interrupt */ if (param) { - ppc->spr[SPR4XX_TSR] |= PPC4XX_TSR_FIS; - ppc4xx_set_irq_line(ppc, 0, 0); + m_core->spr[SPR4XX_TSR] |= PPC4XX_TSR_FIS; + ppc4xx_set_irq_line(0, 0); } /* update ourself for the next interval if we are enabled */ - if (ppc->spr[SPR4XX_TCR] & PPC4XX_TCR_FIE) + if (m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_FIE) { - UINT32 timebase = get_timebase(ppc); - UINT32 interval = 0x200 << (4 * ((ppc->spr[SPR4XX_TCR] & PPC4XX_TCR_FP_MASK) >> 24)); + UINT32 timebase = get_timebase(); + UINT32 interval = 0x200 << (4 * ((m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_FP_MASK) >> 24)); UINT32 target = (timebase + interval) & ~(interval - 1); - ppc->fit_timer->adjust(ppc->device->cycles_to_attotime((target + 1 - timebase) / ppc->tb_divisor), TRUE); + m_fit_timer->adjust(cycles_to_attotime((target + 1 - timebase) / m_tb_divisor), TRUE); } /* otherwise, turn ourself off */ else - ppc->fit_timer->adjust(attotime::never, FALSE); + m_fit_timer->adjust(attotime::never, FALSE); } @@ -2161,30 +2562,28 @@ static TIMER_CALLBACK( ppc4xx_fit_callback ) ppc4xx_pit_callback - PIT timer callback -------------------------------------------------*/ -static TIMER_CALLBACK( ppc4xx_pit_callback ) +TIMER_CALLBACK_MEMBER( ppc_device::ppc4xx_pit_callback ) { - powerpc_state *ppc = (powerpc_state *)ptr; - /* if this is a real callback and we are enabled, signal an interrupt */ if (param) { - ppc->spr[SPR4XX_TSR] |= PPC4XX_TSR_PIS; - ppc4xx_set_irq_line(ppc, 0, 0); + m_core->spr[SPR4XX_TSR] |= PPC4XX_TSR_PIS; + ppc4xx_set_irq_line(0, 0); } /* update ourself for the next interval if we are enabled and we are either being forced to update, or we are in auto-reload mode */ - if ((ppc->spr[SPR4XX_TCR] & PPC4XX_TCR_PIE) && ppc->pit_reload != 0 && (!param || (ppc->spr[SPR4XX_TCR] & PPC4XX_TCR_ARE))) + if ((m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_PIE) && m_pit_reload != 0 && (!param || (m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_ARE))) { - UINT32 timebase = get_timebase(ppc); - UINT32 interval = ppc->pit_reload; + UINT32 timebase = get_timebase(); + UINT32 interval = m_pit_reload; UINT32 target = timebase + interval; - ppc->pit_timer->adjust(ppc->device->cycles_to_attotime((target + 1 - timebase) / ppc->tb_divisor), TRUE); + m_pit_timer->adjust(cycles_to_attotime((target + 1 - timebase) / m_tb_divisor), TRUE); } /* otherwise, turn ourself off */ else - ppc->pit_timer->adjust(attotime::never, FALSE); + m_pit_timer->adjust(attotime::never, FALSE); } @@ -2193,31 +2592,31 @@ static TIMER_CALLBACK( ppc4xx_pit_callback ) state for the SPU -------------------------------------------------*/ -static void ppc4xx_spu_update_irq_states(powerpc_state *ppc) +void ppc_device::ppc4xx_spu_update_irq_states() { /* check for receive buffer full interrupt */ - if ((ppc->spu.regs[SPU4XX_RX_COMMAND] & 0x60) == 0x20 && (ppc->spu.regs[SPU4XX_LINE_STATUS] & 0x80)) - ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_SPUR, ASSERT_LINE); + if ((m_spu.regs[SPU4XX_RX_COMMAND] & 0x60) == 0x20 && (m_spu.regs[SPU4XX_LINE_STATUS] & 0x80)) + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_SPUR, ASSERT_LINE); /* check for receive error interrupt */ - else if ((ppc->spu.regs[SPU4XX_RX_COMMAND] & 0x10) && (ppc->spu.regs[SPU4XX_LINE_STATUS] & 0x78)) - ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_SPUR, ASSERT_LINE); + else if ((m_spu.regs[SPU4XX_RX_COMMAND] & 0x10) && (m_spu.regs[SPU4XX_LINE_STATUS] & 0x78)) + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_SPUR, ASSERT_LINE); /* clear otherwise */ else - ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_SPUR, CLEAR_LINE); + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_SPUR, CLEAR_LINE); /* check for transmit buffer empty interrupt */ - if ((ppc->spu.regs[SPU4XX_TX_COMMAND] & 0x60) == 0x20 && (ppc->spu.regs[SPU4XX_LINE_STATUS] & 0x04)) - ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_SPUT, ASSERT_LINE); + if ((m_spu.regs[SPU4XX_TX_COMMAND] & 0x60) == 0x20 && (m_spu.regs[SPU4XX_LINE_STATUS] & 0x04)) + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_SPUT, ASSERT_LINE); /* check for shift register empty interrupt */ - else if ((ppc->spu.regs[SPU4XX_TX_COMMAND] & 0x10) && (ppc->spu.regs[SPU4XX_LINE_STATUS] & 0x02)) - ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_SPUT, ASSERT_LINE); + else if ((m_spu.regs[SPU4XX_TX_COMMAND] & 0x10) && (m_spu.regs[SPU4XX_LINE_STATUS] & 0x02)) + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_SPUT, ASSERT_LINE); /* clear otherwise */ else - ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_SPUT, CLEAR_LINE); + ppc4xx_set_irq_line(PPC4XX_IRQ_BIT_SPUT, CLEAR_LINE); } @@ -2225,18 +2624,18 @@ static void ppc4xx_spu_update_irq_states(powerpc_state *ppc) ppc4xx_spu_rx_data - serial port data receive -------------------------------------------------*/ -static void ppc4xx_spu_rx_data(powerpc_state *ppc, UINT8 data) +void ppc_device::ppc4xx_spu_rx_data(UINT8 data) { UINT32 new_rxin; /* fail if we are going to overflow */ - new_rxin = (ppc->spu.rxin + 1) % ARRAY_LENGTH(ppc->spu.rxbuffer); - if (new_rxin == ppc->spu.rxout) + new_rxin = (m_spu.rxin + 1) % ARRAY_LENGTH(m_spu.rxbuffer); + if (new_rxin == m_spu.rxout) fatalerror("ppc4xx_spu_rx_data: buffer overrun!\n"); /* store the data and accept the new in index */ - ppc->spu.rxbuffer[ppc->spu.rxin] = data; - ppc->spu.rxin = new_rxin; + m_spu.rxbuffer[m_spu.rxin] = data; + m_spu.rxin = new_rxin; } @@ -2245,25 +2644,25 @@ static void ppc4xx_spu_rx_data(powerpc_state *ppc, UINT8 data) the transmit/receive timer -------------------------------------------------*/ -static void ppc4xx_spu_timer_reset(powerpc_state *ppc) +void ppc_device::ppc4xx_spu_timer_reset() { - UINT8 enabled = (ppc->spu.regs[SPU4XX_RX_COMMAND] | ppc->spu.regs[SPU4XX_TX_COMMAND]) & 0x80; + UINT8 enabled = (m_spu.regs[SPU4XX_RX_COMMAND] | m_spu.regs[SPU4XX_TX_COMMAND]) & 0x80; /* if we're enabled, reset at the current baud rate */ if (enabled) { - attotime clockperiod = attotime::from_hz((ppc->dcr[DCR4XX_IOCR] & 0x02) ? 3686400 : 33333333); - int divisor = ((ppc->spu.regs[SPU4XX_BAUD_DIVISOR_H] * 256 + ppc->spu.regs[SPU4XX_BAUD_DIVISOR_L]) & 0xfff) + 1; - int bpc = 7 + ((ppc->spu.regs[SPU4XX_CONTROL] & 8) >> 3) + 1 + (ppc->spu.regs[SPU4XX_CONTROL] & 1); + attotime clockperiod = attotime::from_hz((m_dcr[DCR4XX_IOCR] & 0x02) ? 3686400 : 33333333); + int divisor = ((m_spu.regs[SPU4XX_BAUD_DIVISOR_H] * 256 + m_spu.regs[SPU4XX_BAUD_DIVISOR_L]) & 0xfff) + 1; + int bpc = 7 + ((m_spu.regs[SPU4XX_CONTROL] & 8) >> 3) + 1 + (m_spu.regs[SPU4XX_CONTROL] & 1); attotime charperiod = clockperiod * (divisor * 16 * bpc); - ppc->spu.timer->adjust(charperiod, 0, charperiod); + m_spu.timer->adjust(charperiod, 0, charperiod); if (PRINTF_SPU) printf("ppc4xx_spu_timer_reset: baud rate = %.0f\n", ATTOSECONDS_TO_HZ(charperiod.attoseconds) * bpc); } /* otherwise, disable the timer */ else - ppc->spu.timer->adjust(attotime::never); + m_spu.timer->adjust(attotime::never); } @@ -2272,69 +2671,67 @@ static void ppc4xx_spu_timer_reset(powerpc_state *ppc) timer -------------------------------------------------*/ -static TIMER_CALLBACK( ppc4xx_spu_callback ) +TIMER_CALLBACK_MEMBER( ppc_device::ppc4xx_spu_callback ) { - powerpc_state *ppc = (powerpc_state *)ptr; - /* transmit enabled? */ - if (ppc->spu.regs[SPU4XX_TX_COMMAND] & 0x80) + if (m_spu.regs[SPU4XX_TX_COMMAND] & 0x80) { - int operation = (ppc->spu.regs[SPU4XX_TX_COMMAND] >> 5) & 3; + int operation = (m_spu.regs[SPU4XX_TX_COMMAND] >> 5) & 3; /* if we have data to transmit, do it now */ - if (!(ppc->spu.regs[SPU4XX_LINE_STATUS] & 0x04)) + if (!(m_spu.regs[SPU4XX_LINE_STATUS] & 0x04)) { /* if we have a transmit handler, send it that way */ - if (ppc->spu.tx_handler != NULL) - (*ppc->spu.tx_handler)(ppc->device, ppc->spu.txbuf); + if (m_spu.tx_handler != NULL) + (*m_spu.tx_handler)(this, m_spu.txbuf); /* indicate that we have moved it to the shift register */ - ppc->spu.regs[SPU4XX_LINE_STATUS] |= 0x04; - ppc->spu.regs[SPU4XX_LINE_STATUS] &= ~0x02; + m_spu.regs[SPU4XX_LINE_STATUS] |= 0x04; + m_spu.regs[SPU4XX_LINE_STATUS] &= ~0x02; } /* otherwise, clear the shift register */ - else if (!(ppc->spu.regs[SPU4XX_LINE_STATUS] & 0x02)) - ppc->spu.regs[SPU4XX_LINE_STATUS] |= 0x02; + else if (!(m_spu.regs[SPU4XX_LINE_STATUS] & 0x02)) + m_spu.regs[SPU4XX_LINE_STATUS] |= 0x02; /* handle DMA */ - if (operation >= 2 && ppc4xx_dma_fetch_transmit_byte(ppc, operation, &ppc->spu.txbuf)) - ppc->spu.regs[SPU4XX_LINE_STATUS] &= ~0x04; + if (operation >= 2 && ppc4xx_dma_fetch_transmit_byte(operation, &m_spu.txbuf)) + m_spu.regs[SPU4XX_LINE_STATUS] &= ~0x04; } /* receive enabled? */ - if (ppc->spu.regs[SPU4XX_RX_COMMAND] & 0x80) - if (ppc->spu.rxout != ppc->spu.rxin) + if (m_spu.regs[SPU4XX_RX_COMMAND] & 0x80) + if (m_spu.rxout != m_spu.rxin) { - int operation = (ppc->spu.regs[SPU4XX_RX_COMMAND] >> 5) & 3; + int operation = (m_spu.regs[SPU4XX_RX_COMMAND] >> 5) & 3; UINT8 rxbyte; /* consume the byte and advance the out pointer */ - rxbyte = ppc->spu.rxbuffer[ppc->spu.rxout]; - ppc->spu.rxout = (ppc->spu.rxout + 1) % ARRAY_LENGTH(ppc->spu.rxbuffer); + rxbyte = m_spu.rxbuffer[m_spu.rxout]; + m_spu.rxout = (m_spu.rxout + 1) % ARRAY_LENGTH(m_spu.rxbuffer); /* if we're not full, copy data to the buffer and update the line status */ - if (!(ppc->spu.regs[SPU4XX_LINE_STATUS] & 0x80)) + if (!(m_spu.regs[SPU4XX_LINE_STATUS] & 0x80)) { - ppc->spu.rxbuf = rxbyte; - ppc->spu.regs[SPU4XX_LINE_STATUS] |= 0x80; + m_spu.rxbuf = rxbyte; + m_spu.regs[SPU4XX_LINE_STATUS] |= 0x80; } /* otherwise signal an overrun */ else { - ppc->spu.regs[SPU4XX_LINE_STATUS] |= 0x20; + m_spu.regs[SPU4XX_LINE_STATUS] |= 0x20; goto updateirq; } /* handle DMA */ - if (operation >= 2 && ppc4xx_dma_handle_receive_byte(ppc, operation, ppc->spu.rxbuf)) - ppc->spu.regs[SPU4XX_LINE_STATUS] &= ~0x80; + if (operation >= 2 && ppc4xx_dma_handle_receive_byte(operation, m_spu.rxbuf)) + m_spu.regs[SPU4XX_LINE_STATUS] &= ~0x80; } /* update the final IRQ states */ updateirq: - ppc4xx_spu_update_irq_states(ppc); + ppc4xx_spu_update_irq_states(); } @@ -2344,19 +2741,18 @@ updateirq: READ8_MEMBER( ppc4xx_device::ppc4xx_spu_r ) { - powerpc_state *ppc = *(powerpc_state **)downcast<legacy_cpu_device *>(this)->token(); UINT8 result = 0xff; switch (offset) { case SPU4XX_BUFFER: - result = ppc->spu.rxbuf; - ppc->spu.regs[SPU4XX_LINE_STATUS] &= ~0x80; + result = m_spu.rxbuf; + m_spu.regs[SPU4XX_LINE_STATUS] &= ~0x80; break; default: - if (offset < ARRAY_LENGTH(ppc->spu.regs)) - result = ppc->spu.regs[offset]; + if (offset < ARRAY_LENGTH(m_spu.regs)) + result = m_spu.regs[offset]; break; } if (PRINTF_SPU) @@ -2371,7 +2767,6 @@ READ8_MEMBER( ppc4xx_device::ppc4xx_spu_r ) WRITE8_MEMBER( ppc4xx_device::ppc4xx_spu_w ) { - powerpc_state *ppc = *(powerpc_state **)downcast<legacy_cpu_device *>(this)->token(); UINT8 oldstate, newstate; if (PRINTF_SPU) @@ -2380,50 +2775,50 @@ WRITE8_MEMBER( ppc4xx_device::ppc4xx_spu_w ) { /* clear error bits */ case SPU4XX_LINE_STATUS: - ppc->spu.regs[SPU4XX_LINE_STATUS] &= ~(data & 0xf8); - ppc4xx_spu_update_irq_states(ppc); + m_spu.regs[SPU4XX_LINE_STATUS] &= ~(data & 0xf8); + ppc4xx_spu_update_irq_states(); break; /* enable/disable the timer if one of these is enabled */ case SPU4XX_RX_COMMAND: case SPU4XX_TX_COMMAND: - oldstate = ppc->spu.regs[SPU4XX_RX_COMMAND] | ppc->spu.regs[SPU4XX_TX_COMMAND]; - ppc->spu.regs[offset] = data; - newstate = ppc->spu.regs[SPU4XX_RX_COMMAND] | ppc->spu.regs[SPU4XX_TX_COMMAND]; + oldstate = m_spu.regs[SPU4XX_RX_COMMAND] | m_spu.regs[SPU4XX_TX_COMMAND]; + m_spu.regs[offset] = data; + newstate = m_spu.regs[SPU4XX_RX_COMMAND] | m_spu.regs[SPU4XX_TX_COMMAND]; if ((oldstate ^ newstate) & 0x80) - ppc4xx_spu_timer_reset(ppc); - ppc4xx_spu_update_irq_states(ppc); + ppc4xx_spu_timer_reset(); + ppc4xx_spu_update_irq_states(); break; /* if the divisor changes, we need to update the timer */ case SPU4XX_BAUD_DIVISOR_H: case SPU4XX_BAUD_DIVISOR_L: - if (data != ppc->spu.regs[offset]) + if (data != m_spu.regs[offset]) { - ppc->spu.regs[offset] = data; - ppc4xx_spu_timer_reset(ppc); + m_spu.regs[offset] = data; + ppc4xx_spu_timer_reset(); } break; /* if the number of data bits or stop bits changes, we need to update the timer */ case SPU4XX_CONTROL: - oldstate = ppc->spu.regs[offset]; - ppc->spu.regs[offset] = data; + oldstate = m_spu.regs[offset]; + m_spu.regs[offset] = data; if ((oldstate ^ data) & 0x09) - ppc4xx_spu_timer_reset(ppc); + ppc4xx_spu_timer_reset(); break; break; case SPU4XX_BUFFER: /* write to the transmit buffer and mark it full */ - ppc->spu.txbuf = data; - ppc->spu.regs[SPU4XX_LINE_STATUS] &= ~0x04; + m_spu.txbuf = data; + m_spu.regs[SPU4XX_LINE_STATUS] &= ~0x04; break; default: - if (offset < ARRAY_LENGTH(ppc->spu.regs)) - ppc->spu.regs[offset] = data; + if (offset < ARRAY_LENGTH(m_spu.regs)) + m_spu.regs[offset] = data; break; } } @@ -2431,25 +2826,13 @@ WRITE8_MEMBER( ppc4xx_device::ppc4xx_spu_w ) /*------------------------------------------------- - internal_ppc4xx - internal address map for - the 4XX --------------------------------------------------*/ - -static ADDRESS_MAP_START( internal_ppc4xx, AS_PROGRAM, 32, ppc4xx_device ) - AM_RANGE(0x40000000, 0x4000000f) AM_READWRITE8(ppc4xx_spu_r, ppc4xx_spu_w, 0xffffffff) -ADDRESS_MAP_END - - - -/*------------------------------------------------- ppc4xx_spu_set_tx_handler - PowerPC 4XX- specific TX handler configuration -------------------------------------------------*/ -void ppc4xx_spu_set_tx_handler(device_t *device, ppc4xx_spu_tx_handler handler) +void ppc4xx_device::ppc4xx_spu_set_tx_handler(ppc4xx_spu_tx_handler handler) { - powerpc_state *ppc = *(powerpc_state **)downcast<legacy_cpu_device *>(device)->token(); - ppc->spu.tx_handler = handler; + m_spu.tx_handler = handler; } @@ -2458,10 +2841,9 @@ void ppc4xx_spu_set_tx_handler(device_t *device, ppc4xx_spu_tx_handler handler) specific serial byte receive -------------------------------------------------*/ -void ppc4xx_spu_receive_byte(device_t *device, UINT8 byteval) +void ppc4xx_device::ppc4xx_spu_receive_byte(UINT8 byteval) { - powerpc_state *ppc = *(powerpc_state **)downcast<legacy_cpu_device *>(device)->token(); - ppc4xx_spu_rx_data(ppc, byteval); + ppc4xx_spu_rx_data(byteval); } /*------------------------------------------------- @@ -2469,11 +2851,10 @@ void ppc4xx_spu_receive_byte(device_t *device, UINT8 byteval) specific external DMA read handler configuration -------------------------------------------------*/ -void ppc4xx_set_dma_read_handler(device_t *device, int channel, ppc4xx_dma_read_handler handler, int rate) +void ppc4xx_device::ppc4xx_set_dma_read_handler(int channel, ppc4xx_dma_read_handler handler, int rate) { - powerpc_state *ppc = *(powerpc_state **)downcast<legacy_cpu_device *>(device)->token(); - ppc->ext_dma_read_handler[channel] = handler; - ppc->buffered_dma_rate[channel] = rate; + m_ext_dma_read_handler[channel] = handler; + m_buffered_dma_rate[channel] = rate; } /*------------------------------------------------- @@ -2481,21 +2862,19 @@ void ppc4xx_set_dma_read_handler(device_t *device, int channel, ppc4xx_dma_read_ specific external DMA write handler configuration -------------------------------------------------*/ -void ppc4xx_set_dma_write_handler(device_t *device, int channel, ppc4xx_dma_write_handler handler, int rate) +void ppc4xx_device::ppc4xx_set_dma_write_handler(int channel, ppc4xx_dma_write_handler handler, int rate) { - powerpc_state *ppc = *(powerpc_state **)downcast<legacy_cpu_device *>(device)->token(); - ppc->ext_dma_write_handler[channel] = handler; - ppc->buffered_dma_rate[channel] = rate; + m_ext_dma_write_handler[channel] = handler; + m_buffered_dma_rate[channel] = rate; } /*------------------------------------------------- ppc4xx_set_dcr_read_handler -------------------------------------------------*/ -void ppc4xx_set_dcr_read_handler(device_t *device, read32_delegate dcr_read_func) +void ppc4xx_device::ppc4xx_set_dcr_read_handler(read32_delegate dcr_read_func) { - powerpc_state *ppc = *(powerpc_state **)downcast<legacy_cpu_device *>(device)->token(); - ppc->dcr_read_func = dcr_read_func; + m_dcr_read_func = dcr_read_func; } @@ -2503,61 +2882,8 @@ void ppc4xx_set_dcr_read_handler(device_t *device, read32_delegate dcr_read_func ppc4xx_set_dcr_write_handler -------------------------------------------------*/ -void ppc4xx_set_dcr_write_handler(device_t *device, write32_delegate dcr_write_func) -{ - powerpc_state *ppc = *(powerpc_state **)downcast<legacy_cpu_device *>(device)->token(); - ppc->dcr_write_func = dcr_write_func; -} - -/*------------------------------------------------- - ppc4xx_set_info - PowerPC 4XX-specific - information setter --------------------------------------------------*/ - -void ppc4xx_set_info(powerpc_state *ppc, UINT32 state, cpuinfo *info) +void ppc4xx_device::ppc4xx_set_dcr_write_handler(write32_delegate dcr_write_func) { - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_0: ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_EXT0, info->i); break; - case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_1: ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_EXT1, info->i); break; - case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_2: ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_EXT2, info->i); break; - case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_3: ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_EXT3, info->i); break; - case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_4: ppc4xx_set_irq_line(ppc, PPC4XX_IRQ_BIT_EXT4, info->i); break; - - /* --- everything else is handled generically --- */ - default: ppccom_set_info(ppc, state, info); break; - } + m_dcr_write_func = dcr_write_func; } - -/*------------------------------------------------- - ppc4xx_get_info - PowerPC 4XX-specific - information getter --------------------------------------------------*/ - -void ppc4xx_get_info(powerpc_state *ppc, UINT32 state, cpuinfo *info) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_LINES: info->i = 5; break; - case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_0: info->i = ppc4xx_get_irq_line(ppc, PPC4XX_IRQ_BIT_EXT0); break; - case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_1: info->i = ppc4xx_get_irq_line(ppc, PPC4XX_IRQ_BIT_EXT1); break; - case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_2: info->i = ppc4xx_get_irq_line(ppc, PPC4XX_IRQ_BIT_EXT2); break; - case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_3: info->i = ppc4xx_get_irq_line(ppc, PPC4XX_IRQ_BIT_EXT3); break; - case CPUINFO_INT_INPUT_STATE + PPC_IRQ_LINE_4: info->i = ppc4xx_get_irq_line(ppc, PPC4XX_IRQ_BIT_EXT4); break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 31; break; - case CPUINFO_INT_LOGADDR_WIDTH_PROGRAM: info->i = 32; break; - case CPUINFO_INT_PAGE_SHIFT_PROGRAM: info->i = POWERPC_MIN_PAGE_SHIFT;break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: /* provided per-CPU */ break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(internal_ppc4xx); break; - - /* --- everything else is handled generically --- */ - default: ppccom_get_info(ppc, state, info); break; - } -} diff --git a/src/emu/cpu/powerpc/ppccom.h b/src/emu/cpu/powerpc/ppccom.h index b1b082c21ab..53507716a58 100644 --- a/src/emu/cpu/powerpc/ppccom.h +++ b/src/emu/cpu/powerpc/ppccom.h @@ -12,13 +12,39 @@ #define __PPCCOM_H__ #include "ppc.h" -#include "cpu/vtlb.h" + + +/*************************************************************************** + DEBUGGING +***************************************************************************/ + +#define LOG_UML (0) +#define LOG_NATIVE (0) + +#define DISABLE_FLAG_OPTIMIZATIONS (0) +#define DISABLE_FAST_REGISTERS (0) +#define SINGLE_INSTRUCTION_MODE (0) + +#define PRINTF_EXCEPTIONS (0) +#define PRINTF_MMU (0) + +#define PROBE_ADDRESS ~0 /*************************************************************************** CONSTANTS ***************************************************************************/ +/* size of the execution code cache */ +#define CACHE_SIZE (32 * 1024 * 1024) + +/* compilation boundaries -- how far back/forward does the analysis extend? */ +#define COMPILE_BACKWARDS_BYTES 128 +#define COMPILE_FORWARDS_BYTES 512 +#define COMPILE_MAX_INSTRUCTIONS ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4)) +#define COMPILE_MAX_SEQUENCE 64 + + /* core parameters */ #define POWERPC_MIN_PAGE_SHIFT 12 #define POWERPC_MIN_PAGE_SIZE (1 << POWERPC_MIN_PAGE_SHIFT) @@ -43,39 +69,6 @@ #define PPCCAP_601BAT 0x80 /* TRUE if we're doing 601-style BATs (unified I/D, different bit layout) */ #define PPCCAP_604_MMU 0x100 /* TRUE if we have 604-class MMU features */ -/* PowerPC flavors */ -enum powerpc_flavor -{ - PPC_MODEL_403GA = 0x00200000, - PPC_MODEL_403GB = 0x00200100, - PPC_MODEL_403GC = 0x00200200, - PPC_MODEL_403GCX = 0x00201400, - PPC_MODEL_405GP = 0x40110000, - PPC_MODEL_601 = 0x00010000, - PPC_MODEL_603 = 0x00030000, /* "Wart" */ - PPC_MODEL_604 = 0x00040000, /* "Zephyr" */ - PPC_MODEL_602 = 0x00050200, /* "Galahad" */ - PPC_MODEL_603E = 0x00060103, /* "Stretch", version 1.3 */ - PPC_MODEL_603EV = 0x00070000, /* "Valiant" */ - PPC_MODEL_603R = 0x00071202, /* "Goldeneye", version 2.1 */ - PPC_MODEL_740 = 0x00080301, /* "Arthur", version 3.1 */ - PPC_MODEL_750 = PPC_MODEL_740, - PPC_MODEL_740P = 0x00080202, /* "Conan Doyle", version 1.2 */ - PPC_MODEL_750P = PPC_MODEL_740P, - PPC_MODEL_755 = 0x00083203, /* "Goldfinger", version 2.3 */ - PPC_MODEL_7400 = 0x000c0209, /* "Max", version 2.9 */ - PPC_MODEL_7410 = 0x800c1104, /* "Nitro", version 3.4 */ - PPC_MODEL_7450 = 0x80000201, /* "Vger", version 2.1 */ - PPC_MODEL_7451 = 0x80000203, /* "Vger", version 2.3 */ - PPC_MODEL_7441 = PPC_MODEL_7451, - PPC_MODEL_7455 = 0x80010303, /* "Apollo 6", version 3.3 */ - PPC_MODEL_7445 = PPC_MODEL_7455, - PPC_MODEL_7457 = 0x80020101, /* "Apollo 7", version 1.1 */ - PPC_MODEL_MPC8240 = 0x00810101, /* "Kahlua" */ - PPC_MODEL_MPC8241 = 0x80811014, /* "Kahlua Lt" */ - PPC_MODEL_MPC8245 = 0x80811014, /* "Kahlua II" */ -}; - /* exception types */ enum @@ -485,130 +478,4 @@ enum -/*************************************************************************** - STRUCTURES & TYPEDEFS -***************************************************************************/ - -/* PowerPC 4XX-specific serial port state */ -struct ppc4xx_spu_state -{ - UINT8 regs[9]; - UINT8 txbuf; - UINT8 rxbuf; - emu_timer * timer; - UINT8 rxbuffer[256]; - UINT32 rxin, rxout; - ppc4xx_spu_tx_handler tx_handler; -}; - - -/* forward declaration of implementation-specific state */ -struct ppcimp_state; - - -/* PowerPC state */ -struct powerpc_state -{ - /* core registers */ - UINT32 pc; - int icount; - UINT32 r[32]; - double f[32]; - UINT32 cr[8]; - UINT32 xerso; - UINT32 fpscr; - UINT32 msr; - UINT32 sr[16]; - UINT32 spr[1024]; - UINT32 dcr[256]; - - /* parameters for calls */ - UINT32 param0; - UINT32 param1; - - /* MMU */ - vtlb_state * vtlb; - - /* architectural distinctions */ - powerpc_flavor flavor; - UINT32 cap; - UINT8 cache_line_size; - UINT32 tb_divisor; - - /* PowerPC 4xx-specific state */ - ppc4xx_spu_state spu; - emu_timer * fit_timer; - emu_timer * pit_timer; - emu_timer * wdog_timer; - UINT32 pit_reload; - UINT32 irqstate; - emu_timer * buffered_dma_timer[4]; - int buffered_dma_rate[4]; - - /* PowerPC 603-specific state */ - UINT32 mmu603_cmp; - UINT32 mmu603_hash[2]; - UINT32 mmu603_r[4]; - - /* internal stuff */ - device_irq_acknowledge_delegate irq_callback; - legacy_cpu_device * device; - address_space *program; - direct_read_data *direct; - offs_t codexor; - UINT32 irq_pending; - UINT32 system_clock; - UINT32 cpu_clock; - UINT64 tb_zero_cycles; - UINT64 dec_zero_cycles; - emu_timer * decrementer_int_timer; - - /* for use by specific implementations */ - ppcimp_state * impstate; - - read32_delegate dcr_read_func; - write32_delegate dcr_write_func; - - ppc_dcstore_handler dcstore_handler; - - ppc4xx_dma_read_handler ext_dma_read_handler[4]; - ppc4xx_dma_write_handler ext_dma_write_handler[4]; -}; - - - -/*************************************************************************** - FUNCTION PROTOTYPES -***************************************************************************/ - -void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT32 cap, int tb_divisor, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback); -void ppccom_exit(powerpc_state *ppc); - -void ppccom_reset(powerpc_state *ppc); -offs_t ppccom_dasm(powerpc_state *ppc, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram); - -int ppccom_translate_address(powerpc_state *ppc, address_spacenum space, int intention, offs_t *address); - -void ppccom_set_info(powerpc_state *ppc, UINT32 state, cpuinfo *info); -void ppccom_get_info(powerpc_state *ppc, UINT32 state, cpuinfo *info); - -void ppccom_tlb_fill(powerpc_state *ppc); -void ppccom_tlb_flush(powerpc_state *ppc); - -void ppccom_execute_tlbie(powerpc_state *ppc); -void ppccom_execute_tlbia(powerpc_state *ppc); -void ppccom_execute_tlbl(powerpc_state *ppc); -void ppccom_execute_mftb(powerpc_state *ppc); -void ppccom_execute_mfspr(powerpc_state *ppc); -void ppccom_execute_mtspr(powerpc_state *ppc); -void ppccom_execute_mfdcr(powerpc_state *ppc); -void ppccom_execute_mtdcr(powerpc_state *ppc); - -void ppccom_update_fprf(powerpc_state *ppc); - -void ppccom_dcstore_callback(powerpc_state *ppc); - -void ppc4xx_set_info(powerpc_state *ppc, UINT32 state, cpuinfo *info); -void ppc4xx_get_info(powerpc_state *ppc, UINT32 state, cpuinfo *info); - #endif /* __PPCCOM_H__ */ diff --git a/src/emu/cpu/powerpc/ppcdrc.c b/src/emu/cpu/powerpc/ppcdrc.c index 5cbbcbf27df..fb1fc0ca7f8 100644 --- a/src/emu/cpu/powerpc/ppcdrc.c +++ b/src/emu/cpu/powerpc/ppcdrc.c @@ -16,6 +16,7 @@ #include "emu.h" #include "debugger.h" +#include "ppc.h" #include "ppccom.h" #include "ppcfe.h" #include "cpu/drcfe.h" @@ -29,24 +30,6 @@ extern offs_t ppc_dasm_one(char *buffer, UINT32 pc, UINT32 op); /*************************************************************************** - DEBUGGING -***************************************************************************/ - -#define LOG_UML (0) -#define LOG_NATIVE (0) - -#define DISABLE_FLAG_OPTIMIZATIONS (0) -#define DISABLE_FAST_REGISTERS (0) -#define SINGLE_INSTRUCTION_MODE (0) - -#define PRINTF_EXCEPTIONS (0) -#define PRINTF_MMU (0) - -#define PROBE_ADDRESS ~0 - - - -/*************************************************************************** CONSTANTS ***************************************************************************/ @@ -61,15 +44,6 @@ extern offs_t ppc_dasm_one(char *buffer, UINT32 pc, UINT32 op); #define MODE_PROTECTION 0x02 /* 4XX */ #define MODE_USER 0x04 -/* size of the execution code cache */ -#define CACHE_SIZE (32 * 1024 * 1024) - -/* compilation boundaries -- how far back/forward does the analysis extend? */ -#define COMPILE_BACKWARDS_BYTES 128 -#define COMPILE_FORWARDS_BYTES 512 -#define COMPILE_MAX_INSTRUCTIONS ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4)) -#define COMPILE_MAX_SEQUENCE 64 - /* exit codes */ #define EXECUTE_OUT_OF_CYCLES 0 #define EXECUTE_MISSING_CODE 1 @@ -82,15 +56,15 @@ extern offs_t ppc_dasm_one(char *buffer, UINT32 pc, UINT32 op); MACROS ***************************************************************************/ -#define R32(reg) ppc->impstate->regmap[reg] -#define R32Z(reg) (((reg) == 0) ? parameter(0) : ppc->impstate->regmap[reg]) -#define F64(reg) ppc->impstate->fdregmap[reg] -#define CR32(reg) mem(&ppc->cr[reg]) -#define FPSCR32 mem(&ppc->fpscr) -#define MSR32 mem(&ppc->msr) -#define XERSO32 mem(&ppc->xerso) -#define SR32(reg) mem(&ppc->sr[reg]) -#define SPR32(reg) mem(&ppc->spr[reg]) +#define R32(reg) m_regmap[reg] +#define R32Z(reg) (((reg) == 0) ? parameter(0) : m_regmap[reg]) +#define F64(reg) m_fdregmap[reg] +#define CR32(reg) mem(&m_core->cr[reg]) +#define FPSCR32 mem(&m_core->fpscr) +#define MSR32 mem(&m_core->msr) +#define XERSO32 mem(&m_core->xerso) +#define SR32(reg) mem(&m_core->sr[reg]) +#define SPR32(reg) mem(&m_core->spr[reg]) #define CRMASK(reg) (0xf0000000 >> ((reg) * 4)) @@ -122,336 +96,15 @@ extern offs_t ppc_dasm_one(char *buffer, UINT32 pc, UINT32 op); /*************************************************************************** - STRUCTURES & TYPEDEFS -***************************************************************************/ - -/* fast RAM info */ -struct fast_ram_info -{ - offs_t start; /* start of the RAM block */ - offs_t end; /* end of the RAM block */ - UINT8 readonly; /* TRUE if read-only */ - void * base; /* base in memory where the RAM lives */ -}; - - -/* hotspot info */ -struct hotspot_info -{ - offs_t pc; /* PC to consider */ - UINT32 opcode; /* required opcode at that PC */ - UINT32 cycles; /* number of cycles to eat when hit */ -}; - - -/* internal compiler state */ -struct compiler_state -{ - UINT32 cycles; /* accumulated cycles */ - UINT8 checkints; /* need to check interrupts before next instruction */ - UINT8 checksoftints; /* need to check software interrupts before next instruction */ - code_label labelnum; /* index for local labels */ -}; - - -/* PowerPC implementation state */ -struct ppcimp_state -{ - /* core state */ - drc_cache * cache; /* pointer to the DRC code cache */ - drcuml_state * drcuml; /* DRC UML generator state */ - ppc_frontend * drcfe; /* pointer to the DRC front-end state */ - UINT32 drcoptions; /* configurable DRC options */ - - /* parameters for subroutines */ - UINT32 mode; /* current global mode */ - const char * format; /* format string for printing */ - UINT32 arg0; /* print_debug argument 1 */ - UINT32 arg1; /* print_debug argument 2 */ - UINT32 updateaddr; /* update address storage */ - UINT32 swcount; /* counter for sw instructions */ - UINT32 tempaddr; /* temporary address storage */ - drcuml_ireg tempdata; /* temporary data storage */ - double fp0; /* floating point 0 */ - - /* tables */ - UINT8 fpmode[4]; /* FPU mode table */ - UINT8 sz_cr_table[32]; /* SZ CR table */ - UINT8 cmp_cr_table[32]; /* CMP CR table */ - UINT8 cmpl_cr_table[32]; /* CMPL CR table */ - UINT8 fcmp_cr_table[32]; /* FCMP CR table */ - - /* internal stuff */ - UINT8 cache_dirty; /* true if we need to flush the cache */ - - /* register mappings */ - parameter regmap[32]; /* parameter to register mappings for all 32 integer registers */ - parameter fdregmap[32]; /* parameter to register mappings for all 32 floating point registers */ - - /* subroutines */ - code_handle * entry; /* entry point */ - code_handle * nocode; /* nocode exception handler */ - code_handle * out_of_cycles; /* out of cycles exception handler */ - code_handle * tlb_mismatch; /* tlb mismatch handler */ - code_handle * swap_tgpr; /* swap TGPR handler */ - code_handle * lsw[8][32]; /* lsw entries */ - code_handle * stsw[8][32]; /* stsw entries */ - code_handle * read8[8]; /* read byte */ - code_handle * write8[8]; /* write byte */ - code_handle * read16[8]; /* read half */ - code_handle * read16mask[8]; /* read half */ - code_handle * write16[8]; /* write half */ - code_handle * write16mask[8]; /* write half */ - code_handle * read32[8]; /* read word */ - code_handle * read32align[8]; /* read word aligned */ - code_handle * read32mask[8]; /* read word */ - code_handle * write32[8]; /* write word */ - code_handle * write32align[8]; /* write word aligned */ - code_handle * write32mask[8]; /* write word */ - code_handle * read64[8]; /* read double */ - code_handle * read64mask[8]; /* read double */ - code_handle * write64[8]; /* write double */ - code_handle * write64mask[8]; /* write double */ - code_handle * exception[EXCEPTION_COUNT]; /* array of exception handlers */ - code_handle * exception_norecover[EXCEPTION_COUNT]; /* array of exception handlers */ - - /* fast RAM */ - UINT32 fastram_select; - fast_ram_info fastram[PPC_MAX_FASTRAM]; - - /* hotspots */ - UINT32 hotspot_select; - hotspot_info hotspot[PPC_MAX_HOTSPOTS]; -}; - - - -/*************************************************************************** - FUNCTION PROTOTYPES -***************************************************************************/ - -static void code_flush_cache(powerpc_state *ppc); -static void code_compile_block(powerpc_state *ppc, UINT8 mode, offs_t pc); - -static void cfunc_printf_exception(void *param); -static void cfunc_printf_probe(void *param); - -static void static_generate_entry_point(powerpc_state *ppc); -static void static_generate_nocode_handler(powerpc_state *ppc); -static void static_generate_out_of_cycles(powerpc_state *ppc); -static void static_generate_tlb_mismatch(powerpc_state *ppc); -static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int recover, const char *name); -static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int size, int iswrite, int ismasked, const char *name, code_handle *&handleptr, code_handle *masked); -static void static_generate_swap_tgpr(powerpc_state *ppc); -static void static_generate_lsw_entries(powerpc_state *ppc, int mode); -static void static_generate_stsw_entries(powerpc_state *ppc, int mode); - -static void generate_update_mode(powerpc_state *ppc, drcuml_block *block); -static void generate_update_cycles(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, parameter, int allow_exception); -static void generate_checksum_block(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast); -static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_opcode(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_instruction_13(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); - -static void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op); -static const char *log_desc_flags_to_string(UINT32 flags); -static void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist); -static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent); - - - -/*************************************************************************** - PRIVATE GLOBAL VARIABLES -***************************************************************************/ - -/* lookup table for FP modes */ -static const UINT8 fpmode_source[4] = -{ - ROUND_ROUND, - ROUND_TRUNC, - ROUND_CEIL, - ROUND_FLOOR -}; - -/* flag lookup table for SZ */ -static const UINT8 sz_cr_table_source[32] = -{ - /* ..... */ 0x4, - /* ....C */ 0x4, - /* ...V. */ 0x4, - /* ...VC */ 0x4, - /* ..Z.. */ 0x2, - /* ..Z.C */ 0x2, - /* ..ZV. */ 0x2, - /* ..ZVC */ 0x2, - /* .S... */ 0x8, - /* .S..C */ 0x8, - /* .S.V. */ 0x8, - /* .S.VC */ 0x8, - /* .SZ.. */ 0x2, - /* .SZ.C */ 0x2, - /* .SZV. */ 0x2, - /* .SZVC */ 0x2, - /* U.... */ 0x4, - /* U...C */ 0x4, - /* U..V. */ 0x4, - /* U..VC */ 0x4, - /* U.Z.. */ 0x2, - /* U.Z.C */ 0x2, - /* U.ZV. */ 0x2, - /* U.ZVC */ 0x2, - /* US... */ 0x8, - /* US..C */ 0x8, - /* US.V. */ 0x8, - /* US.VC */ 0x8, - /* USZ.. */ 0x2, - /* USZ.C */ 0x2, - /* USZV. */ 0x2, - /* USZVC */ 0x2 -}; - -/* flag lookup table for CMP */ -static const UINT8 cmp_cr_table_source[32] = -{ - /* ..... */ 0x4, - /* ....C */ 0x4, - /* ...V. */ 0x8, - /* ...VC */ 0x8, - /* ..Z.. */ 0x2, - /* ..Z.C */ 0x2, - /* ..ZV. */ 0x2, - /* ..ZVC */ 0x2, - /* .S... */ 0x8, - /* .S..C */ 0x8, - /* .S.V. */ 0x4, - /* .S.VC */ 0x4, - /* .SZ.. */ 0x2, - /* .SZ.C */ 0x2, - /* .SZV. */ 0x2, - /* .SZVC */ 0x2, - /* U.... */ 0x4, - /* U...C */ 0x4, - /* U..V. */ 0x8, - /* U..VC */ 0x8, - /* U.Z.. */ 0x2, - /* U.Z.C */ 0x2, - /* U.ZV. */ 0x2, - /* U.ZVC */ 0x2, - /* US... */ 0x8, - /* US..C */ 0x8, - /* US.V. */ 0x4, - /* US.VC */ 0x4, - /* USZ.. */ 0x2, - /* USZ.C */ 0x2, - /* USZV. */ 0x2, - /* USZVC */ 0x2 -}; - -/* flag lookup table for CMPL */ -static const UINT8 cmpl_cr_table_source[32] = -{ - /* ..... */ 0x4, - /* ....C */ 0x8, - /* ...V. */ 0x4, - /* ...VC */ 0x8, - /* ..Z.. */ 0x2, - /* ..Z.C */ 0x2, - /* ..ZV. */ 0x2, - /* ..ZVC */ 0x2, - /* .S... */ 0x4, - /* .S..C */ 0x8, - /* .S.V. */ 0x4, - /* .S.VC */ 0x8, - /* .SZ.. */ 0x2, - /* .SZ.C */ 0x2, - /* .SZV. */ 0x2, - /* .SZVC */ 0x2, - /* U.... */ 0x4, - /* U...C */ 0x8, - /* U..V. */ 0x4, - /* U..VC */ 0x8, - /* U.Z.. */ 0x2, - /* U.Z.C */ 0x2, - /* U.ZV. */ 0x2, - /* U.ZVC */ 0x2, - /* US... */ 0x4, - /* US..C */ 0x8, - /* US.V. */ 0x4, - /* US.VC */ 0x8, - /* USZ.. */ 0x2, - /* USZ.C */ 0x2, - /* USZV. */ 0x2, - /* USZVC */ 0x2 -}; - -/* flag lookup table for FCMP */ -static const UINT8 fcmp_cr_table_source[32] = -{ - /* ..... */ 0x4, - /* ....C */ 0x8, - /* ...V. */ 0x4, - /* ...VC */ 0x8, - /* ..Z.. */ 0x2, - /* ..Z.C */ 0xa, - /* ..ZV. */ 0x2, - /* ..ZVC */ 0xa, - /* .S... */ 0x4, - /* .S..C */ 0x8, - /* .S.V. */ 0x4, - /* .S.VC */ 0x8, - /* .SZ.. */ 0x2, - /* .SZ.C */ 0xa, - /* .SZV. */ 0x2, - /* .SZVC */ 0xa, - /* U.... */ 0x5, - /* U...C */ 0x9, - /* U..V. */ 0x5, - /* U..VC */ 0x9, - /* U.Z.. */ 0x3, - /* U.Z.C */ 0xb, - /* U.ZV. */ 0x3, - /* U.ZVC */ 0xb, - /* US... */ 0x5, - /* US..C */ 0x9, - /* US.V. */ 0x5, - /* US.VC */ 0x9, - /* USZ.. */ 0x3, - /* USZ.C */ 0xb, - /* USZV. */ 0x3, - /* USZVC */ 0xb -}; - - - -/*************************************************************************** INLINE FUNCTIONS ***************************************************************************/ -INLINE powerpc_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == PPC403GA || - device->type() == PPC403GCX || - device->type() == PPC405GP || - device->type() == PPC601 || - device->type() == PPC602 || - device->type() == PPC603 || - device->type() == PPC603E || - device->type() == PPC603R || - device->type() == PPC604 || - device->type() == MPC8240); - return *(powerpc_state **)downcast<legacy_cpu_device *>(device)->token(); -} - /*------------------------------------------------- alloc_handle - allocate a handle if not already allocated -------------------------------------------------*/ -INLINE void alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const char *name) +inline void ppc_device::alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const char *name) { if (*handleptr == NULL) *handleptr = drcuml->handle_alloc(name); @@ -463,13 +116,17 @@ INLINE void alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const ch registers -------------------------------------------------*/ -INLINE void load_fast_iregs(powerpc_state *ppc, drcuml_block *block) +inline void ppc_device::load_fast_iregs(drcuml_block *block) { int regnum; - for (regnum = 0; regnum < ARRAY_LENGTH(ppc->impstate->regmap); regnum++) - if (ppc->impstate->regmap[regnum].is_int_register()) - UML_MOV(block, ireg(ppc->impstate->regmap[regnum].ireg() - REG_I0), mem(&ppc->r[regnum])); + for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++) + { + if (m_regmap[regnum].is_int_register()) + { + UML_MOV(block, ireg(m_regmap[regnum].ireg() - REG_I0), mem(&m_core->r[regnum])); + } + } } @@ -478,13 +135,17 @@ INLINE void load_fast_iregs(powerpc_state *ppc, drcuml_block *block) registers -------------------------------------------------*/ -INLINE void save_fast_iregs(powerpc_state *ppc, drcuml_block *block) +void ppc_device::save_fast_iregs(drcuml_block *block) { int regnum; - for (regnum = 0; regnum < ARRAY_LENGTH(ppc->impstate->regmap); regnum++) - if (ppc->impstate->regmap[regnum].is_int_register()) - UML_MOV(block, mem(&ppc->r[regnum]), ireg(ppc->impstate->regmap[regnum].ireg() - REG_I0)); + for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++) + { + if (m_regmap[regnum].is_int_register()) + { + UML_MOV(block, mem(&m_core->r[regnum]), ireg(m_regmap[regnum].ireg() - REG_I0)); + } + } } @@ -493,7 +154,7 @@ INLINE void save_fast_iregs(powerpc_state *ppc, drcuml_block *block) for an rlw* instruction -------------------------------------------------*/ -INLINE UINT32 compute_rlw_mask(UINT8 mb, UINT8 me) +inline UINT32 ppc_device::compute_rlw_mask(UINT8 mb, UINT8 me) { if (mb <= me) return (0xffffffff >> mb) & (0xffffffff << (31 - me)); @@ -507,7 +168,7 @@ INLINE UINT32 compute_rlw_mask(UINT8 mb, UINT8 me) for a mtcrf/mfcrf instruction -------------------------------------------------*/ -INLINE UINT32 compute_crf_mask(UINT8 crm) +inline UINT32 ppc_device::compute_crf_mask(UINT8 crm) { UINT32 mask = 0; if (crm & 0x80) mask |= 0xf0000000; @@ -527,7 +188,7 @@ INLINE UINT32 compute_crf_mask(UINT8 crm) SPR field of an opcode -------------------------------------------------*/ -INLINE UINT32 compute_spr(UINT32 spr) +inline UINT32 ppc_device::compute_spr(UINT32 spr) { return ((spr >> 5) | (spr << 5)) & 0x3ff; } @@ -539,258 +200,44 @@ INLINE UINT32 compute_spr(UINT32 spr) ***************************************************************************/ /*------------------------------------------------- - ppcdrc_init - initialize the processor --------------------------------------------------*/ - -static void ppcdrc_init(powerpc_flavor flavor, UINT32 cap, int tb_divisor, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback) -{ - powerpc_state *ppc; - drcbe_info beinfo; - UINT32 flags = 0; - drc_cache *cache; - int regnum; - - /* allocate enough space for the cache and the core */ - cache = auto_alloc(device->machine(), drc_cache(CACHE_SIZE + sizeof(*ppc))); - - /* allocate the core from the near cache */ - *(powerpc_state **)device->token() = ppc = (powerpc_state *)cache->alloc_near(sizeof(*ppc)); - memset(ppc, 0, sizeof(*ppc)); - - /* initialize the core */ - ppccom_init(ppc, flavor, cap, tb_divisor, device, irqcallback); - - /* allocate the implementation-specific state from the full cache */ - ppc->impstate = (ppcimp_state *)cache->alloc_near(sizeof(*ppc->impstate)); - memset(ppc->impstate, 0, sizeof(*ppc->impstate)); - ppc->impstate->cache = cache; - - /* initialize the UML generator */ - if (LOG_UML) - flags |= DRCUML_OPTION_LOG_UML; - if (LOG_NATIVE) - flags |= DRCUML_OPTION_LOG_NATIVE; - ppc->impstate->drcuml = auto_alloc(device->machine(), drcuml_state(*device, *cache, flags, 8, 32, 2)); - - /* add symbols for our stuff */ - ppc->impstate->drcuml->symbol_add(&ppc->pc, sizeof(ppc->pc), "pc"); - ppc->impstate->drcuml->symbol_add(&ppc->icount, sizeof(ppc->icount), "icount"); - for (regnum = 0; regnum < 32; regnum++) - { - char buf[10]; - sprintf(buf, "r%d", regnum); - ppc->impstate->drcuml->symbol_add(&ppc->r[regnum], sizeof(ppc->r[regnum]), buf); - sprintf(buf, "fpr%d", regnum); - ppc->impstate->drcuml->symbol_add(&ppc->f[regnum], sizeof(ppc->r[regnum]), buf); - } - for (regnum = 0; regnum < 8; regnum++) - { - char buf[10]; - sprintf(buf, "cr%d", regnum); - ppc->impstate->drcuml->symbol_add(&ppc->cr[regnum], sizeof(ppc->cr[regnum]), buf); - } - ppc->impstate->drcuml->symbol_add(&ppc->xerso, sizeof(ppc->xerso), "xerso"); - ppc->impstate->drcuml->symbol_add(&ppc->fpscr, sizeof(ppc->fpscr), "fpscr"); - ppc->impstate->drcuml->symbol_add(&ppc->msr, sizeof(ppc->msr), "msr"); - ppc->impstate->drcuml->symbol_add(&ppc->sr, sizeof(ppc->sr), "sr"); - ppc->impstate->drcuml->symbol_add(&ppc->spr[SPR_XER], sizeof(ppc->spr[SPR_XER]), "xer"); - ppc->impstate->drcuml->symbol_add(&ppc->spr[SPR_LR], sizeof(ppc->spr[SPR_LR]), "lr"); - ppc->impstate->drcuml->symbol_add(&ppc->spr[SPR_CTR], sizeof(ppc->spr[SPR_CTR]), "ctr"); - ppc->impstate->drcuml->symbol_add(&ppc->spr, sizeof(ppc->spr), "spr"); - ppc->impstate->drcuml->symbol_add(&ppc->dcr, sizeof(ppc->dcr), "dcr"); - ppc->impstate->drcuml->symbol_add(&ppc->param0, sizeof(ppc->param0), "param0"); - ppc->impstate->drcuml->symbol_add(&ppc->param1, sizeof(ppc->param1), "param1"); - ppc->impstate->drcuml->symbol_add(&ppc->irq_pending, sizeof(ppc->irq_pending), "irq_pending"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->mode, sizeof(ppc->impstate->mode), "mode"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->arg0, sizeof(ppc->impstate->arg0), "arg0"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->arg1, sizeof(ppc->impstate->arg1), "arg1"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->updateaddr, sizeof(ppc->impstate->updateaddr), "updateaddr"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->swcount, sizeof(ppc->impstate->swcount), "swcount"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->tempaddr, sizeof(ppc->impstate->tempaddr), "tempaddr"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->tempdata, sizeof(ppc->impstate->tempdata), "tempdata"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->fp0, sizeof(ppc->impstate->fp0), "fp0"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->fpmode, sizeof(ppc->impstate->fpmode), "fpmode"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->sz_cr_table, sizeof(ppc->impstate->sz_cr_table), "sz_cr_table"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->cmp_cr_table, sizeof(ppc->impstate->cmp_cr_table), "cmp_cr_table"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->cmpl_cr_table, sizeof(ppc->impstate->cmpl_cr_table), "cmpl_cr_table"); - ppc->impstate->drcuml->symbol_add(&ppc->impstate->fcmp_cr_table, sizeof(ppc->impstate->fcmp_cr_table), "fcmp_cr_table"); - - /* initialize the front-end helper */ - ppc->impstate->drcfe = auto_alloc(device->machine(), ppc_frontend(*ppc, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE)); - - /* initialize the implementation state tables */ - memcpy(ppc->impstate->fpmode, fpmode_source, sizeof(fpmode_source)); - memcpy(ppc->impstate->sz_cr_table, sz_cr_table_source, sizeof(sz_cr_table_source)); - memcpy(ppc->impstate->cmp_cr_table, cmp_cr_table_source, sizeof(cmp_cr_table_source)); - memcpy(ppc->impstate->cmpl_cr_table, cmpl_cr_table_source, sizeof(cmpl_cr_table_source)); - memcpy(ppc->impstate->fcmp_cr_table, fcmp_cr_table_source, sizeof(fcmp_cr_table_source)); - - /* compute the register parameters */ - for (regnum = 0; regnum < 32; regnum++) - { - ppc->impstate->regmap[regnum] = mem(&ppc->r[regnum]); - ppc->impstate->fdregmap[regnum] = mem(&ppc->f[regnum]); - } - - /* if we have registers to spare, assign r0, r1, r2 to leftovers */ - if (!DISABLE_FAST_REGISTERS) - { - ppc->impstate->drcuml->get_backend_info(beinfo); - if (beinfo.direct_iregs > 5) - ppc->impstate->regmap[0] = I5; - if (beinfo.direct_iregs > 6) - ppc->impstate->regmap[1] = I6; - if (beinfo.direct_iregs > 7) - ppc->impstate->regmap[2] = I7; - } - - /* mark the cache dirty so it is updated on next execute */ - ppc->impstate->cache_dirty = TRUE; -} - - -/*------------------------------------------------- - ppcdrc_reset - reset the processor --------------------------------------------------*/ - -static CPU_RESET( ppcdrc ) -{ - powerpc_state *ppc = get_safe_token(device); - - /* reset the common code and mark the cache dirty */ - ppccom_reset(ppc); - ppc->impstate->mode = 0; - ppc->impstate->cache_dirty = TRUE; -} - - -/*------------------------------------------------- ppcdrc_execute - execute the CPU for the specified number of cycles -------------------------------------------------*/ -static CPU_EXECUTE( ppcdrc ) +void ppc_device::execute_run() { - powerpc_state *ppc = get_safe_token(device); - drcuml_state *drcuml = ppc->impstate->drcuml; int execute_result; /* reset the cache if dirty */ - if (ppc->impstate->cache_dirty) - code_flush_cache(ppc); - ppc->impstate->cache_dirty = FALSE; + if (m_cache_dirty) + code_flush_cache(); + m_cache_dirty = FALSE; /* execute */ do { /* run as much as we can */ - execute_result = drcuml->execute(*ppc->impstate->entry); + execute_result = m_drcuml->execute(*m_entry); /* if we need to recompile, do it */ if (execute_result == EXECUTE_MISSING_CODE) - code_compile_block(ppc, ppc->impstate->mode, ppc->pc); + code_compile_block(m_core->mode, m_core->pc); else if (execute_result == EXECUTE_UNMAPPED_CODE) - fatalerror("Attempted to execute unmapped code at PC=%08X\n", ppc->pc); + fatalerror("Attempted to execute unmapped code at PC=%08X\n", m_core->pc); else if (execute_result == EXECUTE_RESET_CACHE) - code_flush_cache(ppc); + code_flush_cache(); } while (execute_result != EXECUTE_OUT_OF_CYCLES); } /*------------------------------------------------- - ppcdrc_exit - cleanup from execution --------------------------------------------------*/ - -static CPU_EXIT( ppcdrc ) -{ - powerpc_state *ppc = get_safe_token(device); - ppccom_exit(ppc); - - /* clean up the DRC */ - auto_free(device->machine(), ppc->impstate->drcfe); - auto_free(device->machine(), ppc->impstate->drcuml); - auto_free(device->machine(), ppc->impstate->cache); -} - - -/*------------------------------------------------- - ppcdrc_translate - perform virtual-to-physical - address translation --------------------------------------------------*/ - -static CPU_TRANSLATE( ppcdrc ) -{ - powerpc_state *ppc = get_safe_token(device); - return ppccom_translate_address(ppc, space, intention, address); -} - - -/*------------------------------------------------- - ppcdrc_dasm - disassemble an instruction --------------------------------------------------*/ - -static CPU_DISASSEMBLE( ppcdrc ) -{ - powerpc_state *ppc = get_safe_token(device); - return ppccom_dasm(ppc, buffer, pc, oprom, opram); -} - - -/*------------------------------------------------- - ppcdrc_set_info - set information about a given - CPU instance --------------------------------------------------*/ - -static CPU_SET_INFO( ppcdrc ) -{ - powerpc_state *ppc = get_safe_token(device); - - /* --- everything is handled generically --- */ - ppccom_set_info(ppc, state, info); -} - - -/*------------------------------------------------- - ppcdrc_get_info - return information about a given - CPU instance --------------------------------------------------*/ - -static CPU_GET_INFO( ppcdrc ) -{ - powerpc_state *ppc = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(powerpc_state *); break; - case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(ppcdrc); break; - case CPUINFO_FCT_INIT: /* provided per-CPU */ break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(ppcdrc); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(ppcdrc); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(ppcdrc); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(ppcdrc);break; - case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(ppcdrc); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - - /* --- everything else is handled generically --- */ - default: ppccom_get_info(ppc, state, info); break; - } -} - - -/*------------------------------------------------- ppcdrc_set_options - configure DRC options -------------------------------------------------*/ -void ppcdrc_set_options(device_t *device, UINT32 options) +void ppc_device::ppcdrc_set_options(UINT32 options) { - powerpc_state *ppc = get_safe_token(device); - ppc->impstate->drcoptions = options; + m_drcoptions = options; } @@ -799,16 +246,15 @@ void ppcdrc_set_options(device_t *device, UINT32 options) region -------------------------------------------------*/ -void ppcdrc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base) +void ppc_device::ppcdrc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base) { - powerpc_state *ppc = get_safe_token(device); - if (ppc->impstate->fastram_select < ARRAY_LENGTH(ppc->impstate->fastram)) + if (m_fastram_select < ARRAY_LENGTH(m_fastram)) { - ppc->impstate->fastram[ppc->impstate->fastram_select].start = start; - ppc->impstate->fastram[ppc->impstate->fastram_select].end = end; - ppc->impstate->fastram[ppc->impstate->fastram_select].readonly = readonly; - ppc->impstate->fastram[ppc->impstate->fastram_select].base = base; - ppc->impstate->fastram_select++; + m_fastram[m_fastram_select].start = start; + m_fastram[m_fastram_select].end = end; + m_fastram[m_fastram_select].readonly = readonly; + m_fastram[m_fastram_select].base = base; + m_fastram_select++; } } @@ -817,15 +263,14 @@ void ppcdrc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readon ppcdrc_add_hotspot - add a new hotspot -------------------------------------------------*/ -void ppcdrc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles) +void ppc_device::ppcdrc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles) { - powerpc_state *ppc = get_safe_token(device); - if (ppc->impstate->hotspot_select < ARRAY_LENGTH(ppc->impstate->hotspot)) + if (m_hotspot_select < ARRAY_LENGTH(m_hotspot)) { - ppc->impstate->hotspot[ppc->impstate->hotspot_select].pc = pc; - ppc->impstate->hotspot[ppc->impstate->hotspot_select].opcode = opcode; - ppc->impstate->hotspot[ppc->impstate->hotspot_select].cycles = cycles; - ppc->impstate->hotspot_select++; + m_hotspot[m_hotspot_select].pc = pc; + m_hotspot[m_hotspot_select].opcode = opcode; + m_hotspot[m_hotspot_select].cycles = cycles; + m_hotspot_select++; } } @@ -840,66 +285,63 @@ void ppcdrc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycle regenerate static code -------------------------------------------------*/ -static void code_flush_cache(powerpc_state *ppc) +void ppc_device::code_flush_cache() { - drcuml_state *drcuml = ppc->impstate->drcuml; - int mode; - /* empty the transient cache contents */ - drcuml->reset(); + m_drcuml->reset(); try { /* generate the entry point and out-of-cycles handlers */ - static_generate_entry_point(ppc); - static_generate_nocode_handler(ppc); - static_generate_out_of_cycles(ppc); - static_generate_tlb_mismatch(ppc); - if (ppc->cap & PPCCAP_603_MMU) - static_generate_swap_tgpr(ppc); + static_generate_entry_point(); + static_generate_nocode_handler(); + static_generate_out_of_cycles(); + static_generate_tlb_mismatch(); + if (m_cap & PPCCAP_603_MMU) + static_generate_swap_tgpr(); /* append exception handlers for various types */ - static_generate_exception(ppc, EXCEPTION_RESET, TRUE, "exception_reset"); - static_generate_exception(ppc, EXCEPTION_MACHCHECK, TRUE, "exception_machine_check"); - static_generate_exception(ppc, EXCEPTION_DSI, TRUE, "exception_dsi"); - static_generate_exception(ppc, EXCEPTION_ISI, TRUE, "exception_isi"); - static_generate_exception(ppc, EXCEPTION_EI, TRUE, "exception_ei"); - static_generate_exception(ppc, EXCEPTION_EI, FALSE, "exception_ei_norecover"); - static_generate_exception(ppc, EXCEPTION_ALIGN, TRUE, "exception_align"); - static_generate_exception(ppc, EXCEPTION_PROGRAM, TRUE, "exception_program"); - static_generate_exception(ppc, EXCEPTION_NOFPU, TRUE, "exception_fpu_unavailable"); - static_generate_exception(ppc, EXCEPTION_DECREMENT, TRUE, "exception_decrementer"); - static_generate_exception(ppc, EXCEPTION_SYSCALL, TRUE, "exception_syscall"); - static_generate_exception(ppc, EXCEPTION_TRACE, TRUE, "exception_trace"); - static_generate_exception(ppc, EXCEPTION_FPASSIST, TRUE, "exception_floating_point_assist"); - if (ppc->cap & PPCCAP_603_MMU) + static_generate_exception(EXCEPTION_RESET, TRUE, "exception_reset"); + static_generate_exception(EXCEPTION_MACHCHECK, TRUE, "exception_machine_check"); + static_generate_exception(EXCEPTION_DSI, TRUE, "exception_dsi"); + static_generate_exception(EXCEPTION_ISI, TRUE, "exception_isi"); + static_generate_exception(EXCEPTION_EI, TRUE, "exception_ei"); + static_generate_exception(EXCEPTION_EI, FALSE, "exception_ei_norecover"); + static_generate_exception(EXCEPTION_ALIGN, TRUE, "exception_align"); + static_generate_exception(EXCEPTION_PROGRAM, TRUE, "exception_program"); + static_generate_exception(EXCEPTION_NOFPU, TRUE, "exception_fpu_unavailable"); + static_generate_exception(EXCEPTION_DECREMENT, TRUE, "exception_decrementer"); + static_generate_exception(EXCEPTION_SYSCALL, TRUE, "exception_syscall"); + static_generate_exception(EXCEPTION_TRACE, TRUE, "exception_trace"); + static_generate_exception(EXCEPTION_FPASSIST, TRUE, "exception_floating_point_assist"); + if (m_cap & PPCCAP_603_MMU) { - static_generate_exception(ppc, EXCEPTION_ITLBMISS, TRUE, "exception_itlb_miss"); - static_generate_exception(ppc, EXCEPTION_DTLBMISSL, TRUE, "exception_dtlb_miss_load"); - static_generate_exception(ppc, EXCEPTION_DTLBMISSS, TRUE, "exception_dtlb_miss_store"); + static_generate_exception(EXCEPTION_ITLBMISS, TRUE, "exception_itlb_miss"); + static_generate_exception(EXCEPTION_DTLBMISSL, TRUE, "exception_dtlb_miss_load"); + static_generate_exception(EXCEPTION_DTLBMISSS, TRUE, "exception_dtlb_miss_store"); } /* add subroutines for memory accesses */ - for (mode = 0; mode < 8; mode++) + for (int mode = 0; mode < 8; mode++) { - static_generate_memory_accessor(ppc, mode, 1, FALSE, FALSE, "read8", ppc->impstate->read8[mode], NULL); - static_generate_memory_accessor(ppc, mode, 1, TRUE, FALSE, "write8", ppc->impstate->write8[mode], NULL); - static_generate_memory_accessor(ppc, mode, 2, FALSE, TRUE, "read16mask", ppc->impstate->read16mask[mode], NULL); - static_generate_memory_accessor(ppc, mode, 2, FALSE, FALSE, "read16", ppc->impstate->read16[mode], ppc->impstate->read16mask[mode]); - static_generate_memory_accessor(ppc, mode, 2, TRUE, TRUE, "write16mask", ppc->impstate->write16mask[mode], NULL); - static_generate_memory_accessor(ppc, mode, 2, TRUE, FALSE, "write16", ppc->impstate->write16[mode], ppc->impstate->write16mask[mode]); - static_generate_memory_accessor(ppc, mode, 4, FALSE, TRUE, "read32mask", ppc->impstate->read32mask[mode], NULL); - static_generate_memory_accessor(ppc, mode, 4, FALSE, FALSE, "read32align", ppc->impstate->read32align[mode], NULL); - static_generate_memory_accessor(ppc, mode, 4, FALSE, FALSE, "read32", ppc->impstate->read32[mode], ppc->impstate->read32mask[mode]); - static_generate_memory_accessor(ppc, mode, 4, TRUE, TRUE, "write32mask", ppc->impstate->write32mask[mode], NULL); - static_generate_memory_accessor(ppc, mode, 4, TRUE, FALSE, "write32align",ppc->impstate->write32align[mode],NULL); - static_generate_memory_accessor(ppc, mode, 4, TRUE, FALSE, "write32", ppc->impstate->write32[mode], ppc->impstate->write32mask[mode]); - static_generate_memory_accessor(ppc, mode, 8, FALSE, TRUE, "read64mask", ppc->impstate->read64mask[mode], NULL); - static_generate_memory_accessor(ppc, mode, 8, FALSE, FALSE, "read64", ppc->impstate->read64[mode], ppc->impstate->read64mask[mode]); - static_generate_memory_accessor(ppc, mode, 8, TRUE, TRUE, "write64mask", ppc->impstate->write64mask[mode], NULL); - static_generate_memory_accessor(ppc, mode, 8, TRUE, FALSE, "write64", ppc->impstate->write64[mode], ppc->impstate->write64mask[mode]); - static_generate_lsw_entries(ppc, mode); - static_generate_stsw_entries(ppc, mode); + static_generate_memory_accessor(mode, 1, FALSE, FALSE, "read8", m_read8[mode], NULL); + static_generate_memory_accessor(mode, 1, TRUE, FALSE, "write8", m_write8[mode], NULL); + static_generate_memory_accessor(mode, 2, FALSE, TRUE, "read16mask", m_read16mask[mode], NULL); + static_generate_memory_accessor(mode, 2, FALSE, FALSE, "read16", m_read16[mode], m_read16mask[mode]); + static_generate_memory_accessor(mode, 2, TRUE, TRUE, "write16mask", m_write16mask[mode], NULL); + static_generate_memory_accessor(mode, 2, TRUE, FALSE, "write16", m_write16[mode], m_write16mask[mode]); + static_generate_memory_accessor(mode, 4, FALSE, TRUE, "read32mask", m_read32mask[mode], NULL); + static_generate_memory_accessor(mode, 4, FALSE, FALSE, "read32align", m_read32align[mode], NULL); + static_generate_memory_accessor(mode, 4, FALSE, FALSE, "read32", m_read32[mode], m_read32mask[mode]); + static_generate_memory_accessor(mode, 4, TRUE, TRUE, "write32mask", m_write32mask[mode], NULL); + static_generate_memory_accessor(mode, 4, TRUE, FALSE, "write32align",m_write32align[mode],NULL); + static_generate_memory_accessor(mode, 4, TRUE, FALSE, "write32", m_write32[mode], m_write32mask[mode]); + static_generate_memory_accessor(mode, 8, FALSE, TRUE, "read64mask", m_read64mask[mode], NULL); + static_generate_memory_accessor(mode, 8, FALSE, FALSE, "read64", m_read64[mode], m_read64mask[mode]); + static_generate_memory_accessor(mode, 8, TRUE, TRUE, "write64mask", m_write64mask[mode], NULL); + static_generate_memory_accessor(mode, 8, TRUE, FALSE, "write64", m_write64[mode], m_write64mask[mode]); + static_generate_lsw_entries(mode); + static_generate_stsw_entries(mode); } } catch (drcuml_block::abort_compilation &) @@ -914,9 +356,8 @@ static void code_flush_cache(powerpc_state *ppc) given mode at the specified pc -------------------------------------------------*/ -static void code_compile_block(powerpc_state *ppc, UINT8 mode, offs_t pc) +void ppc_device::code_compile_block(UINT8 mode, offs_t pc) { - drcuml_state *drcuml = ppc->impstate->drcuml; compiler_state compiler = { 0 }; const opcode_desc *seqhead, *seqlast; const opcode_desc *desclist; @@ -926,9 +367,9 @@ static void code_compile_block(powerpc_state *ppc, UINT8 mode, offs_t pc) g_profiler.start(PROFILER_DRC_COMPILE); /* get a description of this sequence */ - desclist = ppc->impstate->drcfe->describe_code(pc); + desclist = m_drcfe->describe_code(pc); if (LOG_UML || LOG_NATIVE) - log_opcode_desc(drcuml, desclist, 0); + log_opcode_desc(m_drcuml, desclist, 0); bool succeeded = false; while (!succeeded) @@ -936,7 +377,7 @@ static void code_compile_block(powerpc_state *ppc, UINT8 mode, offs_t pc) try { /* start the block */ - block = drcuml->begin_block(4096); + block = m_drcuml->begin_block(4096); /* loop until we get through all instruction sequences */ for (seqhead = desclist; seqhead != NULL; seqhead = seqlast->next()) @@ -955,7 +396,7 @@ static void code_compile_block(powerpc_state *ppc, UINT8 mode, offs_t pc) assert(seqlast != NULL); /* if we don't have a hash for this mode/pc, or if we are overriding all, add one */ - if (override || !drcuml->hash_exists(mode, seqhead->pc)) + if (override || !m_drcuml->hash_exists(mode, seqhead->pc)) UML_HASH(block, mode, seqhead->pc); // hash mode,pc /* if we already have a hash, and this is the first sequence, assume that we */ @@ -970,14 +411,14 @@ static void code_compile_block(powerpc_state *ppc, UINT8 mode, offs_t pc) else { UML_LABEL(block, seqhead->pc | 0x80000000); // label seqhead->pc | 0x80000000 - UML_HASHJMP(block, ppc->impstate->mode, seqhead->pc, *ppc->impstate->nocode); + UML_HASHJMP(block, m_core->mode, seqhead->pc, *m_nocode); // hashjmp <mode>,seqhead->pc,nocode continue; } /* validate this code block if we're not pointing into ROM */ - if (ppc->program->get_write_ptr(seqhead->physpc) != NULL) - generate_checksum_block(ppc, block, &compiler, seqhead, seqlast); // <checksum> + if (m_program->get_write_ptr(seqhead->physpc) != NULL) + generate_checksum_block(block, &compiler, seqhead, seqlast); // <checksum> /* label this instruction, if it may be jumped to locally */ if (seqhead->flags & OPFLAG_IS_BRANCH_TARGET) @@ -985,7 +426,7 @@ static void code_compile_block(powerpc_state *ppc, UINT8 mode, offs_t pc) /* iterate over instructions in the sequence and compile them */ for (curdesc = seqhead; curdesc != seqlast->next(); curdesc = curdesc->next()) - generate_sequence_instruction(ppc, block, &compiler, curdesc); // <instruction> + generate_sequence_instruction(block, &compiler, curdesc); // <instruction> /* if we need to return to the start, do it */ if (seqlast->flags & OPFLAG_RETURN_TO_START) @@ -996,13 +437,13 @@ static void code_compile_block(powerpc_state *ppc, UINT8 mode, offs_t pc) nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4; /* count off cycles and go there */ - generate_update_cycles(ppc, block, &compiler, nextpc, TRUE); // <subtract cycles> + generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles> /* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */ if (seqlast->flags & OPFLAG_CAN_CHANGE_MODES) - UML_HASHJMP(block, mem(&ppc->impstate->mode), nextpc, *ppc->impstate->nocode);// hashjmp <mode>,nextpc,nocode + UML_HASHJMP(block, mem(&m_core->mode), nextpc, *m_nocode);// hashjmp <mode>,nextpc,nocode else if (seqlast->next() == NULL || seqlast->next()->pc != nextpc) - UML_HASHJMP(block, ppc->impstate->mode, nextpc, *ppc->impstate->nocode);// hashjmp <mode>,nextpc,nocode + UML_HASHJMP(block, m_core->mode, nextpc, *m_nocode);// hashjmp <mode>,nextpc,nocode } /* end the sequence */ @@ -1013,7 +454,7 @@ static void code_compile_block(powerpc_state *ppc, UINT8 mode, offs_t pc) catch (drcuml_block::abort_compilation &) { // flush the cache and try again - code_flush_cache(ppc); + code_flush_cache(); } } } @@ -1031,9 +472,14 @@ static void code_compile_block(powerpc_state *ppc, UINT8 mode, offs_t pc) static void cfunc_printf_exception(void *param) { - powerpc_state *ppc = (powerpc_state *)param; - printf("Exception: type=%2d EPC=%08X MSR=%08X\n", ppc->param0, ppc->spr[SPROEA_SRR0], ppc->spr[SPROEA_SRR1]); - cfunc_printf_probe(ppc); + ppc_device *ppc = (ppc_device *)param; + ppc->ppc_cfunc_printf_exception(); +} + +void ppc_device::ppc_cfunc_printf_exception() +{ + printf("Exception: type=%2d EPC=%08X MSR=%08X\n", m_core->param0, m_core->spr[SPROEA_SRR0], m_core->spr[SPROEA_SRR1]); + ppc_cfunc_printf_probe(); } @@ -1044,8 +490,13 @@ static void cfunc_printf_exception(void *param) static void cfunc_printf_debug(void *param) { - powerpc_state *ppc = (powerpc_state *)param; - printf(ppc->impstate->format, ppc->impstate->arg0, ppc->impstate->arg1); + ppc_device *ppc = (ppc_device *)param; + ppc->ppc_cfunc_printf_debug(); +} + +void ppc_device::ppc_cfunc_printf_debug() +{ + printf(m_core->format, m_core->arg0, m_arg1); } @@ -1056,26 +507,29 @@ static void cfunc_printf_debug(void *param) static void cfunc_printf_probe(void *param) { - powerpc_state *ppc = (powerpc_state *)param; - UINT32 pc = (UINT32)(FPTR)param; + ppc_device *ppc = (ppc_device *)param; + ppc->ppc_cfunc_printf_probe(); +} - printf(" PC=%08X\n", pc); +void ppc_device::ppc_cfunc_printf_probe() +{ + printf(" PC=%08X\n", m_core->pc); printf(" r0=%08X r1=%08X r2=%08X r3=%08X\n", - ppc->r[0], ppc->r[1], ppc->r[2], ppc->r[3]); + m_core->r[0], m_core->r[1], m_core->r[2], m_core->r[3]); printf(" r4=%08X r5=%08X r6=%08X r7=%08X\n", - ppc->r[4], ppc->r[5], ppc->r[6], ppc->r[7]); + m_core->r[4], m_core->r[5], m_core->r[6], m_core->r[7]); printf(" r8=%08X r9=%08X r10=%08X r11=%08X\n", - ppc->r[8], ppc->r[9], ppc->r[10], ppc->r[11]); + m_core->r[8], m_core->r[9], m_core->r[10], m_core->r[11]); printf("r12=%08X r13=%08X r14=%08X r15=%08X\n", - ppc->r[12], ppc->r[13], ppc->r[14], ppc->r[15]); + m_core->r[12], m_core->r[13], m_core->r[14], m_core->r[15]); printf("r16=%08X r17=%08X r18=%08X r19=%08X\n", - ppc->r[16], ppc->r[17], ppc->r[18], ppc->r[19]); + m_core->r[16], m_core->r[17], m_core->r[18], m_core->r[19]); printf("r20=%08X r21=%08X r22=%08X r23=%08X\n", - ppc->r[20], ppc->r[21], ppc->r[22], ppc->r[23]); + m_core->r[20], m_core->r[21], m_core->r[22], m_core->r[23]); printf("r24=%08X r25=%08X r26=%08X r27=%08X\n", - ppc->r[24], ppc->r[25], ppc->r[26], ppc->r[27]); + m_core->r[24], m_core->r[25], m_core->r[26], m_core->r[27]); printf("r28=%08X r29=%08X r30=%08X r31=%08X\n", - ppc->r[28], ppc->r[29], ppc->r[30], ppc->r[31]); + m_core->r[28], m_core->r[29], m_core->r[30], m_core->r[31]); } @@ -1086,11 +540,87 @@ static void cfunc_printf_probe(void *param) static void cfunc_unimplemented(void *param) { - powerpc_state *ppc = (powerpc_state *)param; - UINT32 opcode = ppc->impstate->arg0; - fatalerror("PC=%08X: Unimplemented op %08X\n", ppc->pc, opcode); + ppc_device *ppc = (ppc_device *)param; + ppc->ppc_cfunc_unimplemented(); +} + +void ppc_device::ppc_cfunc_unimplemented() +{ + UINT32 opcode = m_core->arg0; + fatalerror("PC=%08X: Unimplemented op %08X\n", m_core->pc, opcode); +} + +static void cfunc_ppccom_tlb_fill(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_tlb_fill(); +} + +static void cfunc_ppccom_update_fprf(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_update_fprf(); +} + +static void cfunc_ppccom_dcstore_callback(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_dcstore_callback(); +} + +static void cfunc_ppccom_execute_tlbie(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_execute_tlbie(); +} + +static void cfunc_ppccom_execute_tlbia(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_execute_tlbia(); +} + +static void cfunc_ppccom_execute_tlbl(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_execute_tlbl(); +} + +static void cfunc_ppccom_execute_mfspr(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_execute_mfspr(); +} + +static void cfunc_ppccom_execute_mftb(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_execute_mftb(); } +static void cfunc_ppccom_execute_mtspr(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_execute_mtspr(); +} + +static void cfunc_ppccom_tlb_flush(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_tlb_flush(); +} + +static void cfunc_ppccom_execute_mfdcr(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_execute_mfdcr(); +} + +static void cfunc_ppccom_execute_mtdcr(void *param) +{ + ppc_device *ppc = (ppc_device *)param; + ppc->ppccom_execute_mtdcr(); +} /*************************************************************************** @@ -1102,42 +632,41 @@ static void cfunc_unimplemented(void *param) static entry point -------------------------------------------------*/ -static void static_generate_entry_point(powerpc_state *ppc) +void ppc_device::static_generate_entry_point() { - drcuml_state *drcuml = ppc->impstate->drcuml; code_label skip = 1; drcuml_block *block; /* begin generating */ - block = drcuml->begin_block(20); + block = m_drcuml->begin_block(20); /* forward references */ - alloc_handle(drcuml, &ppc->impstate->nocode, "nocode"); - alloc_handle(drcuml, &ppc->impstate->exception_norecover[EXCEPTION_EI], "exception_ei_norecover"); + alloc_handle(m_drcuml, &m_nocode, "nocode"); + alloc_handle(m_drcuml, &m_exception_norecover[EXCEPTION_EI], "exception_ei_norecover"); - alloc_handle(drcuml, &ppc->impstate->entry, "entry"); - UML_HANDLE(block, *ppc->impstate->entry); // handle entry + alloc_handle(m_drcuml, &m_entry, "entry"); + UML_HANDLE(block, *m_entry); // handle entry /* reset the FPU mode */ UML_AND(block, I0, FPSCR32, 3); // and i0,fpscr,3 - UML_LOAD(block, I0, &ppc->impstate->fpmode[0], I0, SIZE_BYTE, SCALE_x1); // load i0,fpmode,i0,byte + UML_LOAD(block, I0, &m_fpmode[0], I0, SIZE_BYTE, SCALE_x1); // load i0,fpmode,i0,byte UML_SETFMOD(block, I0); // setfmod i0 /* load fast integer registers */ - load_fast_iregs(ppc, block); // <load fastregs> + load_fast_iregs(block); // <load fastregs> /* check for interrupts */ - UML_TEST(block, mem(&ppc->irq_pending), ~0); // test [irq_pending],0 + UML_TEST(block, mem(&m_core->irq_pending), ~0); // test [irq_pending],0 UML_JMPc(block, COND_Z, skip); // jmp skip,Z UML_TEST(block, MSR32, MSR_EE); // test msr,MSR_EE UML_JMPc(block, COND_Z, skip); // jmp skip,Z - UML_MOV(block, I0, mem(&ppc->pc)); // mov i0,pc + UML_MOV(block, I0, mem(&m_core->pc)); // mov i0,pc UML_MOV(block, I1, 0); // mov i1,0 - UML_CALLH(block, *ppc->impstate->exception_norecover[EXCEPTION_EI]); // callh exception_norecover + UML_CALLH(block, *m_exception_norecover[EXCEPTION_EI]); // callh exception_norecover UML_LABEL(block, skip); // skip: /* generate a hash jump via the current mode and PC */ - UML_HASHJMP(block, mem(&ppc->impstate->mode), mem(&ppc->pc), *ppc->impstate->nocode); // hashjmp <mode>,<pc>,nocode + UML_HASHJMP(block, mem(&m_core->mode), mem(&m_core->pc), *m_nocode); // hashjmp <mode>,<pc>,nocode block->end(); } @@ -1148,20 +677,19 @@ static void static_generate_entry_point(powerpc_state *ppc) exception handler for "out of code" -------------------------------------------------*/ -static void static_generate_nocode_handler(powerpc_state *ppc) +void ppc_device::static_generate_nocode_handler() { - drcuml_state *drcuml = ppc->impstate->drcuml; drcuml_block *block; /* begin generating */ - block = drcuml->begin_block(10); + block = m_drcuml->begin_block(10); /* generate a hash jump via the current mode and PC */ - alloc_handle(drcuml, &ppc->impstate->nocode, "nocode"); - UML_HANDLE(block, *ppc->impstate->nocode); // handle nocode + alloc_handle(m_drcuml, &m_nocode, "nocode"); + UML_HANDLE(block, *m_nocode); // handle nocode UML_GETEXP(block, I0); // getexp i0 - UML_MOV(block, mem(&ppc->pc), I0); // mov [pc],i0 - save_fast_iregs(ppc, block); // <save fastregs> + UML_MOV(block, mem(&m_core->pc), I0); // mov [pc],i0 + save_fast_iregs(block); // <save fastregs> UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE block->end(); @@ -1173,20 +701,19 @@ static void static_generate_nocode_handler(powerpc_state *ppc) out of cycles exception handler -------------------------------------------------*/ -static void static_generate_out_of_cycles(powerpc_state *ppc) +void ppc_device::static_generate_out_of_cycles() { - drcuml_state *drcuml = ppc->impstate->drcuml; drcuml_block *block; /* begin generating */ - block = drcuml->begin_block(10); + block = m_drcuml->begin_block(10); /* generate a hash jump via the current mode and PC */ - alloc_handle(drcuml, &ppc->impstate->out_of_cycles, "out_of_cycles"); - UML_HANDLE(block, *ppc->impstate->out_of_cycles); // handle out_of_cycles + alloc_handle(m_drcuml, &m_out_of_cycles, "out_of_cycles"); + UML_HANDLE(block, *m_out_of_cycles); // handle out_of_cycles UML_GETEXP(block, I0); // getexp i0 - UML_MOV(block, mem(&ppc->pc), I0); // mov <pc>,i0 - save_fast_iregs(ppc, block); // <save fastregs> + UML_MOV(block, mem(&m_core->pc), I0); // mov <pc>,i0 + save_fast_iregs(block); // <save fastregs> UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES block->end(); @@ -1198,52 +725,51 @@ static void static_generate_out_of_cycles(powerpc_state *ppc) TLB mismatch handler -------------------------------------------------*/ -static void static_generate_tlb_mismatch(powerpc_state *ppc) +void ppc_device::static_generate_tlb_mismatch() { - drcuml_state *drcuml = ppc->impstate->drcuml; drcuml_block *block; int isi, exit, label = 1; /* forward references */ - alloc_handle(drcuml, &ppc->impstate->exception[EXCEPTION_ISI], "exception_isi"); - if (ppc->cap & PPCCAP_603_MMU) - alloc_handle(drcuml, &ppc->impstate->exception[EXCEPTION_ITLBMISS], "exception_itlb_miss"); + alloc_handle(m_drcuml, &m_exception[EXCEPTION_ISI], "exception_isi"); + if (m_cap & PPCCAP_603_MMU) + alloc_handle(m_drcuml, &m_exception[EXCEPTION_ITLBMISS], "exception_itlb_miss"); /* begin generating */ - block = drcuml->begin_block(20); + block = m_drcuml->begin_block(20); /* generate a hash jump via the current mode and PC */ - alloc_handle(drcuml, &ppc->impstate->tlb_mismatch, "tlb_mismatch"); - UML_HANDLE(block, *ppc->impstate->tlb_mismatch); // handle tlb_mismatch + alloc_handle(m_drcuml, &m_tlb_mismatch, "tlb_mismatch"); + UML_HANDLE(block, *m_tlb_mismatch); // handle tlb_mismatch UML_RECOVER(block, I0, MAPVAR_PC); // recover i0,PC UML_SHR(block, I1, I0, 12); // shr i1,i0,12 - UML_LOAD(block, I2, (void *)vtlb_table(ppc->vtlb), I1, SIZE_DWORD, SCALE_x4); // load i2,[vtlb],i1,dword - UML_MOV(block, mem(&ppc->param0), I0); // mov [param0],i0 - UML_MOV(block, mem(&ppc->param1), TRANSLATE_FETCH); // mov [param1],TRANSLATE_FETCH - UML_CALLC(block, (c_function)ppccom_tlb_fill, ppc); // callc tlbfill,ppc - UML_LOAD(block, I1, (void *)vtlb_table(ppc->vtlb), I1, SIZE_DWORD, SCALE_x4); // load i1,[vtlb],i1,dword + UML_LOAD(block, I2, (void *)vtlb_table(m_vtlb), I1, SIZE_DWORD, SCALE_x4); // load i2,[vtlb],i1,dword + UML_MOV(block, mem(&m_core->param0), I0); // mov [param0],i0 + UML_MOV(block, mem(&m_core->param1), TRANSLATE_FETCH); // mov [param1],TRANSLATE_FETCH + UML_CALLC(block, (c_function)cfunc_ppccom_tlb_fill, this); // callc tlbfill,ppc + UML_LOAD(block, I1, (void *)vtlb_table(m_vtlb), I1, SIZE_DWORD, SCALE_x4); // load i1,[vtlb],i1,dword UML_TEST(block, I1, VTLB_FETCH_ALLOWED); // test i1,VTLB_FETCH_ALLOWED UML_JMPc(block, COND_Z, isi = label++); // jmp isi,z UML_CMP(block, I2, 0); // cmp i2,0 UML_JMPc(block, COND_NZ, exit = label++); // jmp exit,nz - UML_HASHJMP(block, mem(&ppc->impstate->mode), I0, *ppc->impstate->nocode); // hashjmp <mode>,i0,nocode + UML_HASHJMP(block, mem(&m_core->mode), I0, *m_nocode); // hashjmp <mode>,i0,nocode UML_LABEL(block, exit); // exit: - UML_MOV(block, mem(&ppc->pc), I0); // mov <pc>,i0 - save_fast_iregs(ppc, block); // <save fastregs> + UML_MOV(block, mem(&m_core->pc), I0); // mov <pc>,i0 + save_fast_iregs(block); // <save fastregs> UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE UML_LABEL(block, isi); // isi: - if (!(ppc->cap & PPCCAP_603_MMU)) + if (!(m_cap & PPCCAP_603_MMU)) { - UML_MOV(block, SPR32(SPROEA_DSISR), mem(&ppc->param0)); // mov [dsisr],[param0] - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_ISI], I0); // exh isi,i0 + UML_MOV(block, SPR32(SPROEA_DSISR), mem(&m_core->param0)); // mov [dsisr],[param0] + UML_EXH(block, *m_exception[EXCEPTION_ISI], I0); // exh isi,i0 } else { UML_MOV(block, SPR32(SPR603_IMISS), I0); // mov [imiss],i0 - UML_MOV(block, SPR32(SPR603_ICMP), mem(&ppc->mmu603_cmp)); // mov [icmp],[mmu603_cmp] - UML_MOV(block, SPR32(SPR603_HASH1), mem(&ppc->mmu603_hash[0])); // mov [hash1],[mmu603_hash][0] - UML_MOV(block, SPR32(SPR603_HASH2), mem(&ppc->mmu603_hash[1])); // mov [hash2],[mmu603_hash][1] - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_ITLBMISS], I0); // exh itlbmiss,i0 + UML_MOV(block, SPR32(SPR603_ICMP), mem(&m_core->mmu603_cmp)); // mov [icmp],[mmu603_cmp] + UML_MOV(block, SPR32(SPR603_HASH1), mem(&m_core->mmu603_hash[0])); // mov [hash1],[mmu603_hash][0] + UML_MOV(block, SPR32(SPR603_HASH2), mem(&m_core->mmu603_hash[1])); // mov [hash2],[mmu603_hash][1] + UML_EXH(block, *m_exception[EXCEPTION_ITLBMISS], I0); // exh itlbmiss,i0 } block->end(); @@ -1255,19 +781,18 @@ static void static_generate_tlb_mismatch(powerpc_state *ppc) exception handler -------------------------------------------------*/ -static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int recover, const char *name) +void ppc_device::static_generate_exception(UINT8 exception, int recover, const char *name) { - drcuml_state *drcuml = ppc->impstate->drcuml; - code_handle *&exception_handle = recover ? ppc->impstate->exception[exception] : ppc->impstate->exception_norecover[exception]; + code_handle *&exception_handle = recover ? m_exception[exception] : m_exception_norecover[exception]; UINT32 vector = exception << 8; code_label label = 1; drcuml_block *block; /* begin generating */ - block = drcuml->begin_block(1024); + block = m_drcuml->begin_block(1024); /* add a global entry for this */ - alloc_handle(drcuml, &exception_handle, name); + alloc_handle(m_drcuml, &exception_handle, name); UML_HANDLE(block, *exception_handle); // handle name /* exception parameter is expected to be the fault address in this case */ @@ -1285,7 +810,7 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r } /* OEA handling of SRR exceptions */ - if (ppc->cap & PPCCAP_OEA) + if (m_cap & PPCCAP_OEA) { UINT32 msrandmask = MSROEA_POW | MSR_EE | MSR_PR | MSROEA_FP | MSROEA_FE0 | MSROEA_SE | MSROEA_BE | MSROEA_FE1 | MSROEA_IR | MSROEA_DR | MSROEA_RI | MSR_LE; UINT32 msrormask = 0; @@ -1296,10 +821,10 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r { code_label not_decrementer; - UML_TEST(block, mem(&ppc->irq_pending), 0x01); // test [irq_pending],0x01 + UML_TEST(block, mem(&m_core->irq_pending), 0x01); // test [irq_pending],0x01 UML_JMPc(block, COND_NZ, not_decrementer = label++); // jmp not_decrementer,nz UML_MOV(block, I3, EXCEPTION_DECREMENT << 8); // mov i3,EXCEPTION_DECREMENT << 8 - UML_AND(block, mem(&ppc->irq_pending), mem(&ppc->irq_pending), ~0x02); // and [irq_pending],[irq_pending],~0x02 + UML_AND(block, mem(&m_core->irq_pending), mem(&m_core->irq_pending), ~0x02); // and [irq_pending],[irq_pending],~0x02 UML_LABEL(block, not_decrementer); // not_decrementer: } @@ -1313,7 +838,7 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r UML_GETEXP(block, I1); // getexp i1 UML_OR(block, SPR32(SPROEA_SRR1), SPR32(SPROEA_SRR1), I1); // or [srr1],[srr1],i1 } - if (ppc->cap & PPCCAP_603_MMU) + if (m_cap & PPCCAP_603_MMU) { if (exception == EXCEPTION_ITLBMISS) UML_OR(block, SPR32(SPROEA_SRR1), SPR32(SPROEA_SRR1), 0x00040000); // or [srr1],0x00040000 @@ -1324,7 +849,7 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r } /* update MSR */ - if (ppc->cap & PPCCAP_603_MMU) + if (m_cap & PPCCAP_603_MMU) { if (exception == EXCEPTION_ITLBMISS || exception == EXCEPTION_DTLBMISSL || exception == EXCEPTION_DTLBMISSS) msrormask |= MSR603_TGPR; @@ -1336,16 +861,16 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r UML_OR(block, I2, I2, msrormask); // or i2,i2,ormask UML_ROLINS(block, I2, I2, 16, MSR_LE); // rolins i2,u2,16,MSR_LE UML_MOV(block, MSR32, I2); // mov [msr],i2 - if (ppc->cap & PPCCAP_603_MMU) + if (m_cap & PPCCAP_603_MMU) { UML_XOR(block, I0, I0, I2); // xor i0,i0,i2 UML_TEST(block, I0, MSR603_TGPR); // test i0,tgpr - UML_CALLHc(block, COND_NZ, *ppc->impstate->swap_tgpr); // callh swap_tgpr,nz + UML_CALLHc(block, COND_NZ, *m_swap_tgpr); // callh swap_tgpr,nz } - generate_update_mode(ppc, block); // <update mode> + generate_update_mode(block); // <update mode> /* determine our target PC */ - if (ppc->flavor == PPC_MODEL_602) + if (m_flavor == PPC_MODEL_602) UML_MOV(block, I0, SPR32(SPR602_IBR)); // mov i0,[ibr] else UML_MOV(block, I0, 0x00000000); // mov i0,0x00000000 @@ -1355,7 +880,7 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r } /* 4XX handling of exceptions */ - if (ppc->cap & PPCCAP_4XX) + if (m_cap & PPCCAP_4XX) { /* check registers to see the real source of our exception (EI exceptions only) */ UML_MOV(block, I3, vector); // mov i3,vector @@ -1397,7 +922,7 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r /* finish updating MSR */ UML_ROLINS(block, I2, I2, 16, MSR_LE); // rolins i2,u2,16,MSR_LE UML_MOV(block, MSR32, I2); // mov [msr],i2 - generate_update_mode(ppc, block); // <update mode> + generate_update_mode(block); // <update mode> /* program exception flags go to ESR */ if (exception == EXCEPTION_PROGRAM) @@ -1415,14 +940,14 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r if ((PRINTF_EXCEPTIONS && exception != EXCEPTION_EI && exception != EXCEPTION_SYSCALL) || (PRINTF_MMU && (exception == EXCEPTION_ISI || exception == EXCEPTION_DSI))) { - UML_MOV(block, mem(&ppc->param0), exception); // mov [param0],exception - UML_CALLC(block, cfunc_printf_exception, ppc); // callc cfunc_printf_exception,ppc + UML_MOV(block, mem(&m_core->param0), exception); // mov [param0],exception + UML_CALLC(block, cfunc_printf_exception, this); // callc cfunc_printf_exception,ppc } /* adjust cycles */ - UML_SUB(block, mem(&ppc->icount), mem(&ppc->icount), I1); // sub icount,icount,cycles - UML_EXHc(block, COND_S, *ppc->impstate->out_of_cycles, I0); // exh out_of_cycles,i0 - UML_HASHJMP(block, mem(&ppc->impstate->mode), I0, *ppc->impstate->nocode); // hashjmp <mode>,i0,nocode + UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), I1); // sub icount,icount,cycles + UML_EXHc(block, COND_S, *m_out_of_cycles, I0); // exh out_of_cycles,i0 + UML_HASHJMP(block, mem(&m_core->mode), I0, *m_nocode); // hashjmp <mode>,i0,nocode block->end(); } @@ -1432,13 +957,12 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r static_generate_memory_accessor ------------------------------------------------------------------*/ -static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int size, int iswrite, int ismasked, const char *name, code_handle *&handleptr, code_handle *masked) +void ppc_device::static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, code_handle *&handleptr, code_handle *masked) { /* on entry, address is in I0; data for writes is in I1; masks are in I2 */ /* on exit, read result is in I0 */ /* routine trashes I0-I3 */ - drcuml_state *drcuml = ppc->impstate->drcuml; - int fastxor = BYTE8_XOR_BE(0) >> (int)(ppc->device->space_config(AS_PROGRAM)->m_databus_width < 64); + int fastxor = BYTE8_XOR_BE(0) >> (int)(space_config(AS_PROGRAM)->m_databus_width < 64); drcuml_block *block; int translate_type; int tlbreturn = 0; @@ -1454,17 +978,17 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si translate_type = iswrite ? TRANSLATE_WRITE : TRANSLATE_READ; /* begin generating */ - block = drcuml->begin_block(1024); + block = m_drcuml->begin_block(1024); /* add a global entry for this */ - alloc_handle(drcuml, &handleptr, name); + alloc_handle(m_drcuml, &handleptr, name); UML_HANDLE(block, *handleptr); // handle *handleptr /* check for unaligned accesses and break into two */ if (!ismasked && size != 1) { /* in little-endian mode, anything misaligned generates an exception */ - if ((mode & MODE_LITTLE_ENDIAN) || masked == NULL || !(ppc->cap & PPCCAP_MISALIGNED)) + if ((mode & MODE_LITTLE_ENDIAN) || masked == NULL || !(m_cap & PPCCAP_MISALIGNED)) { UML_TEST(block, I0, size - 1); // test i0,size-1 UML_JMPc(block, COND_NZ, alignex = label++); // jmp alignex,nz @@ -1494,34 +1018,34 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si } /* general case: assume paging and perform a translation */ - if (((ppc->cap & PPCCAP_OEA) && (mode & MODE_DATA_TRANSLATION)) || (iswrite && (ppc->cap & PPCCAP_4XX) && (mode & MODE_PROTECTION))) + if (((m_cap & PPCCAP_OEA) && (mode & MODE_DATA_TRANSLATION)) || (iswrite && (m_cap & PPCCAP_4XX) && (mode & MODE_PROTECTION))) { UML_SHR(block, I3, I0, 12); // shr i3,i0,12 - UML_LOAD(block, I3, (void *)vtlb_table(ppc->vtlb), I3, SIZE_DWORD, SCALE_x4);// load i3,[vtlb],i3,dword + UML_LOAD(block, I3, (void *)vtlb_table(m_vtlb), I3, SIZE_DWORD, SCALE_x4);// load i3,[vtlb],i3,dword UML_TEST(block, I3, (UINT64)1 << translate_type); // test i3,1 << translate_type UML_JMPc(block, COND_Z, tlbmiss = label++); // jmp tlbmiss,z UML_LABEL(block, tlbreturn = label++); // tlbreturn: UML_ROLINS(block, I0, I3, 0, 0xfffff000); // rolins i0,i3,0,0xfffff000 } - else if (ppc->cap & PPCCAP_4XX) + else if (m_cap & PPCCAP_4XX) UML_AND(block, I0, I0, 0x7fffffff); // and i0,i0,0x7fffffff UML_XOR(block, I0, I0, (mode & MODE_LITTLE_ENDIAN) ? (8 - size) : 0); // xor i0,i0,8-size - if ((ppc->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) for (ramnum = 0; ramnum < PPC_MAX_FASTRAM; ramnum++) - if (ppc->impstate->fastram[ramnum].base != NULL && (!iswrite || !ppc->impstate->fastram[ramnum].readonly)) + if (m_fastram[ramnum].base != NULL && (!iswrite || !m_fastram[ramnum].readonly)) { - void *fastbase = (UINT8 *)ppc->impstate->fastram[ramnum].base - ppc->impstate->fastram[ramnum].start; + void *fastbase = (UINT8 *)m_fastram[ramnum].base - m_fastram[ramnum].start; UINT32 skip = label++; - if (ppc->impstate->fastram[ramnum].end != 0xffffffff) + if (m_fastram[ramnum].end != 0xffffffff) { - UML_CMP(block, I0, ppc->impstate->fastram[ramnum].end); // cmp i0,end + UML_CMP(block, I0, m_fastram[ramnum].end); // cmp i0,end UML_JMPc(block, COND_A, skip); // ja skip } - if (ppc->impstate->fastram[ramnum].start != 0x00000000) + if (m_fastram[ramnum].start != 0x00000000) { - UML_CMP(block, I0, ppc->impstate->fastram[ramnum].start); // cmp i0,fastram_start + UML_CMP(block, I0, m_fastram[ramnum].start); // cmp i0,fastram_start UML_JMPc(block, COND_B, skip); // jb skip } @@ -1661,29 +1185,29 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si { if (iswrite) { - UML_MOV(block, mem(&ppc->impstate->tempaddr), I0); // mov [tempaddr],i0 - UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I1); // mov [tempdata],i1 + UML_MOV(block, mem(&m_core->tempaddr), I0); // mov [tempaddr],i0 + UML_MOV(block, mem(&m_core->tempdata.w.l), I1); // mov [tempdata],i1 UML_SUB(block, I0, I0, 1); // sub i0,i0,1 UML_SHR(block, I1, I1, 8); // shr i1,i1,8 UML_MOV(block, I2, 0x00ff); // mov i2,0x00ff UML_CALLH(block, *masked); // callh masked - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 1); // add i0,[tempaddr],1 - UML_SHL(block, I1, mem(&ppc->impstate->tempdata.w.l), 8); // shl i1,[tempdata],8 + UML_ADD(block, I0, mem(&m_core->tempaddr), 1); // add i0,[tempaddr],1 + UML_SHL(block, I1, mem(&m_core->tempdata.w.l), 8); // shl i1,[tempdata],8 UML_MOV(block, I2, 0xff00); // mov i2,0xff00 UML_CALLH(block, *masked); // callh masked } else { - UML_MOV(block, mem(&ppc->impstate->tempaddr), I0); // mov [tempaddr],i0 + UML_MOV(block, mem(&m_core->tempaddr), I0); // mov [tempaddr],i0 UML_SUB(block, I0, I0, 1); // sub i0,i0,1 UML_MOV(block, I2, 0x00ff); // mov i2,0x00ff UML_CALLH(block, *masked); // callh masked - UML_SHL(block, mem(&ppc->impstate->tempdata.w.l), I0, 8); // shl [tempdata],i0,8 - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 1); // add i0,[tempaddr],1 + UML_SHL(block, mem(&m_core->tempdata.w.l), I0, 8); // shl [tempdata],i0,8 + UML_ADD(block, I0, mem(&m_core->tempaddr), 1); // add i0,[tempaddr],1 UML_MOV(block, I2, 0xff00); // mov i2,0xff00 UML_CALLH(block, *masked); // callh masked UML_SHR(block, I0, I0, 8); // shr i0,i0,8 - UML_OR(block, I0, I0, mem(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] + UML_OR(block, I0, I0, mem(&m_core->tempdata.w.l)); // or i0,i0,[tempdata] } } else if (size == 4) @@ -1691,16 +1215,16 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si int offs2, offs3; if (iswrite) { - UML_MOV(block, mem(&ppc->impstate->tempaddr), I0); // mov [tempaddr],i0 - UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I1); // mov [tempdata],i1 + UML_MOV(block, mem(&m_core->tempaddr), I0); // mov [tempaddr],i0 + UML_MOV(block, mem(&m_core->tempdata.w.l), I1); // mov [tempdata],i1 UML_TEST(block, I0, 2); // test i0,i0,2 UML_JMPc(block, COND_NZ, offs2 = label++); // jnz offs2 UML_SUB(block, I0, I0, 1); // sub i0,i0,1 UML_SHR(block, I1, I1, 8); // shr i1,i1,8 UML_MOV(block, I2, 0x00ffffff); // mov i2,0x00ffffff UML_CALLH(block, *masked); // callh masked - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 3); // add i0,[tempaddr],3 - UML_SHL(block, I1, mem(&ppc->impstate->tempdata.w.l), 24); // shl i1,[tempdata],24 + UML_ADD(block, I0, mem(&m_core->tempaddr), 3); // add i0,[tempaddr],3 + UML_SHL(block, I1, mem(&m_core->tempdata.w.l), 24); // shl i1,[tempdata],24 UML_MOV(block, I2, 0xff000000); // mov i2,0xff000000 UML_CALLH(block, *masked); // callh masked UML_RET(block); // ret @@ -1711,8 +1235,8 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si UML_SHR(block, I1, I1, 16); // shr i1,i1,16 UML_MOV(block, I2, 0x0000ffff); // mov i2,0x0000ffff UML_CALLH(block, *masked); // callh masked - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 2); // add i0,[tempaddr],2 - UML_SHL(block, I1, mem(&ppc->impstate->tempdata.w.l), 16); // shl i1,[tempdata],16 + UML_ADD(block, I0, mem(&m_core->tempaddr), 2); // add i0,[tempaddr],2 + UML_SHL(block, I1, mem(&m_core->tempdata.w.l), 16); // shl i1,[tempdata],16 UML_MOV(block, I2, 0xffff0000); // mov i2,0xffff0000 UML_CALLH(block, *masked); // callh masked UML_RET(block); // ret @@ -1721,25 +1245,25 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si UML_SHR(block, I1, I1, 24); // shr i1,i1,24 UML_MOV(block, I2, 0x000000ff); // mov i2,0x000000ff UML_CALLH(block, *masked); // callh masked - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 1); // add i0,[tempaddr],1 - UML_SHL(block, I1, mem(&ppc->impstate->tempdata.w.l), 8); // shl i1,[tempdata],8 + UML_ADD(block, I0, mem(&m_core->tempaddr), 1); // add i0,[tempaddr],1 + UML_SHL(block, I1, mem(&m_core->tempdata.w.l), 8); // shl i1,[tempdata],8 UML_MOV(block, I2, 0xffffff00); // mov i2,0xffffff00 UML_CALLH(block, *masked); // callh masked } else { - UML_MOV(block, mem(&ppc->impstate->tempaddr), I0); // mov [tempaddr],i0 + UML_MOV(block, mem(&m_core->tempaddr), I0); // mov [tempaddr],i0 UML_TEST(block, I0, 2); // test i0,i0,2 UML_JMPc(block, COND_NZ, offs2 = label++); // jnz offs2 UML_SUB(block, I0, I0, 1); // sub i0,i0,1 UML_MOV(block, I2, 0x00ffffff); // mov i2,0x00ffffff UML_CALLH(block, *masked); // callh masked - UML_SHL(block, mem(&ppc->impstate->tempdata.w.l), I0, 8); // shl [tempdata],i0,8 - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 3); // add i0,[tempaddr],3 + UML_SHL(block, mem(&m_core->tempdata.w.l), I0, 8); // shl [tempdata],i0,8 + UML_ADD(block, I0, mem(&m_core->tempaddr), 3); // add i0,[tempaddr],3 UML_MOV(block, I2, 0xff000000); // mov i2,0xff000000 UML_CALLH(block, *masked); // callh masked UML_SHR(block, I0, I0, 24); // shr i0,i0,24 - UML_OR(block, I0, I0, mem(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] + UML_OR(block, I0, I0, mem(&m_core->tempdata.w.l)); // or i0,i0,[tempdata] UML_RET(block); // ret UML_LABEL(block, offs2); // offs2: UML_TEST(block, I0, 1); // test i0,i0,1 @@ -1747,50 +1271,50 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si UML_SUB(block, I0, I0, 2); // sub i0,i0,2 UML_MOV(block, I2, 0x0000ffff); // mov i2,0x0000ffff UML_CALLH(block, *masked); // callh masked - UML_SHL(block, mem(&ppc->impstate->tempdata.w.l), I0, 16); // shl [tempdata],i0,16 - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 2); // add i0,[tempaddr],2 + UML_SHL(block, mem(&m_core->tempdata.w.l), I0, 16); // shl [tempdata],i0,16 + UML_ADD(block, I0, mem(&m_core->tempaddr), 2); // add i0,[tempaddr],2 UML_MOV(block, I2, 0xffff0000); // mov i2,0xffff0000 UML_CALLH(block, *masked); // callh masked UML_SHR(block, I0, I0, 16); // shr i0,i0,16 - UML_OR(block, I0, I0, mem(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] + UML_OR(block, I0, I0, mem(&m_core->tempdata.w.l)); // or i0,i0,[tempdata] UML_RET(block); // ret UML_LABEL(block, offs3); // offs3: UML_SUB(block, I0, I0, 3); // sub i0,i0,3 UML_MOV(block, I2, 0x000000ff); // mov i2,0x000000ff UML_CALLH(block, *masked); // callh masked - UML_SHL(block, mem(&ppc->impstate->tempdata.w.l), I0, 24); // shl [tempdata],i0,24 - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 1); // add i0,[tempaddr],1 + UML_SHL(block, mem(&m_core->tempdata.w.l), I0, 24); // shl [tempdata],i0,24 + UML_ADD(block, I0, mem(&m_core->tempaddr), 1); // add i0,[tempaddr],1 UML_MOV(block, I2, 0xffffff00); // mov i2,0xffffff00 UML_CALLH(block, *masked); // callh masked UML_SHR(block, I0, I0, 8); // shr i0,i0,8 - UML_OR(block, I0, I0, mem(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] + UML_OR(block, I0, I0, mem(&m_core->tempdata.w.l)); // or i0,i0,[tempdata] } } else if (size == 8) { if (iswrite) { - UML_MOV(block, mem(&ppc->impstate->tempaddr), I0); // mov [tempaddr],i0 - UML_DMOV(block, mem(&ppc->impstate->tempdata.d), I1); // dmov [tempdata],i1 + UML_MOV(block, mem(&m_core->tempaddr), I0); // mov [tempaddr],i0 + UML_DMOV(block, mem(&m_core->tempdata.d), I1); // dmov [tempdata],i1 UML_DSHR(block, I1, I1, 32); // dshr i1,i1,32 UML_DMOV(block, I2, U64(0x00000000ffffffff)); // dmov i2,0x00000000ffffffff UML_CALLH(block, *masked); // callh masked - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 4); // add i0,[tempaddr],4 - UML_DSHL(block, I1, mem(&ppc->impstate->tempdata.d), 32); // dshl i1,[tempdata],32 + UML_ADD(block, I0, mem(&m_core->tempaddr), 4); // add i0,[tempaddr],4 + UML_DSHL(block, I1, mem(&m_core->tempdata.d), 32); // dshl i1,[tempdata],32 UML_DMOV(block, I2, U64(0xffffffff00000000)); // dmov i2,0xffffffff00000000 UML_CALLH(block, *masked); // callh masked } else { - UML_MOV(block, mem(&ppc->impstate->tempaddr), I0); // mov [tempaddr],i0 + UML_MOV(block, mem(&m_core->tempaddr), I0); // mov [tempaddr],i0 UML_DMOV(block, I2, U64(0x00000000ffffffff)); // mov i2,0x00000000ffffffff UML_CALLH(block, *masked); // callh masked - UML_DSHL(block, mem(&ppc->impstate->tempdata.d), I0, 32); // dshl [tempdata],i0,32 - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 4); // add i0,[tempaddr],4 + UML_DSHL(block, mem(&m_core->tempdata.d), I0, 32); // dshl [tempdata],i0,32 + UML_ADD(block, I0, mem(&m_core->tempaddr), 4); // add i0,[tempaddr],4 UML_DMOV(block, I2, U64(0xffffffff00000000)); // dmov i2,0xffffffff00000000 UML_CALLH(block, *masked); // callh masked UML_DSHR(block, I0, I0, 32); // dshr i0,i0,32 - UML_DOR(block, I0, I0, mem(&ppc->impstate->tempdata.d)); // dor i0,i0,[tempdata] + UML_DOR(block, I0, I0, mem(&m_core->tempdata.d)); // dor i0,i0,[tempdata] } } UML_RET(block); // ret @@ -1801,46 +1325,46 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si { UML_LABEL(block, alignex); // alignex: UML_RECOVER(block, SPR32(SPROEA_DSISR), MAPVAR_DSISR); // recover [dsisr],DSISR - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_ALIGN], I0); // exh align,i0 + UML_EXH(block, *m_exception[EXCEPTION_ALIGN], I0); // exh align,i0 } /* handle a TLB miss */ if (tlbmiss != 0) { UML_LABEL(block, tlbmiss); // tlbmiss: - UML_MOV(block, mem(&ppc->param0), I0); // mov [param0],i0 - UML_MOV(block, mem(&ppc->param1), translate_type); // mov [param1],translate_type - UML_CALLC(block, (c_function)ppccom_tlb_fill, ppc); // callc tlbfill,ppc + UML_MOV(block, mem(&m_core->param0), I0); // mov [param0],i0 + UML_MOV(block, mem(&m_core->param1), translate_type); // mov [param1],translate_type + UML_CALLC(block, (c_function)cfunc_ppccom_tlb_fill, this); // callc tlbfill,ppc UML_SHR(block, I3, I0, 12); // shr i3,i0,12 - UML_LOAD(block, I3, (void *)vtlb_table(ppc->vtlb), I3, SIZE_DWORD, SCALE_x4);// load i3,[vtlb],i3,dword + UML_LOAD(block, I3, (void *)vtlb_table(m_vtlb), I3, SIZE_DWORD, SCALE_x4);// load i3,[vtlb],i3,dword UML_TEST(block, I3, (UINT64)1 << translate_type); // test i3,1 << translate_type UML_JMPc(block, COND_NZ, tlbreturn); // jmp tlbreturn,nz /* 4XX case: protection exception */ - if (ppc->cap & PPCCAP_4XX) + if (m_cap & PPCCAP_4XX) { UML_MOV(block, SPR32(SPR4XX_DEAR), I0); // mov [dear],i0 - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DSI], I0); // exh dsi,i0 + UML_EXH(block, *m_exception[EXCEPTION_DSI], I0); // exh dsi,i0 } /* 603 case: TLBMISS exception */ - else if (ppc->cap & PPCCAP_603_MMU) + else if (m_cap & PPCCAP_603_MMU) { UML_MOV(block, SPR32(SPR603_DMISS), I0); // mov [dmiss],i0 - UML_MOV(block, SPR32(SPR603_DCMP), mem(&ppc->mmu603_cmp)); // mov [dcmp],[mmu603_cmp] - UML_MOV(block, SPR32(SPR603_HASH1), mem(&ppc->mmu603_hash[0])); // mov [hash1],[mmu603_hash][0] - UML_MOV(block, SPR32(SPR603_HASH2), mem(&ppc->mmu603_hash[1])); // mov [hash2],[mmu603_hash][1] + UML_MOV(block, SPR32(SPR603_DCMP), mem(&m_core->mmu603_cmp)); // mov [dcmp],[mmu603_cmp] + UML_MOV(block, SPR32(SPR603_HASH1), mem(&m_core->mmu603_hash[0])); // mov [hash1],[mmu603_hash][0] + UML_MOV(block, SPR32(SPR603_HASH2), mem(&m_core->mmu603_hash[1])); // mov [hash2],[mmu603_hash][1] if (iswrite) - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DTLBMISSS], I0); // exh dtlbmisss,i0 + UML_EXH(block, *m_exception[EXCEPTION_DTLBMISSS], I0); // exh dtlbmisss,i0 else - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DTLBMISSL], I0); // exh dtlbmissl,i0 + UML_EXH(block, *m_exception[EXCEPTION_DTLBMISSL], I0); // exh dtlbmissl,i0 } /* general case: DSI exception */ else { - UML_MOV(block, SPR32(SPROEA_DSISR), mem(&ppc->param0)); // mov [dsisr],[param0] - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DSI], I0); // exh dsi,i0 + UML_MOV(block, SPR32(SPROEA_DSISR), mem(&m_core->param0)); // mov [dsisr],[param0] + UML_EXH(block, *m_exception[EXCEPTION_DSI], I0); // exh dsi,i0 } } @@ -1853,23 +1377,22 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si subroutine to swap GPR0-3 with TGPR0-3 -------------------------------------------------*/ -static void static_generate_swap_tgpr(powerpc_state *ppc) +void ppc_device::static_generate_swap_tgpr() { - drcuml_state *drcuml = ppc->impstate->drcuml; drcuml_block *block; int regnum; /* begin generating */ - block = drcuml->begin_block(30); + block = m_drcuml->begin_block(30); /* generate a hash jump via the current mode and PC */ - alloc_handle(drcuml, &ppc->impstate->swap_tgpr, "swap_tgpr"); - UML_HANDLE(block, *ppc->impstate->swap_tgpr); // handle swap_tgpr + alloc_handle(m_drcuml, &m_swap_tgpr, "swap_tgpr"); + UML_HANDLE(block, *m_swap_tgpr); // handle swap_tgpr for (regnum = 0; regnum < 4; regnum++) { UML_MOV(block, I1, R32(regnum)); // mov i1,r[regnum] - UML_MOV(block, R32(regnum), mem(&ppc->mmu603_r[regnum])); // mov r[regnum],mmu603_r[regnum] - UML_MOV(block, mem(&ppc->mmu603_r[regnum]), I1); // mov mmu603_r[regnum],i1 + UML_MOV(block, R32(regnum), mem(&m_core->mmu603_r[regnum])); // mov r[regnum],mmu603_r[regnum] + UML_MOV(block, mem(&m_core->mmu603_r[regnum]), I1); // mov mmu603_r[regnum],i1 } UML_RET(block); // ret @@ -1883,14 +1406,13 @@ static void static_generate_swap_tgpr(powerpc_state *ppc) for each possible register -------------------------------------------------*/ -static void static_generate_lsw_entries(powerpc_state *ppc, int mode) +void ppc_device::static_generate_lsw_entries(int mode) { - drcuml_state *drcuml = ppc->impstate->drcuml; drcuml_block *block; int regnum; /* begin generating */ - block = drcuml->begin_block(32 * 30); + block = m_drcuml->begin_block(32 * 30); /* iterate over all possible registers */ for (regnum = 0; regnum < 32; regnum++) @@ -1899,32 +1421,32 @@ static void static_generate_lsw_entries(powerpc_state *ppc, int mode) /* allocate a handle */ sprintf(temp, "lsw%d", regnum); - alloc_handle(drcuml, &ppc->impstate->lsw[mode][regnum], temp); - UML_HANDLE(block, *ppc->impstate->lsw[mode][regnum]); // handle lsw<regnum> + alloc_handle(m_drcuml, &m_lsw[mode][regnum], temp); + UML_HANDLE(block, *m_lsw[mode][regnum]); // handle lsw<regnum> UML_LABEL(block, regnum); // regnum: - UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 0); // add i0,[updateaddr],0 - UML_CALLH(block, *ppc->impstate->read8[mode]); // callh read8 + UML_ADD(block, I0, mem(&m_core->updateaddr), 0); // add i0,[updateaddr],0 + UML_CALLH(block, *m_read8[mode]); // callh read8 UML_ROLAND(block, R32(regnum), I0, 24, 0xff000000); // roland reg,i0,24,0xff000000 - UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_SUB(block, mem(&m_core->swcount), mem(&m_core->swcount), 1); // sub [swcount],[swcount],1 UML_RETc(block, COND_Z); // ret z - UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 1); // add i0,[updateaddr],1 - UML_CALLH(block, *ppc->impstate->read8[mode]); // callh read8 + UML_ADD(block, I0, mem(&m_core->updateaddr), 1); // add i0,[updateaddr],1 + UML_CALLH(block, *m_read8[mode]); // callh read8 UML_ROLAND(block, I0, I0, 16, 0x00ff0000); // roland i0,i0,16,0x00ff0000 UML_OR(block, R32(regnum), R32(regnum), I0); // or reg,i0 - UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_SUB(block, mem(&m_core->swcount), mem(&m_core->swcount), 1); // sub [swcount],[swcount],1 UML_RETc(block, COND_Z); // ret z - UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 2); // add i0,[updateaddr],2 - UML_CALLH(block, *ppc->impstate->read8[mode]); // callh read8 + UML_ADD(block, I0, mem(&m_core->updateaddr), 2); // add i0,[updateaddr],2 + UML_CALLH(block, *m_read8[mode]); // callh read8 UML_ROLAND(block, I0, I0, 8, 0x0000ff00); // roland i0,i0,8,0x0000ff00 UML_OR(block, R32(regnum), R32(regnum), I0); // or reg,i0 - UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_SUB(block, mem(&m_core->swcount), mem(&m_core->swcount), 1); // sub [swcount],[swcount],1 UML_RETc(block, COND_Z); // ret z - UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 3); // add i0,[updateaddr],3 - UML_ADD(block, mem(&ppc->impstate->updateaddr), I0, 1); // add [updateaddr],i0,1 - UML_CALLH(block, *ppc->impstate->read8[mode]); // callh read8 + UML_ADD(block, I0, mem(&m_core->updateaddr), 3); // add i0,[updateaddr],3 + UML_ADD(block, mem(&m_core->updateaddr), I0, 1); // add [updateaddr],i0,1 + UML_CALLH(block, *m_read8[mode]); // callh read8 UML_ROLAND(block, I0, I0, 0, 0x000000ff); // roland i0,i0,0,0x000000ff UML_OR(block, R32(regnum), R32(regnum), I0); // or reg,i0 - UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_SUB(block, mem(&m_core->swcount), mem(&m_core->swcount), 1); // sub [swcount],[swcount],1 UML_RETc(block, COND_Z); // ret z UML_JMP(block, (regnum + 1) % 32); // jmp nextreg } @@ -1939,45 +1461,43 @@ static void static_generate_lsw_entries(powerpc_state *ppc, int mode) for each possible register -------------------------------------------------*/ -static void static_generate_stsw_entries(powerpc_state *ppc, int mode) +void ppc_device::static_generate_stsw_entries(int mode) { - drcuml_state *drcuml = ppc->impstate->drcuml; drcuml_block *block; - int regnum; /* begin generating */ - block = drcuml->begin_block(32 * 30); + block = m_drcuml->begin_block(32 * 30); /* iterate over all possible registers */ - for (regnum = 0; regnum < 32; regnum++) + for (int regnum = 0; regnum < 32; regnum++) { char temp[20]; /* allocate a handle */ sprintf(temp, "stsw%d", regnum); - alloc_handle(drcuml, &ppc->impstate->stsw[mode][regnum], temp); - UML_HANDLE(block, *ppc->impstate->stsw[mode][regnum]); // handle stsw<regnum> + alloc_handle(m_drcuml, &m_stsw[mode][regnum], temp); + UML_HANDLE(block, *m_stsw[mode][regnum]); // handle stsw<regnum> UML_LABEL(block, regnum); // regnum: - UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 0); // add i0,[updateaddr],0 + UML_ADD(block, I0, mem(&m_core->updateaddr), 0); // add i0,[updateaddr],0 UML_ROLAND(block, I1, R32(regnum), 8, 0xff); // roland i1,regnum,8,0xff - UML_CALLH(block, *ppc->impstate->write8[mode]); // callh write8 - UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_CALLH(block, *m_write8[mode]); // callh write8 + UML_SUB(block, mem(&m_core->swcount), mem(&m_core->swcount), 1); // sub [swcount],[swcount],1 UML_RETc(block, COND_Z); // ret z - UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 1); // add i0,[updateaddr],1 + UML_ADD(block, I0, mem(&m_core->updateaddr), 1); // add i0,[updateaddr],1 UML_ROLAND(block, I1, R32(regnum), 16, 0xff); // roland i1,regnum,16,0xff - UML_CALLH(block, *ppc->impstate->write8[mode]); // callh write8 - UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_CALLH(block, *m_write8[mode]); // callh write8 + UML_SUB(block, mem(&m_core->swcount), mem(&m_core->swcount), 1); // sub [swcount],[swcount],1 UML_RETc(block, COND_Z); // ret z - UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 2); // add i0,[updateaddr],2 + UML_ADD(block, I0, mem(&m_core->updateaddr), 2); // add i0,[updateaddr],2 UML_ROLAND(block, I1, R32(regnum), 24, 0xff); // roland i1,regnum,24,0xff - UML_CALLH(block, *ppc->impstate->write8[mode]); // callh write8 - UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_CALLH(block, *m_write8[mode]); // callh write8 + UML_SUB(block, mem(&m_core->swcount), mem(&m_core->swcount), 1); // sub [swcount],[swcount],1 UML_RETc(block, COND_Z); // ret z - UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 3); // add i0,[updateaddr],3 - UML_ADD(block, mem(&ppc->impstate->updateaddr), I0, 1); // add [updateaddr],i0,1 + UML_ADD(block, I0, mem(&m_core->updateaddr), 3); // add i0,[updateaddr],3 + UML_ADD(block, mem(&m_core->updateaddr), I0, 1); // add [updateaddr],i0,1 UML_ROLAND(block, I1, R32(regnum), 0, 0xff); // roland i1,regnum,0,0xff - UML_CALLH(block, *ppc->impstate->write8[mode]); // callh write8 - UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_CALLH(block, *m_write8[mode]); // callh write8 + UML_SUB(block, mem(&m_core->swcount), mem(&m_core->swcount), 1); // sub [swcount],[swcount],1 UML_RETc(block, COND_Z); // ret z UML_JMP(block, (regnum + 1) % 32); // jmp nextreg } @@ -1996,20 +1516,20 @@ static void static_generate_stsw_entries(powerpc_state *ppc, int mode) on the MSR -------------------------------------------------*/ -static void generate_update_mode(powerpc_state *ppc, drcuml_block *block) +void ppc_device::generate_update_mode(drcuml_block *block) { /* LE in bit 0 of mode */ UML_AND(block, I0, MSR32, MSR_LE); // and i0,msr,MSR_LE /* DR (OEA and 403GCX) in bit 1 of mode */ - if ((ppc->cap & PPCCAP_OEA) || ppc->flavor == PPC_MODEL_403GCX) + if ((m_cap & PPCCAP_OEA) || m_flavor == PPC_MODEL_403GCX) { UML_ROLAND(block, I1, MSR32, 29, 0x02); // roland i1,[msr],29,0x02 UML_OR(block, I0, I0, I1); // or i0,i0,i1 } /* (4XX) in bit 1 of mode */ - if (ppc->cap & PPCCAP_4XX) + if (m_cap & PPCCAP_4XX) { UML_ROLAND(block, I1, MSR32, 30, 0x02); // roland i1,[msr],30,0x02 UML_OR(block, I0, I0, I1); // or i0,i0,i1 @@ -2017,7 +1537,7 @@ static void generate_update_mode(powerpc_state *ppc, drcuml_block *block) /* PR in bit 2 of mode */ UML_ROLAND(block, I1, MSR32, 20, 0x04); // roland i1,[msr],20,0x04 - UML_OR(block, mem(&ppc->impstate->mode), I0, I1); // or [mode],i0,i1 + UML_OR(block, mem(&m_core->mode), I0, I1); // or [mode],i0,i1 } @@ -2027,7 +1547,7 @@ static void generate_update_mode(powerpc_state *ppc, drcuml_block *block) an exception if out -------------------------------------------------*/ -static void generate_update_cycles(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception) +void ppc_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception) { /* check full interrupts if pending */ if (compiler->checkints) @@ -2035,23 +1555,23 @@ static void generate_update_cycles(powerpc_state *ppc, drcuml_block *block, comp code_label skip; compiler->checkints = FALSE; - UML_TEST(block, mem(&ppc->irq_pending), ~0); // test [irq_pending],0 + UML_TEST(block, mem(&m_core->irq_pending), ~0); // test [irq_pending],0 UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z UML_TEST(block, MSR32, MSR_EE); // test [msr],MSR_EE UML_JMPc(block, COND_Z, skip); // jmp skip,Z UML_MOV(block, I0, param); // mov i0,nextpc UML_MOV(block, I1, compiler->cycles); // mov i1,cycles - UML_CALLH(block, *ppc->impstate->exception_norecover[EXCEPTION_EI]); // callh interrupt_norecover + UML_CALLH(block, *m_exception_norecover[EXCEPTION_EI]); // callh interrupt_norecover UML_LABEL(block, skip); // skip: } /* account for cycles */ if (compiler->cycles > 0) { - UML_SUB(block, mem(&ppc->icount), mem(&ppc->icount), MAPVAR_CYCLES); // sub icount,icount,cycles + UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), MAPVAR_CYCLES); // sub icount,icount,cycles UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0 if (allow_exception) - UML_EXHc(block, COND_S, *ppc->impstate->out_of_cycles, param); // exh out_of_cycles,nextpc + UML_EXHc(block, COND_S, *m_out_of_cycles, param); // exh out_of_cycles,nextpc } compiler->cycles = 0; } @@ -2062,21 +1582,21 @@ static void generate_update_cycles(powerpc_state *ppc, drcuml_block *block, comp validate a sequence of opcodes -------------------------------------------------*/ -static void generate_checksum_block(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast) +void ppc_device::generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast) { const opcode_desc *curdesc; if (LOG_UML) block->append_comment("[Validation for %08X]", seqhead->pc); // comment /* loose verify or single instruction: just compare and fail */ - if (!(ppc->impstate->drcoptions & PPCDRC_STRICT_VERIFY) || seqhead->next() == NULL) + if (!(m_drcoptions & PPCDRC_STRICT_VERIFY) || seqhead->next() == NULL) { if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP)) { - void *base = ppc->direct->read_decrypted_ptr(seqhead->physpc, ppc->codexor); + void *base = m_direct->read_decrypted_ptr(seqhead->physpc, m_codexor); UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,dword UML_CMP(block, I0, seqhead->opptr.l[0]); // cmp i0,*opptr - UML_EXHc(block, COND_NE, *ppc->impstate->nocode, seqhead->pc); // exne nocode,seqhead->pc + UML_EXHc(block, COND_NE, *m_nocode, seqhead->pc); // exne nocode,seqhead->pc } } @@ -2087,26 +1607,26 @@ static void generate_checksum_block(powerpc_state *ppc, drcuml_block *block, com for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next()) if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { - void *base = ppc->direct->read_decrypted_ptr(seqhead->physpc, ppc->codexor); + void *base = m_direct->read_decrypted_ptr(seqhead->physpc, m_codexor); UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,dword UML_CMP(block, I0, curdesc->opptr.l[0]); // cmp i0,*opptr - UML_EXHc(block, COND_NE, *ppc->impstate->nocode, seqhead->pc); // exne nocode,seqhead->pc + UML_EXHc(block, COND_NE, *m_nocode, seqhead->pc); // exne nocode,seqhead->pc } #else UINT32 sum = 0; - void *base = ppc->direct->read_decrypted_ptr(seqhead->physpc, ppc->codexor); + void *base = m_direct->read_decrypted_ptr(seqhead->physpc, m_codexor); UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,dword sum += seqhead->opptr.l[0]; for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next()) if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { - base = ppc->direct->read_decrypted_ptr(curdesc->physpc, ppc->codexor); + base = m_direct->read_decrypted_ptr(curdesc->physpc, m_codexor); UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += curdesc->opptr.l[0]; } UML_CMP(block, I0, sum); // cmp i0,sum - UML_EXHc(block, COND_NE, *ppc->impstate->nocode, seqhead->pc); // exne nocode,seqhead->pc + UML_EXHc(block, COND_NE, *m_nocode, seqhead->pc); // exne nocode,seqhead->pc #endif } } @@ -2117,7 +1637,7 @@ static void generate_checksum_block(powerpc_state *ppc, drcuml_block *block, com for a single instruction in a sequence -------------------------------------------------*/ -static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +void ppc_device::generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { int hotnum; @@ -2133,9 +1653,9 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc /* is this a hotspot? */ for (hotnum = 0; hotnum < PPC_MAX_HOTSPOTS; hotnum++) - if (ppc->impstate->hotspot[hotnum].pc != 0 && desc->pc == ppc->impstate->hotspot[hotnum].pc && desc->opptr.l[0] == ppc->impstate->hotspot[hotnum].opcode) + if (m_hotspot[hotnum].pc != 0 && desc->pc == m_hotspot[hotnum].pc && desc->opptr.l[0] == m_hotspot[hotnum].opcode) { - compiler->cycles += ppc->impstate->hotspot[hotnum].cycles; + compiler->cycles += m_hotspot[hotnum].cycles; break; } @@ -2145,23 +1665,23 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc /* if we want a probe, add it here */ if (desc->pc == PROBE_ADDRESS) { - UML_MOV(block, mem(&ppc->pc), desc->pc); // mov [pc],desc->pc + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc UML_CALLC(block, cfunc_printf_probe, (void *)(FPTR)desc->pc); // callc cfunc_printf_probe,desc->pc } /* if we are debugging, call the debugger */ - if ((ppc->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) { - UML_MOV(block, mem(&ppc->pc), desc->pc); // mov [pc],desc->pc - save_fast_iregs(ppc, block); // <save fastregs> + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc + save_fast_iregs(block); // <save fastregs> UML_DEBUG(block, desc->pc); // debug desc->pc } /* if we hit an unmapped address, fatal error */ if (desc->flags & OPFLAG_COMPILER_UNMAPPED) { - UML_MOV(block, mem(&ppc->pc), desc->pc); // mov [pc],desc->pc - save_fast_iregs(ppc, block); // <save fastregs> + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc + save_fast_iregs(block); // <save fastregs> UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE } @@ -2171,17 +1691,17 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc if (PRINTF_MMU) { const char *text = "Compiler page fault @ %08X\n"; - UML_MOV(block, mem(&ppc->impstate->format), (FPTR)text); // mov [format],text - UML_MOV(block, mem(&ppc->impstate->arg0), desc->pc); // mov [arg0],desc->pc - UML_CALLC(block, cfunc_printf_debug, ppc); // callc printf_debug + UML_MOV(block, mem(&m_core->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&m_core->arg0), desc->pc); // mov [arg0],desc->pc + UML_CALLC(block, cfunc_printf_debug, this); // callc printf_debug } - UML_EXH(block, *ppc->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0 + UML_EXH(block, *m_tlb_mismatch, 0); // exh tlb_mismatch,0 } /* validate our TLB entry at this PC; if we fail, we need to handle it */ - if ((desc->flags & OPFLAG_VALIDATE_TLB) && (ppc->impstate->mode & MODE_DATA_TRANSLATION)) + if ((desc->flags & OPFLAG_VALIDATE_TLB) && (m_core->mode & MODE_DATA_TRANSLATION)) { - const vtlb_entry *tlbtable = vtlb_table(ppc->vtlb); + const vtlb_entry *tlbtable = vtlb_table(m_vtlb); /* if we currently have a valid TLB read entry, we just verify */ if (tlbtable[desc->pc >> 12] != 0) @@ -2189,13 +1709,13 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc if (PRINTF_MMU) { const char *text = "Checking TLB at @ %08X\n"; - UML_MOV(block, mem(&ppc->impstate->format), (FPTR)text); // mov [format],text - UML_MOV(block, mem(&ppc->impstate->arg0), desc->pc); // mov [arg0],desc->pc - UML_CALLC(block, cfunc_printf_debug, ppc); // callc printf_debug + UML_MOV(block, mem(&m_core->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&m_core->arg0), desc->pc); // mov [arg0],desc->pc + UML_CALLC(block, cfunc_printf_debug, this); // callc printf_debug } UML_LOAD(block, I0, &tlbtable[desc->pc >> 12], 0, SIZE_DWORD, SCALE_x4);// load i0,tlbtable[desc->pc >> 12],dword UML_CMP(block, I0, tlbtable[desc->pc >> 12]); // cmp i0,*tlbentry - UML_EXHc(block, COND_NE, *ppc->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0,NE + UML_EXHc(block, COND_NE, *m_tlb_mismatch, 0); // exh tlb_mismatch,0,NE } /* otherwise, we generate an unconditional exception */ @@ -2204,31 +1724,31 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc if (PRINTF_MMU) { const char *text = "No valid TLB @ %08X\n"; - UML_MOV(block, mem(&ppc->impstate->format), (FPTR)text); // mov [format],text - UML_MOV(block, mem(&ppc->impstate->arg0), desc->pc); // mov [arg0],desc->pc - UML_CALLC(block, cfunc_printf_debug, ppc); // callc printf_debug + UML_MOV(block, mem(&m_core->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&m_core->arg0), desc->pc); // mov [arg0],desc->pc + UML_CALLC(block, cfunc_printf_debug, this); // callc printf_debug } - UML_EXH(block, *ppc->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0 + UML_EXH(block, *m_tlb_mismatch, 0); // exh tlb_mismatch,0 } } /* if this is an invalid opcode, generate the exception now */ if (desc->flags & OPFLAG_INVALID_OPCODE) - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x80000); // exh exception_program,0x80000 + UML_EXH(block, *m_exception[EXCEPTION_PROGRAM], 0x80000); // exh exception_program,0x80000 /* if this is a privileged opcode in user mode, generate the exception */ - else if ((desc->flags & OPFLAG_PRIVILEGED) && (ppc->impstate->mode & MODE_USER)) - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x40000); // exh exception_program,0x40000 + else if ((desc->flags & OPFLAG_PRIVILEGED) && (m_core->mode & MODE_USER)) + UML_EXH(block, *m_exception[EXCEPTION_PROGRAM], 0x40000); // exh exception_program,0x40000 /* otherwise, unless this is a virtual no-op, it's a regular instruction */ else if (!(desc->flags & OPFLAG_VIRTUAL_NOOP)) { /* compile the instruction */ - if (!generate_opcode(ppc, block, compiler, desc)) + if (!generate_opcode(block, compiler, desc)) { - UML_MOV(block, mem(&ppc->pc), desc->pc); // mov [pc],desc->pc - UML_MOV(block, mem(&ppc->impstate->arg0), desc->opptr.l[0]); // mov [arg0],*desc->opptr.l - UML_CALLC(block, cfunc_unimplemented, ppc); // callc cfunc_unimplemented,ppc + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc + UML_MOV(block, mem(&m_core->arg0), desc->opptr.l[0]); // mov [arg0],*desc->opptr.l + UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc } } } @@ -2238,7 +1758,7 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc generate_compute_flags - compute CR0 and/or XER flags ------------------------------------------------------------------*/ -static void generate_compute_flags(powerpc_state *ppc, drcuml_block *block, const opcode_desc *desc, int updatecr, UINT32 xermask, int invertcarry) +void ppc_device::generate_compute_flags(drcuml_block *block, const opcode_desc *desc, int updatecr, UINT32 xermask, int invertcarry) { UINT32 xerflags; @@ -2260,7 +1780,7 @@ static void generate_compute_flags(powerpc_state *ppc, drcuml_block *block, cons if (xermask == 0) { UML_GETFLGS(block, I0, FLAG_S | FLAG_Z); // getflgs i0,sz - UML_LOAD(block, I0, ppc->impstate->sz_cr_table, I0, SIZE_BYTE, SCALE_x1); // load i0,sz_cr_table,i0,byte + UML_LOAD(block, I0, m_sz_cr_table, I0, SIZE_BYTE, SCALE_x1); // load i0,sz_cr_table,i0,byte UML_OR(block, CR32(0), I0, XERSO32); // or [cr0],i0,[xerso] return; } @@ -2287,7 +1807,7 @@ static void generate_compute_flags(powerpc_state *ppc, drcuml_block *block, cons /* tricky case: both */ UML_GETFLGS(block, I0, FLAG_S | FLAG_Z | xerflags); // getflgs i0,SZ | xerflags - UML_LOAD(block, I1, ppc->impstate->sz_cr_table, I0, SIZE_BYTE, SCALE_x1); // load i1,sz_cr_table,i0,byte + UML_LOAD(block, I1, m_sz_cr_table, I0, SIZE_BYTE, SCALE_x1); // load i1,sz_cr_table,i0,byte if (invertcarry && (xermask & XER_CA)) UML_XOR(block, I0, I0, FLAG_C); // xor i0,i0,FLAG_C UML_ROLINS(block, SPR32(SPR_XER), I0, 29, xermask); // rolins [xer],i0,29,xermask @@ -2309,7 +1829,7 @@ static void generate_compute_flags(powerpc_state *ppc, drcuml_block *block, cons generate_shift_flags - compute S/Z flags for shifts -------------------------------------------------------*/ -static void generate_shift_flags(powerpc_state *ppc, drcuml_block *block, const opcode_desc *desc, UINT32 op) +void ppc_device::generate_shift_flags(drcuml_block *block, const opcode_desc *desc, UINT32 op) { UML_CMP(block, R32(G_RA(op)), 0); // cmp ra, #0 UML_SETc(block, COND_Z, I1); // set Z, i1 @@ -2318,7 +1838,7 @@ static void generate_shift_flags(powerpc_state *ppc, drcuml_block *block, const UML_SHR(block, I2, R32(G_RA(op)), 28); // shr i2, ra, #28 UML_AND(block, I2, I2, FLAG_S); // and i2, i2, FLAG_S (i2 now = FLAG_S) UML_OR(block, I1, I1, I2); // or i1, i1, i2 - UML_LOAD(block, I0, ppc->impstate->sz_cr_table, I1, SIZE_BYTE, SCALE_x1); // load i0,sz_cr_table,i0,byte + UML_LOAD(block, I0, m_sz_cr_table, I1, SIZE_BYTE, SCALE_x1); // load i0,sz_cr_table,i0,byte UML_OR(block, CR32(0), I0, XERSO32); // or [cr0],i0,[xerso] } @@ -2327,13 +1847,13 @@ static void generate_shift_flags(powerpc_state *ppc, drcuml_block *block, const point status flags -------------------------------------------------*/ -static void generate_fp_flags(powerpc_state *ppc, drcuml_block *block, const opcode_desc *desc, int updatefprf) +void ppc_device::generate_fp_flags(drcuml_block *block, const opcode_desc *desc, int updatefprf) { /* for now, only handle the FPRF field */ if (updatefprf) { - UML_MOV(block, mem(&ppc->param0), G_RD(desc->opptr.l[0])); - UML_CALLC(block, (c_function)ppccom_update_fprf, ppc); + UML_MOV(block, mem(&m_core->param0), G_RD(desc->opptr.l[0])); + UML_CALLC(block, (c_function)cfunc_ppccom_update_fprf, this); } } @@ -2342,18 +1862,18 @@ static void generate_fp_flags(powerpc_state *ppc, drcuml_block *block, const opc branch -------------------------------------------------*/ -static void generate_branch(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int source, UINT8 link) +void ppc_device::generate_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int source, UINT8 link) { compiler_state compiler_temp = *compiler; - UINT32 *srcptr = &ppc->spr[source]; + UINT32 *srcptr = &m_core->spr[source]; /* set the link if needed */ if (link) { if (desc->targetpc == BRANCH_TARGET_DYNAMIC && source == SPR_LR) { - UML_MOV(block, mem(&ppc->impstate->tempaddr), mem(srcptr)); // mov [tempaddr],[lr] - srcptr = &ppc->impstate->tempaddr; + UML_MOV(block, mem(&m_core->tempaddr), mem(srcptr)); // mov [tempaddr],[lr] + srcptr = &m_core->tempaddr; } UML_MOV(block, SPR32(SPR_LR), desc->pc + 4); // mov [lr],desc->pc + 4 } @@ -2361,17 +1881,17 @@ static void generate_branch(powerpc_state *ppc, drcuml_block *block, compiler_st /* update the cycles and jump through the hash table to the target */ if (desc->targetpc != BRANCH_TARGET_DYNAMIC) { - generate_update_cycles(ppc, block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles> + generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles> if (desc->flags & OPFLAG_INTRABLOCK_BRANCH) UML_JMP(block, desc->targetpc | 0x80000000); // jmp desc->targetpc | 0x80000000 else - UML_HASHJMP(block, ppc->impstate->mode, desc->targetpc, *ppc->impstate->nocode); + UML_HASHJMP(block, m_core->mode, desc->targetpc, *m_nocode); // hashjmp <mode>,desc->targetpc,nocode } else { - generate_update_cycles(ppc, block, &compiler_temp, mem(srcptr), TRUE); // <subtract cycles> - UML_HASHJMP(block, ppc->impstate->mode, mem(srcptr), *ppc->impstate->nocode); // hashjmp <mode>,<rsreg>,nocode + generate_update_cycles(block, &compiler_temp, mem(srcptr), TRUE); // <subtract cycles> + UML_HASHJMP(block, m_core->mode, mem(srcptr), *m_nocode); // hashjmp <mode>,<rsreg>,nocode } /* update the label */ @@ -2387,7 +1907,7 @@ static void generate_branch(powerpc_state *ppc, drcuml_block *block, compiler_st branch based on the BO and BI fields -------------------------------------------------*/ -static void generate_branch_bo(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 bo, UINT32 bi, int source, int link) +void ppc_device::generate_branch_bo(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 bo, UINT32 bi, int source, int link) { int skip = compiler->labelnum++; @@ -2401,7 +1921,7 @@ static void generate_branch_bo(powerpc_state *ppc, drcuml_block *block, compiler UML_TEST(block, CR32(bi / 4), 8 >> (bi % 4)); // test cr32(bi/4),8 >> (bi % 4) UML_JMPc(block, (bo & 0x08) ? COND_Z : COND_NZ, skip); // jmp skip,z/nz } - generate_branch(ppc, block, compiler, desc, source, link); // <branch> + generate_branch(block, compiler, desc, source, link); // <branch> UML_LABEL(block, skip); // skip: } @@ -2411,11 +1931,10 @@ static void generate_branch_bo(powerpc_state *ppc, drcuml_block *block, compiler opcode -------------------------------------------------*/ -static int generate_opcode(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { UINT32 op = desc->opptr.l[0]; UINT32 opswitch = op >> 26; - int regnum; switch (opswitch) { @@ -2428,15 +1947,15 @@ static int generate_opcode(powerpc_state *ppc, drcuml_block *block, compiler_sta case 0x03: /* TWI */ UML_CMP(block, R32(G_RA(op)), (INT16)G_SIMM(op)); // cmp ra,simm if (G_TO(op) & 0x10) - UML_EXHc(block, COND_L, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,l + UML_EXHc(block, COND_L, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,l if (G_TO(op) & 0x08) - UML_EXHc(block, COND_G, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,g + UML_EXHc(block, COND_G, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,g if (G_TO(op) & 0x04) - UML_EXHc(block, COND_E, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,e + UML_EXHc(block, COND_E, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,e if (G_TO(op) & 0x02) - UML_EXHc(block, COND_B, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,b + UML_EXHc(block, COND_B, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,b if (G_TO(op) & 0x01) - UML_EXHc(block, COND_A, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,a + UML_EXHc(block, COND_A, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,a return TRUE; case 0x07: /* MULLI */ @@ -2455,67 +1974,67 @@ static int generate_opcode(powerpc_state *ppc, drcuml_block *block, compiler_sta case 0x0a: /* CMPLI */ UML_CMP(block, R32(G_RA(op)), G_UIMM(op)); // cmp ra,uimm UML_GETFLGS(block, I0, FLAG_Z | FLAG_C); // getflgs i0,zc - UML_LOAD(block, I0, ppc->impstate->cmpl_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmpl_cr_table,i0,byte + UML_LOAD(block, I0, m_cmpl_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmpl_cr_table,i0,byte UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] return TRUE; case 0x0b: /* CMPI */ UML_CMP(block, R32(G_RA(op)), (INT16)G_SIMM(op)); // cmp ra,uimm UML_GETFLGS(block, I0, FLAG_Z | FLAG_V | FLAG_C | FLAG_S); // getflgs i0,zvcs - UML_LOAD(block, I0, ppc->impstate->cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte + UML_LOAD(block, I0, m_cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] return TRUE; case 0x08: /* SUBFIC */ UML_SUB(block, R32(G_RD(op)), (INT16)G_SIMM(op), R32(G_RA(op))); // sub rd,simm,ra - generate_compute_flags(ppc, block, desc, FALSE, XER_CA, TRUE); // <update flags> + generate_compute_flags(block, desc, FALSE, XER_CA, TRUE); // <update flags> return TRUE; case 0x0c: /* ADDIC */ UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), (INT16)G_SIMM(op)); // add rd,ra,simm - generate_compute_flags(ppc, block, desc, FALSE, XER_CA, FALSE); // <update flags> + generate_compute_flags(block, desc, FALSE, XER_CA, FALSE); // <update flags> return TRUE; case 0x0d: /* ADDIC. */ UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), (INT16)G_SIMM(op)); // add rd,ra,simm - generate_compute_flags(ppc, block, desc, TRUE, XER_CA, FALSE); // <update flags> + generate_compute_flags(block, desc, TRUE, XER_CA, FALSE); // <update flags> return TRUE; case 0x10: /* BCx */ - generate_branch_bo(ppc, block, compiler, desc, G_BO(op), G_BI(op), 0, op & M_LK);// <branch conditional> + generate_branch_bo(block, compiler, desc, G_BO(op), G_BI(op), 0, op & M_LK);// <branch conditional> return TRUE; case 0x11: /* SC */ UML_MAPVAR(block, MAPVAR_PC, desc->pc + 4); // mapvar PC,desc->pc+4 - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_SYSCALL], 0); // exh syscall,0 + UML_EXH(block, *m_exception[EXCEPTION_SYSCALL], 0); // exh syscall,0 return TRUE; case 0x12: /* Bx */ - generate_branch(ppc, block, compiler, desc, 0, op & M_LK); // <branch> + generate_branch(block, compiler, desc, 0, op & M_LK); // <branch> return TRUE; case 0x13: /* 0x13 group */ - return generate_instruction_13(ppc, block, compiler, desc); // <group13> + return generate_instruction_13(block, compiler, desc); // <group13> case 0x14: /* RLWIMIx */ UML_ROLINS(block, R32(G_RA(op)), R32(G_RS(op)), G_SH(op), compute_rlw_mask(G_MB(op), G_ME(op))); // rolins ra,rs,sh,mask if (op & M_RC) - generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x15: /* RLWINMx */ UML_ROLAND(block, R32(G_RA(op)), R32(G_RS(op)), G_SH(op), compute_rlw_mask(G_MB(op), G_ME(op))); // roland ra,rs,sh,mask if (op & M_RC) - generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x17: /* RLWNMx */ UML_ROLAND(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op)), compute_rlw_mask(G_MB(op), G_ME(op))); // roland ra,rs,rb,mask if (op & M_RC) - generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x18: /* ORI */ @@ -2536,254 +2055,254 @@ static int generate_opcode(powerpc_state *ppc, drcuml_block *block, compiler_sta case 0x1c: /* ANDI. */ UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op)); // and ra,rs,uimm - generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x1d: /* ANDIS. */ UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op) << 16); // and ra,rs,uimm << 16 - generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x1f: /* 0x1f group */ - return generate_instruction_1f(ppc, block, compiler, desc); // <group1f> + return generate_instruction_1f(block, compiler, desc); // <group1f> case 0x22: /* LBZ */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->read8[ppc->impstate->mode]); // callh read8 + UML_CALLH(block, *m_read8[m_core->mode]); // callh read8 UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x28: /* LHZ */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode]); // callh read16 UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2a: /* LHA */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode]); // callh read16 UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x20: /* LWZ */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 + UML_CALLH(block, *m_read32[m_core->mode]); // callh read32 UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x23: /* LBZU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->read8[ppc->impstate->mode]); // callh read8 + UML_CALLH(block, *m_read8[m_core->mode]); // callh read8 UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x29: /* LHZU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode]); // callh read16 UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2b: /* LHAU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode]); // callh read16 UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x21: /* LWZU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 + UML_CALLH(block, *m_read32[m_core->mode]); // callh read32 UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x26: /* STB */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_AND(block, I1, R32(G_RS(op)), 0xff); // and i1,rs,0xff UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->write8[ppc->impstate->mode]); // callh write8 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write8[m_core->mode]); // callh write8 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2c: /* STH */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_AND(block, I1, R32(G_RS(op)), 0xffff); // and i1,rs,0xffff UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->write16[ppc->impstate->mode]); // callh write16 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write16[m_core->mode]); // callh write16 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x24: /* STW */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32[m_core->mode]); // callh write32 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x27: /* STBU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_AND(block, I1, R32(G_RS(op)), 0xff); // and i1,rs,0xff - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->write8[ppc->impstate->mode]); // callh write8 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write8[m_core->mode]); // callh write8 + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2d: /* STHU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_AND(block, I1, R32(G_RS(op)), 0xffff); // and i1,rs,0xffff - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->write16[ppc->impstate->mode]); // callh write16 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write16[m_core->mode]); // callh write16 + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x25: /* STWU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32[m_core->mode]); // callh write32 + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2e: /* LMW */ UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_MOV(block, mem(&ppc->impstate->tempaddr), R32Z(G_RA(op))); // mov [tempaddr],ra - for (regnum = G_RD(op); regnum < 32; regnum++) + UML_MOV(block, mem(&m_core->tempaddr), R32Z(G_RA(op))); // mov [tempaddr],ra + for (int regnum = G_RD(op); regnum < 32; regnum++) { - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), (INT16)G_SIMM(op) + 4 * (regnum - G_RD(op))); + UML_ADD(block, I0, mem(&m_core->tempaddr), (INT16)G_SIMM(op) + 4 * (regnum - G_RD(op))); // add i0,[tempaddr],simm + 4*(regnum-rd) - UML_CALLH(block, *ppc->impstate->read32align[ppc->impstate->mode]); // callh read32align + UML_CALLH(block, *m_read32align[m_core->mode]); // callh read32align UML_MOV(block, R32(regnum), I0); // mov regnum,i0 } - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2f: /* STMW */ UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_MOV(block, mem(&ppc->impstate->tempaddr), R32Z(G_RA(op))); // mov [tempaddr],ra - for (regnum = G_RS(op); regnum < 32; regnum++) + UML_MOV(block, mem(&m_core->tempaddr), R32Z(G_RA(op))); // mov [tempaddr],ra + for (int regnum = G_RS(op); regnum < 32; regnum++) { - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), (INT16)G_SIMM(op) + 4 * (regnum - G_RS(op))); + UML_ADD(block, I0, mem(&m_core->tempaddr), (INT16)G_SIMM(op) + 4 * (regnum - G_RS(op))); // add i0,[tempaddr],simm + 4*(regnum-rs) UML_MOV(block, I1, R32(regnum)); // mov i1,regnum - UML_CALLH(block, *ppc->impstate->write32align[ppc->impstate->mode]); // callh write32align + UML_CALLH(block, *m_write32align[m_core->mode]); // callh write32align } - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x30: /* LFS */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I0); // mov [tempdata],i0 - UML_FDFRFLT(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_read32[m_core->mode]); // callh read32 + UML_MOV(block, mem(&m_core->tempdata.w.l), I0); // mov [tempdata],i0 + UML_FDFRFLT(block, F64(G_RD(op)), mem(&m_core->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x32: /* LFD */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->read64[ppc->impstate->mode]); // callh read64 - UML_DMOV(block, mem(&ppc->impstate->tempdata.d), I0); // dmov [tempdata],i0 - UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_read64[m_core->mode]); // callh read64 + UML_DMOV(block, mem(&m_core->tempdata.d), I0); // dmov [tempdata],i0 + UML_FDMOV(block, F64(G_RD(op)), mem(&m_core->tempdata.d)); // fdmov fd,[tempdata] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x31: /* LFSU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I0); // mov [tempdata],i0 - UML_FDFRFLT(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_read32[m_core->mode]); // callh read32 + UML_MOV(block, mem(&m_core->tempdata.w.l), I0); // mov [tempdata],i0 + UML_FDFRFLT(block, F64(G_RD(op)), mem(&m_core->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x33: /* LFDU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->read64[ppc->impstate->mode]); // callh read64 - UML_DMOV(block, mem(&ppc->impstate->tempdata.d), I0); // dmov [tempdata],i0 - UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_read64[m_core->mode]); // callh read64 + UML_DMOV(block, mem(&m_core->tempdata.d), I0); // dmov [tempdata],i0 + UML_FDMOV(block, F64(G_RD(op)), mem(&m_core->tempdata.d)); // fdmov fd,[tempdata] + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x34: /* STFS */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm - UML_FSFRFLT(block, mem(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword - UML_MOV(block, I1, mem(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] + UML_FSFRFLT(block, mem(&m_core->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword + UML_MOV(block, I1, mem(&m_core->tempdata.w.l)); // mov i1,[tempdata] UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32[m_core->mode]); // callh write32 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x36: /* STFD */ UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm - UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs - UML_DMOV(block, I1, mem(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] + UML_FDMOV(block, mem(&m_core->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs + UML_DMOV(block, I1, mem(&m_core->tempdata.d)); // dmov i1,[tempdata] UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) - UML_CALLH(block, *ppc->impstate->write64[ppc->impstate->mode]); // callh write64 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write64[m_core->mode]); // callh write64 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x35: /* STFSU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm - UML_FSFRFLT(block, mem(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword - UML_MOV(block, I1, mem(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_FSFRFLT(block, mem(&m_core->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword + UML_MOV(block, I1, mem(&m_core->tempdata.w.l)); // mov i1,[tempdata] + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32[m_core->mode]); // callh write32 + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x37: /* STFDU */ UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm - UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs - UML_DMOV(block, I1, mem(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_FDMOV(block, mem(&m_core->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs + UML_DMOV(block, I1, mem(&m_core->tempdata.d)); // dmov i1,[tempdata] + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_CALLH(block, *ppc->impstate->write64[ppc->impstate->mode]); // callh write64 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write64[m_core->mode]); // callh write64 + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x3b: /* 0x3b group */ - return generate_instruction_3b(ppc, block, compiler, desc); // <group3b> + return generate_instruction_3b(block, compiler, desc); // <group3b> case 0x3f: /* 0x3f group */ - return generate_instruction_3f(ppc, block, compiler, desc); // <group3f> + return generate_instruction_3f(block, compiler, desc); // <group3f> } return FALSE; @@ -2795,7 +2314,7 @@ static int generate_opcode(powerpc_state *ppc, drcuml_block *block, compiler_sta the 0x13 group -------------------------------------------------*/ -static int generate_instruction_13(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { UINT32 op = desc->opptr.l[0]; UINT32 opswitch = (op >> 1) & 0x3ff; @@ -2803,11 +2322,11 @@ static int generate_instruction_13(powerpc_state *ppc, drcuml_block *block, comp switch (opswitch) { case 0x010: /* BCLRx */ - generate_branch_bo(ppc, block, compiler, desc, G_BO(op), G_BI(op), SPR_LR, op & M_LK);// <branch conditional> + generate_branch_bo(block, compiler, desc, G_BO(op), G_BI(op), SPR_LR, op & M_LK);// <branch conditional> return TRUE; case 0x210: /* BCCTRx */ - generate_branch_bo(ppc, block, compiler, desc, G_BO(op), G_BI(op), SPR_CTR, op & M_LK); + generate_branch_bo(block, compiler, desc, G_BO(op), G_BI(op), SPR_CTR, op & M_LK); // <branch conditional> return TRUE; @@ -2885,9 +2404,9 @@ static int generate_instruction_13(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x032: /* RFI */ - if (ppc->cap & PPCCAP_OEA) + if (m_cap & PPCCAP_OEA) { - if (!(ppc->cap & PPCCAP_603_MMU)) + if (!(m_cap & PPCCAP_603_MMU)) UML_ROLINS(block, MSR32, SPR32(SPROEA_SRR1), 0, 0x87c0ffff); // rolins [msr],[srr1],0,0x87c0ffff else { @@ -2896,25 +2415,25 @@ static int generate_instruction_13(powerpc_state *ppc, drcuml_block *block, comp // rolins [msr],[srr1],0,0x87c0ffff | MSR603_TGPR UML_XOR(block, I0, I0, MSR32); // xor i0,i0,[msr] UML_TEST(block, I0, MSR603_TGPR); // test i0,tgpr - UML_CALLHc(block, COND_NZ, *ppc->impstate->swap_tgpr); // callh swap_tgpr,nz + UML_CALLHc(block, COND_NZ, *m_swap_tgpr); // callh swap_tgpr,nz } } - else if (ppc->cap & PPCCAP_4XX) + else if (m_cap & PPCCAP_4XX) UML_MOV(block, MSR32, SPR32(SPR4XX_SRR1)); // mov [msr],[srr1] - generate_update_mode(ppc, block); // <update mode> + generate_update_mode(block); // <update mode> compiler->checkints = TRUE; - generate_update_cycles(ppc, block, compiler, SPR32(SPROEA_SRR0), TRUE); // <subtract cycles> - UML_HASHJMP(block, mem(&ppc->impstate->mode), SPR32(SPROEA_SRR0), *ppc->impstate->nocode); + generate_update_cycles(block, compiler, SPR32(SPROEA_SRR0), TRUE); // <subtract cycles> + UML_HASHJMP(block, mem(&m_core->mode), SPR32(SPROEA_SRR0), *m_nocode); // hashjmp mode,[srr0],nocode return TRUE; case 0x033: /* RFCI */ - assert(ppc->cap & PPCCAP_4XX); + assert(m_cap & PPCCAP_4XX); UML_MOV(block, MSR32, SPR32(SPR4XX_SRR3)); // mov [msr],[srr3] - generate_update_mode(ppc, block); // <update mode> + generate_update_mode(block); // <update mode> compiler->checkints = TRUE; - generate_update_cycles(ppc, block, compiler, SPR32(SPR4XX_SRR2), TRUE); // <subtract cycles> - UML_HASHJMP(block, mem(&ppc->impstate->mode), SPR32(SPR4XX_SRR2), *ppc->impstate->nocode); + generate_update_cycles(block, compiler, SPR32(SPR4XX_SRR2), TRUE); // <subtract cycles> + UML_HASHJMP(block, mem(&m_core->mode), SPR32(SPR4XX_SRR2), *m_nocode); // hashjmp mode,[srr2],nocode return TRUE; @@ -2932,7 +2451,7 @@ static int generate_instruction_13(powerpc_state *ppc, drcuml_block *block, comp the 0x1f group -------------------------------------------------*/ -static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { UINT32 op = desc->opptr.l[0]; UINT32 opswitch = (op >> 1) & 0x3ff; @@ -2971,28 +2490,28 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x004: /* TW */ UML_CMP(block, R32(G_RA(op)), R32(G_RB(op))); // cmp ra,rb if (G_TO(op) & 0x10) - UML_EXHc(block, COND_L, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,l + UML_EXHc(block, COND_L, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,l if (G_TO(op) & 0x08) - UML_EXHc(block, COND_G, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,g + UML_EXHc(block, COND_G, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,g if (G_TO(op) & 0x04) - UML_EXHc(block, COND_E, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,e + UML_EXHc(block, COND_E, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,e if (G_TO(op) & 0x02) - UML_EXHc(block, COND_B, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,b + UML_EXHc(block, COND_B, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,b if (G_TO(op) & 0x01) - UML_EXHc(block, COND_A, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,a + UML_EXHc(block, COND_A, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,a return TRUE; case 0x10a: /* ADDx */ case 0x30a: /* ADDOx */ UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // add rd,ra,rb - generate_compute_flags(ppc, block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE); + generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags> return TRUE; case 0x00a: /* ADDCx */ case 0x20a: /* ADDCOx */ UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // add rd,ra,rb - generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); + generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags> return TRUE; @@ -3000,7 +2519,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x28a: /* ADDEOx */ UML_CARRY(block, SPR32(SPR_XER), 29); // carry [xer],XER_CA UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // addc rd,ra,rb - generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); + generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags> return TRUE; @@ -3008,7 +2527,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x2ca: /* ADDZEOx */ UML_CARRY(block, SPR32(SPR_XER), 29); // carry [xer],XER_CA UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), 0); // addc rd,ra,0 - generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); + generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags> return TRUE; @@ -3016,21 +2535,21 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x2ea: /* ADDMEOx */ UML_CARRY(block, SPR32(SPR_XER), 29); // carry [xer],XER_CA UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), (UINT32)-1); // addc rd,ra,-1 - generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); + generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags> return TRUE; case 0x028: /* SUBFx */ case 0x228: /* SUBFOx */ UML_SUB(block, R32(G_RD(op)), R32(G_RB(op)), R32(G_RA(op))); // sub rd,rb,ra - generate_compute_flags(ppc, block, desc, op & M_RC, (op & M_OE) ? XER_OV : 0, TRUE); + generate_compute_flags(block, desc, op & M_RC, (op & M_OE) ? XER_OV : 0, TRUE); // <update flags> return TRUE; case 0x008: /* SUBFCx */ case 0x208: /* SUBFCOx */ UML_SUB(block, R32(G_RD(op)), R32(G_RB(op)), R32(G_RA(op))); // sub rd,rb,ra - generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); + generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); // <update flags> return TRUE; @@ -3039,7 +2558,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_XOR(block, I0, SPR32(SPR_XER), XER_CA); // xor i0,[xer],XER_CA UML_CARRY(block, I0, 29); // carry i0,XER_CA UML_SUBB(block, R32(G_RD(op)), R32(G_RB(op)), R32(G_RA(op))); // subc rd,rb,ra - generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); + generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); // <update flags> return TRUE; @@ -3048,7 +2567,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_XOR(block, I0, SPR32(SPR_XER), XER_CA); // xor i0,[xer],XER_CA UML_CARRY(block, I0, 29); // carry i0,XER_CA UML_SUBB(block, R32(G_RD(op)), 0, R32(G_RA(op))); // subc rd,0,ra - generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); + generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); // <update flags> return TRUE; @@ -3057,28 +2576,28 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_XOR(block, I0, SPR32(SPR_XER), XER_CA); // xor i0,[xer],XER_CA UML_CARRY(block, I0, 29); // carry i0,XER_CA UML_SUBB(block, R32(G_RD(op)), (UINT32)-1, R32(G_RA(op))); // subc rd,-1,ra - generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); + generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); // <update flags> return TRUE; case 0x068: /* NEGx */ case 0x268: /* NEGOx */ UML_SUB(block, R32(G_RD(op)), 0, R32(G_RA(op))); // sub rd,0,ra - generate_compute_flags(ppc, block, desc, op & M_RC, (op & M_OE) ? XER_OV : 0, TRUE); + generate_compute_flags(block, desc, op & M_RC, (op & M_OE) ? XER_OV : 0, TRUE); // <update flags> return TRUE; case 0x000: /* CMP */ UML_CMP(block, R32(G_RA(op)), R32(G_RB(op))); // cmp ra,rb UML_GETFLGS(block, I0, FLAG_Z | FLAG_V | FLAG_C | FLAG_S); // getflgs i0,zvcs - UML_LOAD(block, I0, ppc->impstate->cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte + UML_LOAD(block, I0, m_cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] return TRUE; case 0x020: /* CMPL */ UML_CMP(block, R32(G_RA(op)), R32(G_RB(op))); // cmp ra,rb UML_GETFLGS(block, I0, FLAG_Z | FLAG_C); // getflgs i0,zc - UML_LOAD(block, I0, ppc->impstate->cmpl_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmpl_cr_table,i0,byte + UML_LOAD(block, I0, m_cmpl_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmpl_cr_table,i0,byte UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] return TRUE; @@ -3087,7 +2606,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp if (op & M_RC) { UML_TEST(block, R32(G_RD(op)), ~0); // test rd,~0 - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> } return TRUE; @@ -3096,14 +2615,14 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp if (op & M_RC) { UML_TEST(block, R32(G_RD(op)), ~0); // test rd,~0 - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> } return TRUE; case 0x0eb: /* MULLWx */ case 0x2eb: /* MULLWOx */ UML_MULS(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // muls rd,rd,ra,rb - generate_compute_flags(ppc, block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags> + generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags> return TRUE; case 0x1cb: /* DIVWUx */ @@ -3128,7 +2647,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_LABEL(block, compiler->labelnum++); // 0: UML_DIVU(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // divu rd,rd,ra,rb - generate_compute_flags(ppc, block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags> + generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags> UML_LABEL(block, compiler->labelnum++); // 1: return TRUE; @@ -3181,54 +2700,54 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_LABEL(block, compiler->labelnum++); // 2: UML_DIVS(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // divs rd,rd,ra,rb - generate_compute_flags(ppc, block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags> + generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags> UML_LABEL(block, compiler->labelnum++); // 3: return TRUE; case 0x01c: /* ANDx */ UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op))); // and ra,rs,rb - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x03c: /* ANDCx */ UML_XOR(block, I0, R32(G_RB(op)), ~0); // xor i0,rb,~0 UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), I0); // and ra,rs,i0 - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x1dc: /* NANDx */ UML_AND(block, I0, R32(G_RS(op)), R32(G_RB(op))); // and i0,rs,rb UML_XOR(block, R32(G_RA(op)), I0, ~0); // xor ra,i0,~0 - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x1bc: /* ORx */ UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op))); // or ra,rs,rb - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x19c: /* ORCx */ UML_XOR(block, I0, R32(G_RB(op)), ~0); // xor i0,rb,~0 UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), I0); // or ra,rs,i0 - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x07c: /* NORx */ UML_OR(block, I0, R32(G_RS(op)), R32(G_RB(op))); // or i0,rs,rb UML_XOR(block, R32(G_RA(op)), I0, ~0); // xor ra,i0,~0 - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x13c: /* XORx */ UML_XOR(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op))); // xor ra,rs,rb - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x11c: /* EQVx */ UML_XOR(block, I0, R32(G_RS(op)), R32(G_RB(op))); // xor i0,rs,rb UML_XOR(block, R32(G_RA(op)), I0, ~0); // xor ra,i0,~0 - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x018: /* SLWx */ @@ -3250,7 +2769,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp // calculate S and Z flags if (op & M_RC) { - generate_shift_flags(ppc, block, desc, op); + generate_shift_flags(block, desc, op); } UML_LABEL(block, compiler->labelnum++); // 1: @@ -3275,7 +2794,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp // calculate S and Z flags if (op & M_RC) { - generate_shift_flags(ppc, block, desc, op); + generate_shift_flags(block, desc, op); } UML_LABEL(block, compiler->labelnum++); // 1: @@ -3313,7 +2832,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp // calculate S and Z flags if (op & M_RC) { - generate_shift_flags(ppc, block, desc, op); + generate_shift_flags(block, desc, op); } return TRUE; @@ -3330,178 +2849,178 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp // calculate S and Z flags if (op & M_RC) { - generate_shift_flags(ppc, block, desc, op); + generate_shift_flags(block, desc, op); } return TRUE; case 0x01a: /* CNTLZWx */ UML_LZCNT(block, R32(G_RA(op)), R32(G_RS(op))); // lzcnt ra,rs if (op & M_RC) - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x3ba: /* EXTSBx */ UML_SEXT(block, R32(G_RA(op)), R32(G_RS(op)), SIZE_BYTE); // sext ra,rs,byte if (op & M_RC) - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x39a: /* EXTSHx */ UML_SEXT(block, R32(G_RA(op)), R32(G_RS(op)), SIZE_WORD); // sext ra,rs,word if (op & M_RC) - generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x057: /* LBZX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read8[ppc->impstate->mode]); // callh read8 + UML_CALLH(block, *m_read8[m_core->mode]); // callh read8 UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x117: /* LHZX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode]); // callh read16 UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x157: /* LHAX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode]); // callh read16 UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x017: /* LWZX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 + UML_CALLH(block, *m_read32[m_core->mode]); // callh read32 UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x217: /* LFSX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I0); // mov [tempdata],i0 - UML_FDFRFLT(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_read32[m_core->mode]); // callh read32 + UML_MOV(block, mem(&m_core->tempdata.w.l), I0); // mov [tempdata],i0 + UML_FDFRFLT(block, F64(G_RD(op)), mem(&m_core->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x257: /* LFDX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read64[ppc->impstate->mode]); // callh read64 - UML_DMOV(block, mem(&ppc->impstate->tempdata.d), I0); // dmov [tempdata],i0 - UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_read64[m_core->mode]); // callh read64 + UML_DMOV(block, mem(&m_core->tempdata.d), I0); // dmov [tempdata],i0 + UML_FDMOV(block, F64(G_RD(op)), mem(&m_core->tempdata.d)); // fdmov fd,[tempdata] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x316: /* LHBRX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode]); // callh read16 UML_BSWAP(block, I0, I0); // bswap i0,i0 UML_SHR(block, R32(G_RD(op)), I0, 16); // shr rd,i0,16 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x216: /* LWBRX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read32align[ppc->impstate->mode]); // callh read32align + UML_CALLH(block, *m_read32align[m_core->mode]); // callh read32align UML_BSWAP(block, R32(G_RD(op)), I0); // bswap rd,i0 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x077: /* LBZUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op) - UML_CALLH(block, *ppc->impstate->read8[ppc->impstate->mode]); // callh read8 + UML_CALLH(block, *m_read8[m_core->mode]); // callh read8 UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x137: /* LHZUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op) - UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode]); // callh read16 UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x177: /* LHAUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op) - UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode]); // callh read16 UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x037: /* LWZUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op) - UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 + UML_CALLH(block, *m_read32[m_core->mode]); // callh read32 UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x237: /* LFSUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I0); // mov [tempdata],i0 - UML_FDFRFLT(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_read32[m_core->mode]); // callh read32 + UML_MOV(block, mem(&m_core->tempdata.w.l), I0); // mov [tempdata],i0 + UML_FDFRFLT(block, F64(G_RD(op)), mem(&m_core->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x277: /* LFDUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read64[ppc->impstate->mode]); // callh read64 - UML_DMOV(block, mem(&ppc->impstate->tempdata.d), I0); // dmov [tempdata],i0 - UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_read64[m_core->mode]); // callh read64 + UML_DMOV(block, mem(&m_core->tempdata.d), I0); // dmov [tempdata],i0 + UML_FDMOV(block, F64(G_RD(op)), mem(&m_core->tempdata.d)); // fdmov fd,[tempdata] + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x014: /* LWARX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->read32align[ppc->impstate->mode]); // callh read32align + UML_CALLH(block, *m_read32align[m_core->mode]); // callh read32align UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x255: /* LSWI */ - UML_MOV(block, mem(&ppc->impstate->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra - UML_MOV(block, mem(&ppc->impstate->swcount), ((G_NB(op) - 1) & 0x1f) + 1); // mov [swcount],G_NB - UML_CALLH(block, *ppc->impstate->lsw[ppc->impstate->mode][G_RD(op)]); // call lsw[rd] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_MOV(block, mem(&m_core->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra + UML_MOV(block, mem(&m_core->swcount), ((G_NB(op) - 1) & 0x1f) + 1); // mov [swcount],G_NB + UML_CALLH(block, *m_lsw[m_core->mode][G_RD(op)]); // call lsw[rd] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x215: /* LSWX */ - UML_ADD(block, mem(&ppc->impstate->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb - UML_AND(block, mem(&ppc->impstate->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f - UML_SUB(block, mem(&ppc->icount), mem(&ppc->icount), mem(&ppc->impstate->swcount));// sub icount,icount,[swcount] - UML_CALLHc(block, COND_NZ, *ppc->impstate->lsw[ppc->impstate->mode][G_RD(op)]); // call lsw[rd],nz - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_ADD(block, mem(&m_core->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb + UML_AND(block, mem(&m_core->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f + UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), mem(&m_core->swcount));// sub icount,icount,[swcount] + UML_CALLHc(block, COND_NZ, *m_lsw[m_core->mode][G_RD(op)]); // call lsw[rd],nz + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x136: /* ECIWX */ @@ -3512,51 +3031,51 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_AND(block, I1, R32(G_RS(op)), 0xff); // and i1,rs,0xff UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write8[ppc->impstate->mode]); // callh write8 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write8[m_core->mode]); // callh write8 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x197: /* STHX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_AND(block, I1, R32(G_RS(op)), 0xffff); // and i1,rs UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write16[ppc->impstate->mode]); // callh write16 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write16[m_core->mode]); // callh write16 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x097: /* STWX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32[m_core->mode]); // callh write32 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x297: /* STFSX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_FSFRFLT(block, mem(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword - UML_MOV(block, I1, mem(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] + UML_FSFRFLT(block, mem(&m_core->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword + UML_MOV(block, I1, mem(&m_core->tempdata.w.l)); // mov i1,[tempdata] UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32[m_core->mode]); // callh write32 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x3d7: /* STFIWX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs - UML_MOV(block, I1, mem(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata.lo] + UML_FDMOV(block, mem(&m_core->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs + UML_MOV(block, I1, mem(&m_core->tempdata.w.l)); // mov i1,[tempdata.lo] UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32[m_core->mode]); // callh write32 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2d7: /* STFDX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs - UML_DMOV(block, I1, mem(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] + UML_FDMOV(block, mem(&m_core->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs + UML_DMOV(block, I1, mem(&m_core->tempdata.d)); // dmov i1,[tempdata] UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write64[ppc->impstate->mode]); // callh write64 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write64[m_core->mode]); // callh write64 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x396: /* STHBRX */ @@ -3564,98 +3083,98 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_BSWAP(block, I1, R32(G_RS(op))); // bswap i1,rs UML_SHR(block, I1, I1, 16); // shr i1,i1,16 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write16[ppc->impstate->mode]); // callh write16 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write16[m_core->mode]); // callh write16 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x296: /* STWBRX */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_BSWAP(block, I1, R32(G_RS(op))); // bswap i1,rs UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32[m_core->mode]); // callh write32 + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x0f7: /* STBUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_AND(block, I1, R32(G_RS(op)), 0xff); // and i1,rs,0xff - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write8[ppc->impstate->mode]); // callh write8 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write8[m_core->mode]); // callh write8 + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x1b7: /* STHUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_AND(block, I1, R32(G_RS(op)), 0xffff); // and i1,rs,0xffff - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write16[ppc->impstate->mode]); // callh write16 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write16[m_core->mode]); // callh write16 + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x0b7: /* STWUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op) - UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32[m_core->mode]); // callh write32 + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2b7: /* STFSUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_FSFRFLT(block, mem(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword - UML_MOV(block, I1, mem(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_FSFRFLT(block, mem(&m_core->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword + UML_MOV(block, I1, mem(&m_core->tempdata.w.l)); // mov i1,[tempdata] + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32[m_core->mode]); // callh write32 + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2f7: /* STFDUX */ UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs - UML_DMOV(block, I1, mem(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] - UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 + UML_FDMOV(block, mem(&m_core->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs + UML_DMOV(block, I1, mem(&m_core->tempdata.d)); // dmov i1,[tempdata] + UML_MOV(block, mem(&m_core->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write64[ppc->impstate->mode]); // callh write64 - UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write64[m_core->mode]); // callh write64 + UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x096: /* STWCX. */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) - UML_CALLH(block, *ppc->impstate->write32align[ppc->impstate->mode]); // callh write32align - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_CALLH(block, *m_write32align[m_core->mode]); // callh write32align + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> UML_CMP(block, I0, I0); // cmp i0,i0 UML_GETFLGS(block, I0, FLAG_Z | FLAG_C | FLAG_S); // getflgs i0,zcs - UML_LOAD(block, I0, ppc->impstate->cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte + UML_LOAD(block, I0, m_cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] - generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> + generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x2d5: /* STSWI */ - UML_MOV(block, mem(&ppc->impstate->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra - UML_MOV(block, mem(&ppc->impstate->swcount), ((G_NB(op) - 1) & 0x1f) + 1); // mov [swcount],G_NB - UML_CALLH(block, *ppc->impstate->stsw[ppc->impstate->mode][G_RD(op)]); // call stsw[rd] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_MOV(block, mem(&m_core->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra + UML_MOV(block, mem(&m_core->swcount), ((G_NB(op) - 1) & 0x1f) + 1); // mov [swcount],G_NB + UML_CALLH(block, *m_stsw[m_core->mode][G_RD(op)]); // call stsw[rd] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x295: /* STSWX */ - UML_ADD(block, mem(&ppc->impstate->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb - UML_AND(block, mem(&ppc->impstate->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f - UML_SUB(block, mem(&ppc->icount), mem(&ppc->icount), mem(&ppc->impstate->swcount));// sub icount,icount,[swcount] - UML_CALLHc(block, COND_NZ, *ppc->impstate->stsw[ppc->impstate->mode][G_RD(op)]); // call stsw[rd] - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + UML_ADD(block, mem(&m_core->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb + UML_AND(block, mem(&m_core->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f + UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), mem(&m_core->swcount));// sub icount,icount,[swcount] + UML_CALLHc(block, COND_NZ, *m_stsw[m_core->mode][G_RD(op)]); // call stsw[rd] + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x1b6: /* ECOWX */ @@ -3664,8 +3183,8 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x036: /* DCBST */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, mem(&ppc->param0), I0); // mov [param0],i0 - UML_CALLC(block, (c_function)ppccom_dcstore_callback, ppc); + UML_MOV(block, mem(&m_core->param0), I0); // mov [param0],i0 + UML_CALLC(block, (c_function)cfunc_ppccom_dcstore_callback, this); return TRUE; case 0x056: /* DCBF */ @@ -3681,37 +3200,37 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x3f6: /* DCBZ */ UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_AND(block, mem(&ppc->impstate->tempaddr), I0, ~(ppc->cache_line_size - 1)); + UML_AND(block, mem(&m_core->tempaddr), I0, ~(m_cache_line_size - 1)); // and [tempaddr],i0,~(cache_line_size - 1) - for (item = 0; item < ppc->cache_line_size / 8; item++) + for (item = 0; item < m_cache_line_size / 8; item++) { - UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 8 * item); // add i0,[tempaddr],8*item + UML_ADD(block, I0, mem(&m_core->tempaddr), 8 * item); // add i0,[tempaddr],8*item UML_DMOV(block, I1, 0); // dmov i1,0 - UML_CALLH(block, *ppc->impstate->write64[ppc->impstate->mode]); // callh write64 + UML_CALLH(block, *m_write64[m_core->mode]); // callh write64 } return TRUE; case 0x132: /* TLBIE */ - UML_MOV(block, mem(&ppc->param0), R32(G_RB(op))); // mov [param0],rb - UML_CALLC(block, (c_function)ppccom_execute_tlbie, ppc); // callc ppccom_execute_tlbie,ppc + UML_MOV(block, mem(&m_core->param0), R32(G_RB(op))); // mov [param0],rb + UML_CALLC(block, (c_function)cfunc_ppccom_execute_tlbie, this); // callc ppccom_execute_tlbie,ppc return TRUE; case 0x172: /* TLBIA */ - UML_CALLC(block, (c_function)ppccom_execute_tlbia, ppc); // callc ppccom_execute_tlbia,ppc + UML_CALLC(block, (c_function)cfunc_ppccom_execute_tlbia, this); // callc ppccom_execute_tlbia,ppc return TRUE; case 0x3d2: /* TLBLD */ - assert(ppc->cap & PPCCAP_603_MMU); - UML_MOV(block, mem(&ppc->param0), R32(G_RB(op))); // mov [param0],rb - UML_MOV(block, mem(&ppc->param1), 0); // mov [param1],0 - UML_CALLC(block, (c_function)ppccom_execute_tlbl, ppc); // callc ppccom_execute_tlbl,ppc + assert(m_cap & PPCCAP_603_MMU); + UML_MOV(block, mem(&m_core->param0), R32(G_RB(op))); // mov [param0],rb + UML_MOV(block, mem(&m_core->param1), 0); // mov [param1],0 + UML_CALLC(block, (c_function)cfunc_ppccom_execute_tlbl, this); // callc ppccom_execute_tlbl,ppc return TRUE; case 0x3f2: /* TLBLI */ - assert(ppc->cap & PPCCAP_603_MMU); - UML_MOV(block, mem(&ppc->param0), R32(G_RB(op))); // mov [param0],rb - UML_MOV(block, mem(&ppc->param1), 1); // mov [param1],1 - UML_CALLC(block, (c_function)ppccom_execute_tlbl, ppc); // callc ppccom_execute_tlbl,ppc + assert(m_cap & PPCCAP_603_MMU); + UML_MOV(block, mem(&m_core->param0), R32(G_RB(op))); // mov [param0],rb + UML_MOV(block, mem(&m_core->param1), 1); // mov [param1],1 + UML_CALLC(block, (c_function)cfunc_ppccom_execute_tlbl, this); // callc ppccom_execute_tlbl,ppc return TRUE; case 0x013: /* MFCR */ @@ -3747,13 +3266,13 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_OR(block, R32(G_RD(op)), SPR32(spr), I0); // or [rd],[xer],i0 } else if (spr == SPROEA_PVR) - UML_MOV(block, R32(G_RD(op)), ppc->flavor); // mov rd,flavor + UML_MOV(block, R32(G_RD(op)), m_flavor); // mov rd,flavor else { - generate_update_cycles(ppc, block, compiler, desc->pc, TRUE); // <update cycles> - UML_MOV(block, mem(&ppc->param0), spr); // mov [param0],spr - UML_CALLC(block, (c_function)ppccom_execute_mfspr, ppc); // callc ppccom_execute_mfspr,ppc - UML_MOV(block, R32(G_RD(op)), mem(&ppc->param1)); // mov rd,[param1] + generate_update_cycles(block, compiler, desc->pc, TRUE); // <update cycles> + UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr + UML_CALLC(block, (c_function)cfunc_ppccom_execute_mfspr, this); // callc ppccom_execute_mfspr,ppc + UML_MOV(block, R32(G_RD(op)), mem(&m_core->param1)); // mov rd,[param1] } return TRUE; } @@ -3764,7 +3283,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x293: /* MFSRIN */ UML_SHR(block, I0, R32(G_RB(op)), 28); // shr i0,G_RB,28 - UML_LOAD(block, R32(G_RD(op)), &ppc->sr[0], I0, SIZE_DWORD, SCALE_x4); // load rd,sr,i0,dword + UML_LOAD(block, R32(G_RD(op)), &m_core->sr[0], I0, SIZE_DWORD, SCALE_x4); // load rd,sr,i0,dword return TRUE; case 0x173: /* MFTB */ @@ -3772,10 +3291,10 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UINT32 tbr = compute_spr(G_SPR(op)); if (tbr != SPRVEA_TBL_R && tbr != SPRVEA_TBU_R) return FALSE; - generate_update_cycles(ppc, block, compiler, desc->pc, TRUE); // <update cycles> - UML_MOV(block, mem(&ppc->param0), tbr); // mov [param0],tbr - UML_CALLC(block, (c_function)ppccom_execute_mftb, ppc); // callc ppccom_execute_mftb,ppc - UML_MOV(block, R32(G_RD(op)), mem(&ppc->param1)); // mov rd,[param1] + generate_update_cycles(block, compiler, desc->pc, TRUE); // <update cycles> + UML_MOV(block, mem(&m_core->param0), tbr); // mov [param0],tbr + UML_CALLC(block, (c_function)cfunc_ppccom_execute_mftb, this); // callc ppccom_execute_mftb,ppc + UML_MOV(block, R32(G_RD(op)), mem(&m_core->param1)); // mov rd,[param1] return TRUE; } @@ -3792,15 +3311,15 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x092: /* MTMSR */ - if (ppc->cap & PPCCAP_603_MMU) + if (m_cap & PPCCAP_603_MMU) UML_XOR(block, I0, MSR32, R32(G_RS(op))); // xor i0,msr32,rs UML_MOV(block, MSR32, R32(G_RS(op))); // mov msr,rs - if (ppc->cap & PPCCAP_603_MMU) + if (m_cap & PPCCAP_603_MMU) { UML_TEST(block, I0, MSR603_TGPR); // test i0,tgpr - UML_CALLHc(block, COND_NZ, *ppc->impstate->swap_tgpr); // callh swap_tgpr,nz + UML_CALLHc(block, COND_NZ, *m_swap_tgpr); // callh swap_tgpr,nz } - generate_update_mode(ppc, block); // <update mode> + generate_update_mode(block); // <update mode> return TRUE; case 0x1d3: /* MTSPR */ @@ -3817,25 +3336,25 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp ; // read only else { - generate_update_cycles(ppc, block, compiler, desc->pc, TRUE); // <update cycles> - UML_MOV(block, mem(&ppc->param0), spr); // mov [param0],spr - UML_MOV(block, mem(&ppc->param1), R32(G_RS(op))); // mov [param1],rs - UML_CALLC(block, (c_function)ppccom_execute_mtspr, ppc); // callc ppccom_execute_mtspr,ppc + generate_update_cycles(block, compiler, desc->pc, TRUE); // <update cycles> + UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr + UML_MOV(block, mem(&m_core->param1), R32(G_RS(op))); // mov [param1],rs + UML_CALLC(block, (c_function)cfunc_ppccom_execute_mtspr, this); // callc ppccom_execute_mtspr,ppc compiler->checkints = TRUE; - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> } return TRUE; } case 0x0d2: /* MTSR */ UML_MOV(block, SR32(G_SR(op)), R32(G_RS(op))); // mov sr[G_SR],rs - UML_CALLC(block, (c_function)ppccom_tlb_flush, ppc); // callc ppccom_tlb_flush,ppc + UML_CALLC(block, (c_function)cfunc_ppccom_tlb_flush, this); // callc ppccom_tlb_flush,ppc return TRUE; case 0x0f2: /* MTSRIN */ UML_SHR(block, I0, R32(G_RB(op)), 28); // shr i0,G_RB,28 - UML_STORE(block, &ppc->sr[0], I0, R32(G_RS(op)), SIZE_DWORD, SCALE_x4); // store sr,i0,rs,dword - UML_CALLC(block, (c_function)ppccom_tlb_flush, ppc); // callc ppccom_tlb_flush,ppc + UML_STORE(block, &m_core->sr[0], I0, R32(G_RS(op)), SIZE_DWORD, SCALE_x4); // store sr,i0,rs,dword + UML_CALLC(block, (c_function)cfunc_ppccom_tlb_flush, this); // callc ppccom_tlb_flush,ppc return TRUE; case 0x200: /* MCRXR */ @@ -3849,54 +3368,54 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x106: /* ICBT */ case 0x1c6: /* DCCCI */ case 0x3c6: /* ICCCI */ - assert(ppc->cap & PPCCAP_4XX); + assert(m_cap & PPCCAP_4XX); /* effective no-nop */ return TRUE; case 0x1e6: /* DCREAD */ case 0x3e6: /* ICREAD */ - assert(ppc->cap & PPCCAP_4XX); + assert(m_cap & PPCCAP_4XX); UML_MOV(block, R32(G_RT(op)), 0); // mov rt,0 return TRUE; case 0x143: /* MFDCR */ { UINT32 spr = compute_spr(G_SPR(op)); - assert(ppc->cap & PPCCAP_4XX); - generate_update_cycles(ppc, block, compiler, desc->pc, TRUE); // <update cycles> - UML_MOV(block, mem(&ppc->param0), spr); // mov [param0],spr - UML_CALLC(block, (c_function)ppccom_execute_mfdcr, ppc); // callc ppccom_execute_mfdcr,ppc - UML_MOV(block, R32(G_RD(op)), mem(&ppc->param1)); // mov rd,[param1] + assert(m_cap & PPCCAP_4XX); + generate_update_cycles(block, compiler, desc->pc, TRUE); // <update cycles> + UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr + UML_CALLC(block, (c_function)cfunc_ppccom_execute_mfdcr, this); // callc ppccom_execute_mfdcr,ppc + UML_MOV(block, R32(G_RD(op)), mem(&m_core->param1)); // mov rd,[param1] return TRUE; } case 0x1c3: /* MTDCR */ { UINT32 spr = compute_spr(G_SPR(op)); - assert(ppc->cap & PPCCAP_4XX); - generate_update_cycles(ppc, block, compiler, desc->pc, TRUE); // <update cycles> - UML_MOV(block, mem(&ppc->param0), spr); // mov [param0],spr - UML_MOV(block, mem(&ppc->param1), R32(G_RS(op))); // mov [param1],rs - UML_CALLC(block, (c_function)ppccom_execute_mtdcr, ppc); // callc ppccom_execute_mtdcr,ppc + assert(m_cap & PPCCAP_4XX); + generate_update_cycles(block, compiler, desc->pc, TRUE); // <update cycles> + UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr + UML_MOV(block, mem(&m_core->param1), R32(G_RS(op))); // mov [param1],rs + UML_CALLC(block, (c_function)cfunc_ppccom_execute_mtdcr, this); // callc ppccom_execute_mtdcr,ppc compiler->checkints = TRUE; - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; } case 0x083: /* WRTEE */ - assert(ppc->cap & PPCCAP_4XX); + assert(m_cap & PPCCAP_4XX); UML_ROLINS(block, MSR32, R32(G_RS(op)), 0, MSR_EE); // rolins msr,rs,0,MSR_EE compiler->checkints = TRUE; - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x0a3: /* WRTEEI */ - assert(ppc->cap & PPCCAP_4XX); + assert(m_cap & PPCCAP_4XX); if (op & MSR_EE) { UML_OR(block, MSR32, MSR32, MSR_EE); // or msr,msr,MSR_EE compiler->checkints = TRUE; - generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles> } else UML_AND(block, MSR32, MSR32, ~MSR_EE); // and msr,msr,~MSR_EE @@ -3917,7 +3436,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp the 0x3b group -------------------------------------------------*/ -static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { UINT32 op = desc->opptr.l[0]; UINT32 opswitch = (op >> 1) & 0x1f; @@ -3925,87 +3444,87 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp switch (opswitch) { case 0x15: /* FADDSx */ - if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) - return generate_instruction_3f(ppc, block, compiler, desc); + if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDADD(block, F0, F64(G_RA(op)), F64(G_RB(op))); // fdadd f0,ra,rb UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x14: /* FSUBSx */ - if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) - return generate_instruction_3f(ppc, block, compiler, desc); + if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDSUB(block, F0, F64(G_RA(op)), F64(G_RB(op))); // fdsub f0,ra,rb UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x19: /* FMULSx */ - if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) - return generate_instruction_3f(ppc, block, compiler, desc); + if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x12: /* FDIVSx */ - if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) - return generate_instruction_3f(ppc, block, compiler, desc); + if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDDIV(block, F0, F64(G_RA(op)), F64(G_RB(op))); // fddiv f0,ra,rb UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x16: /* FSQRTSx */ - if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) - return generate_instruction_3f(ppc, block, compiler, desc); + if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDSQRT(block, F0, F64(G_RB(op))); // fdsqrt f0,rb UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x18: /* FRESx */ UML_FSFRFLT(block, F0, F64(G_RB(op)), SIZE_QWORD); // fsfrlt f0,rb,qword UML_FSRECIP(block, F0, F0); // fsrecip f0,f0 UML_FDFRFLT(block, F64(G_RD(op)), F0, SIZE_DWORD); // fdfrflt rd,f0,dword - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x1d: /* FMADDSx */ - if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) - return generate_instruction_3f(ppc, block, compiler, desc); + if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDADD(block, F0, F0, F64(G_RB(op))); // fdadd f0,f0,rb UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x1c: /* FMSUBSx */ - if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) - return generate_instruction_3f(ppc, block, compiler, desc); + if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDSUB(block, F0, F0, F64(G_RB(op))); // fdsub f0,f0,rb UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x1f: /* FNMADDSx */ - if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) - return generate_instruction_3f(ppc, block, compiler, desc); + if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDADD(block, F0, F0, F64(G_RB(op))); // fdadd f0,f0,rb UML_FDNEG(block, F0, F0); // fdneg f0,f0 UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x1e: /* FNMSUBSx */ - if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) - return generate_instruction_3f(ppc, block, compiler, desc); + if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES)) + return generate_instruction_3f(block, compiler, desc); UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDSUB(block, F0, F64(G_RB(op)), F0); // fdsub f0,rb,f0 UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; } @@ -4019,7 +3538,7 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp the 0x3f group -------------------------------------------------*/ -static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int ppc_device::generate_instruction_3f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { UINT32 op = desc->opptr.l[0]; UINT32 opswitch = (op >> 1) & 0x3ff; @@ -4031,36 +3550,36 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp { case 0x15: /* FADDx */ UML_FDADD(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fdadd rd,ra,rb - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x14: /* FSUBx */ UML_FDSUB(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fdsub rd,ra,rb - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x19: /* FMULx */ UML_FDMUL(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_REGC(op))); // fdmul rd,ra,rc - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x12: /* FDIVx */ UML_FDDIV(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fddiv rd,ra,rb - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x16: /* FSQRTx */ UML_FDSQRT(block, F64(G_RD(op)), F64(G_RB(op))); // fdsqrt rd,rb - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x1a: /* FRSQRTEx */ UML_FDRSQRT(block, F64(G_RD(op)), F64(G_RB(op))); // fdrsqrt rd,rb - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x17: /* FSELx */ - UML_FDCMP(block, F64(G_RA(op)), mem(&ppc->impstate->fp0)); // fdcmp f0,ra,[fp0] + UML_FDCMP(block, F64(G_RA(op)), mem(&m_core->fp0)); // fdcmp f0,ra,[fp0] UML_FDMOVc(block, COND_AE, F64(G_RD(op)), F64(G_REGC(op))); // fdmov rd,rc,AE UML_FDMOVc(block, COND_B, F64(G_RD(op)), F64(G_RB(op))); // fdmov rd,rb,B return TRUE; @@ -4068,26 +3587,26 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp case 0x1d: /* FMADDx */ UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDADD(block, F64(G_RD(op)), F0, F64(G_RB(op))); // fdadd rd,f0,rb - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x1f: /* FNMADDx */ UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDADD(block, F0, F0, F64(G_RB(op))); // fdadd f0,f0,rb UML_FDNEG(block, F64(G_RD(op)), F0); // fdneg rd,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x1c: /* FMSUBx */ UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDSUB(block, F64(G_RD(op)), F0, F64(G_RB(op))); // fdsub rd,f0,rb - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x1e: /* FNMSUBx */ UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDSUB(block, F64(G_RD(op)), F64(G_RB(op)), F0); // fdsub rd,rb,f0 - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; } } @@ -4104,25 +3623,25 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp case 0x020: /* FCMPO */ UML_FDCMP(block, F64(G_RA(op)), F64(G_RB(op))); // fdcmp ra,rb UML_GETFLGS(block, I0, FLAG_C | FLAG_Z | FLAG_U); // getflgs i0,czu - UML_LOAD(block, I0, ppc->impstate->fcmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,fcmp_cr_table,i0,byte + UML_LOAD(block, I0, m_fcmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,fcmp_cr_table,i0,byte UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] return TRUE; case 0x00c: /* FRSPx */ UML_FDRNDS(block, F64(G_RD(op)), F64(G_RB(op))); // fdrnds rd,rb - generate_fp_flags(ppc, block, desc, TRUE); + generate_fp_flags(block, desc, TRUE); return TRUE; case 0x00e: /* FCTIWx */ UML_FDTOINT(block, I0, F64(G_RB(op)), SIZE_DWORD, ROUND_DEFAULT); // fdtoint i0,rb,dword,default - UML_DAND(block, mem(&ppc->impstate->tempdata.w.l), I0, 0xffffffff);// dand i0,i0,0xffffffff - UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l)); // fdmovr rd,i0 + UML_DAND(block, mem(&m_core->tempdata.w.l), I0, 0xffffffff);// dand i0,i0,0xffffffff + UML_FDMOV(block, F64(G_RD(op)), mem(&m_core->tempdata.w.l)); // fdmovr rd,i0 return TRUE; case 0x00f: /* FCTIWZx */ UML_FDTOINT(block, I0, F64(G_RB(op)), SIZE_DWORD, ROUND_TRUNC); // fdtoint i0,rb,dword,default - UML_DAND(block, mem(&ppc->impstate->tempdata.w.l), I0, 0xffffffff);// dand i0,i0,0xffffffff - UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l)); // fdmovr rd,i0 + UML_DAND(block, mem(&m_core->tempdata.w.l), I0, 0xffffffff);// dand i0,i0,0xffffffff + UML_FDMOV(block, F64(G_RD(op)), mem(&m_core->tempdata.w.l)); // fdmovr rd,i0 return TRUE; case 0x028: /* FNEGx */ @@ -4157,13 +3676,13 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x247: /* MFFSx */ - UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), FPSCR32); // mov [tempdata],fpscr - UML_FSMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.d)); // fsmov rd,fpscr + UML_MOV(block, mem(&m_core->tempdata.w.l), FPSCR32); // mov [tempdata],fpscr + UML_FSMOV(block, F64(G_RD(op)), mem(&m_core->tempdata.d)); // fsmov rd,fpscr return TRUE; case 0x2c7: /* MTFSFx */ - UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RB(op))); // fdmov [tempdata],fb - UML_ROLINS(block, FPSCR32, mem(&ppc->impstate->tempdata.w.l), 0, compute_crf_mask(G_FM(op))); + UML_FDMOV(block, mem(&m_core->tempdata.d), F64(G_RB(op))); // fdmov [tempdata],fb + UML_ROLINS(block, FPSCR32, mem(&m_core->tempdata.w.l), 0, compute_crf_mask(G_FM(op))); // rolins fpscr,rb,0,crf_mask return TRUE; @@ -4188,7 +3707,7 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp including disassembly of a PowerPC instruction -------------------------------------------------*/ -static void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op) +void ppc_device::log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op) { char buffer[100]; if (LOG_UML) @@ -4205,7 +3724,7 @@ static void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op) flags -------------------------------------------------*/ -static const char *log_desc_flags_to_string(UINT32 flags) +const char *ppc_device::log_desc_flags_to_string(UINT32 flags) { static char tempbuf[30]; char *dest = tempbuf; @@ -4259,7 +3778,7 @@ static const char *log_desc_flags_to_string(UINT32 flags) log_register_list - log a list of GPR registers -------------------------------------------------*/ -static void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist) +void ppc_device::log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist) { static const char *const crtext[4] = { "lt", "gt", "eq", "so" }; int count = 0; @@ -4362,7 +3881,7 @@ static void log_register_list(drcuml_state *drcuml, const char *string, const UI log_opcode_desc - log a list of descriptions -------------------------------------------------*/ -static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent) +void ppc_device::log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent) { /* open the file, creating it if necessary */ if (indent == 0) @@ -4401,431 +3920,3 @@ static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, i } } - - -/*************************************************************************** - PPC 4XX VARIANTS -***************************************************************************/ - -/*------------------------------------------------- - ppcdrc4xx_get_info - PowerPC 4XX-specific - information getter --------------------------------------------------*/ - -static CPU_GET_INFO( ppcdrc4xx ) -{ - powerpc_state *ppc = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - CPU_GET_INFO_CALL(ppcdrc); - ppc4xx_get_info(ppc, state, info); -} - - -/*------------------------------------------------- - ppcdrc4xx_set_info - PowerPC 4XX-specific - information setter --------------------------------------------------*/ - -static CPU_SET_INFO( ppcdrc4xx ) -{ - powerpc_state *ppc = get_safe_token(device); - CPU_SET_INFO_CALL(ppcdrc); - ppc4xx_set_info(ppc, state, info); -} - - -/*------------------------------------------------- - ppc403ga_init - PowerPC 403GA-specific - initialization --------------------------------------------------*/ - -static CPU_INIT( ppc403ga ) -{ - ppcdrc_init(PPC_MODEL_403GA, PPCCAP_4XX, 1, device, irqcallback); -} - - -/*------------------------------------------------- - ppc403ga_get_info - PowerPC 403GA-specific - information getter --------------------------------------------------*/ - -CPU_GET_INFO( ppc403ga ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc403ga); break; - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(ppcdrc4xx); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 403GA"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "ppc403ga"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(ppcdrc4xx); break; - } -} - - -/*------------------------------------------------- - ppc403gcx_init - PowerPC 403GCX-specific - initialization --------------------------------------------------*/ - -static CPU_INIT( ppc403gcx ) -{ - ppcdrc_init(PPC_MODEL_403GCX, PPCCAP_4XX, 1, device, irqcallback); -} - - -/*------------------------------------------------- - ppc403gcx_get_info - PowerPC 403GCX-specific - information getter --------------------------------------------------*/ - -CPU_GET_INFO( ppc403gcx ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc403gcx); break; - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(ppcdrc4xx); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 403GCX"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "ppc403gcx"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(ppcdrc4xx); break; - } -} - - - -/*------------------------------------------------- - ppc405gp_init - PowerPC 405GP-specific - initialization --------------------------------------------------*/ - -static CPU_INIT( ppc405gp ) -{ - ppcdrc_init(PPC_MODEL_405GP, PPCCAP_4XX | PPCCAP_VEA, 1, device, irqcallback); -} - - -/*------------------------------------------------- - ppc405gp_get_info - PowerPC 405GP-specific - information getter --------------------------------------------------*/ - -CPU_GET_INFO( ppc405gp ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc405gp); break; - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(ppcdrc4xx); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 405GP"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "ppc405gp"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(ppcdrc4xx); break; - } -} - - -/*************************************************************************** - PPC 6XX VARIANTS -***************************************************************************/ - -/*------------------------------------------------- - ppc601_init - PowerPC 601-specific - initialization --------------------------------------------------*/ - -static CPU_INIT( ppc601 ) -{ - ppcdrc_init(PPC_MODEL_601, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_MFIOC | PPCCAP_601BAT, 0/* no TB */, device, irqcallback); -} - - -/*------------------------------------------------- - ppc601_get_info - PowerPC 601-specific - information getter --------------------------------------------------*/ - -CPU_GET_INFO( ppc601 ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc601); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 601"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "ppc601"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(ppcdrc); break; - } -} - - -/*------------------------------------------------- - ppc602_init - PowerPC 602-specific - initialization --------------------------------------------------*/ - -static CPU_INIT( ppc602 ) -{ - ppcdrc_init(PPC_MODEL_602, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, irqcallback); -} - - -/*------------------------------------------------- - ppc602_get_info - PowerPC 602-specific - information getter --------------------------------------------------*/ - -CPU_GET_INFO( ppc602 ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc602); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 602"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "ppc602"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(ppcdrc); break; - } -} - - -/*------------------------------------------------- - ppc603_init - PowerPC 603-specific - initialization --------------------------------------------------*/ - -static CPU_INIT( ppc603 ) -{ - ppcdrc_init(PPC_MODEL_603, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, irqcallback); -} - - -/*------------------------------------------------- - ppc603_get_info - PowerPC 603-specific - information getter --------------------------------------------------*/ - -CPU_GET_INFO( ppc603 ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc603); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 603"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "ppc603"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(ppcdrc); break; - } -} - - -/*------------------------------------------------- - ppc603e_init - PowerPC 603e-specific - initialization --------------------------------------------------*/ - -static CPU_INIT( ppc603e ) -{ - ppcdrc_init(PPC_MODEL_603E, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, irqcallback); -} - - -/*------------------------------------------------- - ppc603e_get_info - PowerPC 603e-specific - information getter --------------------------------------------------*/ - -CPU_GET_INFO( ppc603e ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc603e); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 603e"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "ppc603e"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(ppcdrc); break; - } -} - - -/*------------------------------------------------- - ppc603r_init - PowerPC 603r-specific - initialization --------------------------------------------------*/ - -static CPU_INIT( ppc603r ) -{ - ppcdrc_init(PPC_MODEL_603R, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, irqcallback); -} - - -/*------------------------------------------------- - ppc603r_get_info - PowerPC 603r-specific - information getter --------------------------------------------------*/ - -CPU_GET_INFO( ppc603r ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc603r); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 603R"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "ppc603r"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(ppcdrc); break; - } -} - - -/*------------------------------------------------- - ppc604_init - PowerPC 604-specific - initialization --------------------------------------------------*/ - -static CPU_INIT( ppc604 ) -{ - ppcdrc_init(PPC_MODEL_604, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_604_MMU, 4, device, irqcallback); -} - - -/*------------------------------------------------- - ppc604_get_info - PowerPC 604-specific - information getter --------------------------------------------------*/ - -CPU_GET_INFO( ppc604 ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(ppc604); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC 604"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "ppc604"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(ppcdrc); break; - } -} - - - -/*************************************************************************** - MPC VARIANTS -***************************************************************************/ - -/*------------------------------------------------- - mpc8240_init - PowerPC MPC8240-specific - initialization --------------------------------------------------*/ - -static CPU_INIT( mpc8240 ) -{ - ppcdrc_init(PPC_MODEL_MPC8240, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4/* unknown */, device, irqcallback); -} - - -/*------------------------------------------------- - mpc8240_get_info - PowerPC MPC8240-specific - information getter --------------------------------------------------*/ - -CPU_GET_INFO( mpc8240 ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(mpc8240); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "PowerPC MPC8240"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "mpc8240"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(ppcdrc); break; - } -} - - -ppc403ga_device::ppc403ga_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock) - : ppc4xx_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(ppc403ga)) -{ -} - -const device_type PPC403GA = &legacy_device_creator<ppc403ga_device>; - -ppc403gcx_device::ppc403gcx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock) - : ppc4xx_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(ppc403gcx)) -{ -} - -const device_type PPC403GCX = &legacy_device_creator<ppc403gcx_device>; - -ppc405gp_device::ppc405gp_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock) - : ppc4xx_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(ppc405gp)) -{ -} - -const device_type PPC405GP = &legacy_device_creator<ppc405gp_device>; - -ppc4xx_device::ppc4xx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info) - : legacy_cpu_device(mconfig, type, tag, owner, clock, info) -{ -} - -DEFINE_LEGACY_CPU_DEVICE(PPC601, ppc601); -DEFINE_LEGACY_CPU_DEVICE(PPC602, ppc602); -DEFINE_LEGACY_CPU_DEVICE(PPC603, ppc603); -DEFINE_LEGACY_CPU_DEVICE(PPC603E, ppc603e); -DEFINE_LEGACY_CPU_DEVICE(PPC603R, ppc603r); -DEFINE_LEGACY_CPU_DEVICE(PPC604, ppc604); -DEFINE_LEGACY_CPU_DEVICE(MPC8240, mpc8240); diff --git a/src/emu/cpu/powerpc/ppcfe.c b/src/emu/cpu/powerpc/ppcfe.c index d2c7a0bfce9..94037f7e137 100644 --- a/src/emu/cpu/powerpc/ppcfe.c +++ b/src/emu/cpu/powerpc/ppcfe.c @@ -56,9 +56,9 @@ // ppc_frontend - constructor //------------------------------------------------- -ppc_frontend::ppc_frontend(powerpc_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence) - : drc_frontend(*state.device, window_start, window_end, max_sequence), - m_context(state) +ppc_frontend::ppc_frontend(ppc_device *ppc, UINT32 window_start, UINT32 window_end, UINT32 max_sequence) + : drc_frontend(*ppc, window_start, window_end, max_sequence), + m_ppc(ppc) { } @@ -74,7 +74,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) int regnum; // compute the physical PC - if (!ppccom_translate_address(&m_context, AS_PROGRAM, TRANSLATE_FETCH, &desc.physpc)) + if (!m_ppc->memory_translate(AS_PROGRAM, TRANSLATE_FETCH, desc.physpc)) { // uh-oh: a page fault; leave the description empty and just if this is the first instruction, leave it empty and // mark as needing to validate; otherwise, just end the sequence here @@ -83,7 +83,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) } // fetch the opcode - op = desc.opptr.l[0] = m_context.direct->read_decrypted_dword(desc.physpc, m_context.codexor); + op = desc.opptr.l[0] = m_ppc->m_direct->read_decrypted_dword(desc.physpc, m_ppc->m_codexor); // all instructions are 4 bytes and default to a single cycle each desc.length = 4; @@ -172,7 +172,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) return true; case 0x11: // SC - if (!(m_context.cap & (PPCCAP_OEA | PPCCAP_4XX))) + if (!(m_ppc->m_cap & (PPCCAP_OEA | PPCCAP_4XX))) return false; desc.flags |= OPFLAG_WILL_CAUSE_EXCEPTION; if (is_601_class()) @@ -305,7 +305,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) case 0x30: // LFS case 0x32: // LFD - if (!(m_context.cap & PPCCAP_FPU)) + if (!(m_ppc->m_cap & PPCCAP_FPU)) return false; GPR_USED_OR_ZERO(desc, G_RA(op)); FPR_MODIFIED(desc, G_RD(op)); @@ -314,7 +314,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) case 0x31: // LFSU case 0x33: // LFDU - if (!(m_context.cap & PPCCAP_FPU)) + if (!(m_ppc->m_cap & PPCCAP_FPU)) return false; if (G_RA(op) == 0) return false; @@ -326,7 +326,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) case 0x34: // STFS case 0x36: // STFD - if (!(m_context.cap & PPCCAP_FPU)) + if (!(m_ppc->m_cap & PPCCAP_FPU)) return false; GPR_USED_OR_ZERO(desc, G_RA(op)); FPR_USED(desc, G_RS(op)); @@ -335,7 +335,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) case 0x35: // STFSU case 0x37: // STFDU - if (!(m_context.cap & PPCCAP_FPU)) + if (!(m_ppc->m_cap & PPCCAP_FPU)) return false; if (G_RA(op) == 0) return false; @@ -411,7 +411,7 @@ bool ppc_frontend::describe_13(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x032: // RFI - if (!(m_context.cap & (PPCCAP_OEA | PPCCAP_4XX))) + if (!(m_ppc->m_cap & (PPCCAP_OEA | PPCCAP_4XX))) return false; desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CHANGE_MODES | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE | OPFLAG_CAN_CAUSE_EXCEPTION; desc.targetpc = BRANCH_TARGET_DYNAMIC; @@ -424,14 +424,14 @@ bool ppc_frontend::describe_13(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x033: // RFCI - if (!(m_context.cap & PPCCAP_4XX)) + if (!(m_ppc->m_cap & PPCCAP_4XX)) return false; desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CHANGE_MODES | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE | OPFLAG_CAN_CAUSE_EXCEPTION; desc.targetpc = BRANCH_TARGET_DYNAMIC; return true; case 0x096: // ISYNC - if (!(m_context.cap & (PPCCAP_VEA | PPCCAP_4XX))) + if (!(m_ppc->m_cap & (PPCCAP_VEA | PPCCAP_4XX))) return false; if (is_601_class()) desc.cycles = 6; // 601 @@ -709,7 +709,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x136: // ECIWX - if (!(m_context.cap & PPCCAP_VEA)) + if (!(m_ppc->m_cap & PPCCAP_VEA)) return false; case 0x014: // LWARX case 0x017: // LWZX @@ -774,14 +774,14 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * case 0x116: // DCBT case 0x2f6: // DCBA case 0x3d6: // ICBI - if (!(m_context.cap & (PPCCAP_VEA | PPCCAP_4XX))) + if (!(m_ppc->m_cap & (PPCCAP_VEA | PPCCAP_4XX))) return false; GPR_USED_OR_ZERO(desc, G_RA(op)); GPR_USED(desc, G_RB(op)); return true; case 0x1d6: // DCBI - if (!(m_context.cap & (PPCCAP_OEA | PPCCAP_4XX))) + if (!(m_ppc->m_cap & (PPCCAP_OEA | PPCCAP_4XX))) return false; GPR_USED_OR_ZERO(desc, G_RA(op)); GPR_USED(desc, G_RB(op)); @@ -817,11 +817,11 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * } if (spr & 0x010) desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION; - if ((m_context.cap & PPCCAP_4XX) && spr == SPR4XX_TBLU) + if ((m_ppc->m_cap & PPCCAP_4XX) && spr == SPR4XX_TBLU) desc.cycles = POWERPC_COUNT_READ_TBL; - else if ((m_context.cap & PPCCAP_VEA) && spr == SPRVEA_TBL_R) + else if ((m_ppc->m_cap & PPCCAP_VEA) && spr == SPRVEA_TBL_R) desc.cycles = POWERPC_COUNT_READ_TBL; - else if ((m_context.cap & PPCCAP_OEA) && spr == SPROEA_DEC) + else if ((m_ppc->m_cap & PPCCAP_OEA) && spr == SPROEA_DEC) desc.cycles = POWERPC_COUNT_READ_DEC; return true; @@ -844,7 +844,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x173: // MFTB - if (!(m_context.cap & PPCCAP_VEA)) + if (!(m_ppc->m_cap & PPCCAP_VEA)) return false; GPR_MODIFIED(desc, G_RD(op)); spr = compute_spr(G_SPR(op)); @@ -893,7 +893,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x0d2: // MTSR - if (!(m_context.cap & PPCCAP_OEA)) + if (!(m_ppc->m_cap & PPCCAP_OEA)) return false; GPR_USED(desc, G_RS(op)); desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION; @@ -918,7 +918,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x1b6: // ECOWX - if (!(m_context.cap & PPCCAP_VEA)) + if (!(m_ppc->m_cap & PPCCAP_VEA)) return false; case 0x096: // STWCX. case 0x097: // STWX @@ -945,7 +945,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x0f2: // MTSRIN - if (!(m_context.cap & PPCCAP_OEA)) + if (!(m_ppc->m_cap & PPCCAP_OEA)) return false; GPR_USED(desc, G_RS(op)); GPR_USED(desc, G_RB(op)); @@ -953,21 +953,21 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x132: // TLBIE - if (!(m_context.cap & PPCCAP_OEA)) + if (!(m_ppc->m_cap & PPCCAP_OEA)) return false; GPR_USED(desc, G_RB(op)); desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION; return true; case 0x172: // TLBIA - if (!(m_context.cap & PPCCAP_OEA) || (m_context.cap & PPCCAP_603_MMU)) + if (!(m_ppc->m_cap & PPCCAP_OEA) || (m_ppc->m_cap & PPCCAP_603_MMU)) return false; desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION; return true; case 0x3d2: // TLBLD case 0x3f2: // TLBLI - if (!(m_context.cap & PPCCAP_603_MMU) && !is_602_class()) + if (!(m_ppc->m_cap & PPCCAP_603_MMU) && !is_602_class()) return false; desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION; return true; @@ -993,7 +993,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * case 0x217: // LFSX case 0x257: // LFDX - if (!(m_context.cap & PPCCAP_FPU)) + if (!(m_ppc->m_cap & PPCCAP_FPU)) return false; GPR_USED_OR_ZERO(desc, G_RA(op)); GPR_USED(desc, G_RB(op)); @@ -1002,7 +1002,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x236: // TLBSYNC - if (!(m_context.cap & PPCCAP_OEA)) + if (!(m_ppc->m_cap & PPCCAP_OEA)) return false; desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION; return true; @@ -1011,13 +1011,13 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x356: // EIEIO - if (!(m_context.cap & (PPCCAP_VEA | PPCCAP_4XX))) + if (!(m_ppc->m_cap & (PPCCAP_VEA | PPCCAP_4XX))) return false; return true; case 0x237: // LFSUX case 0x277: // LFDUX - if (!(m_context.cap & PPCCAP_FPU)) + if (!(m_ppc->m_cap & PPCCAP_FPU)) return false; if (G_RA(op) == 0) return false; @@ -1056,7 +1056,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * case 0x297: // STFSX case 0x2d7: // STFDX case 0x3d7: // STFIWX - if (!(m_context.cap & PPCCAP_FPU)) + if (!(m_ppc->m_cap & PPCCAP_FPU)) return false; GPR_USED_OR_ZERO(desc, G_RA(op)); GPR_USED(desc, G_RB(op)); @@ -1066,7 +1066,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * case 0x2b7: // STFSUX case 0x2f7: // STFDUX - if (!(m_context.cap & PPCCAP_FPU)) + if (!(m_ppc->m_cap & PPCCAP_FPU)) return false; if (G_RA(op) == 0) return false; @@ -1089,7 +1089,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x3f6: // DCBZ - if (!(m_context.cap & (PPCCAP_VEA | PPCCAP_4XX))) + if (!(m_ppc->m_cap & (PPCCAP_VEA | PPCCAP_4XX))) return false; GPR_USED_OR_ZERO(desc, G_RA(op)); GPR_USED(desc, G_RB(op)); @@ -1099,7 +1099,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * case 0x106: // ICBT case 0x1c6: // DCCCI case 0x3c6: // ICCCI - if (!(m_context.cap & PPCCAP_4XX)) + if (!(m_ppc->m_cap & PPCCAP_4XX)) return false; GPR_USED_OR_ZERO(desc, G_RA(op)); GPR_USED(desc, G_RB(op)); @@ -1108,7 +1108,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * case 0x1e6: // DCREAD case 0x3e6: // ICREAD - if (!(m_context.cap & PPCCAP_4XX)) + if (!(m_ppc->m_cap & PPCCAP_4XX)) return false; GPR_USED_OR_ZERO(desc, G_RA(op)); GPR_USED(desc, G_RB(op)); @@ -1117,28 +1117,28 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc * return true; case 0x143: // MFDCR - if (!(m_context.cap & PPCCAP_4XX)) + if (!(m_ppc->m_cap & PPCCAP_4XX)) return false; GPR_MODIFIED(desc, G_RD(op)); desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION; return true; case 0x1c3: // MTDCR - if (!(m_context.cap & PPCCAP_4XX)) + if (!(m_ppc->m_cap & PPCCAP_4XX)) return false; GPR_USED(desc, G_RS(op)); desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION | OPFLAG_CAN_EXPOSE_EXTERNAL_INT; return true; case 0x083: // WRTEE - if (!(m_context.cap & PPCCAP_4XX)) + if (!(m_ppc->m_cap & PPCCAP_4XX)) return false; GPR_USED(desc, G_RS(op)); desc.flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT; return true; case 0x0a3: // WRTEEI - if (!(m_context.cap & PPCCAP_4XX)) + if (!(m_ppc->m_cap & PPCCAP_4XX)) return false; if (op & MSR_EE) desc.flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT; @@ -1166,7 +1166,7 @@ bool ppc_frontend::describe_3b(UINT32 op, opcode_desc &desc, const opcode_desc * { UINT32 opswitch = (op >> 1) & 0x1f; - if (!(m_context.cap & PPCCAP_FPU)) + if (!(m_ppc->m_cap & PPCCAP_FPU)) return false; switch (opswitch) @@ -1242,7 +1242,7 @@ bool ppc_frontend::describe_3f(UINT32 op, opcode_desc &desc, const opcode_desc * { UINT32 opswitch = (op >> 1) & 0x3ff; - if (!(m_context.cap & PPCCAP_FPU)) + if (!(m_ppc->m_cap & PPCCAP_FPU)) return false; if (opswitch & 0x10) diff --git a/src/emu/cpu/powerpc/ppcfe.h b/src/emu/cpu/powerpc/ppcfe.h index 85c1aa334c2..5ba2f53dbb1 100644 --- a/src/emu/cpu/powerpc/ppcfe.h +++ b/src/emu/cpu/powerpc/ppcfe.h @@ -11,7 +11,7 @@ #ifndef __PPCFE_H__ #define __PPCFE_H__ -#include "ppccom.h" +#include "ppc.h" #include "cpu/drcfe.h" @@ -49,7 +49,7 @@ class ppc_frontend : public drc_frontend { public: // construction/destruction - ppc_frontend(powerpc_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence); + ppc_frontend(ppc_device *ppc, UINT32 window_start, UINT32 window_end, UINT32 max_sequence); protected: // required overrides @@ -58,10 +58,10 @@ protected: private: // inlines UINT32 compute_spr(UINT32 spr) const { return ((spr >> 5) | (spr << 5)) & 0x3ff; } - bool is_403_class() const { return (m_context.flavor == PPC_MODEL_403GA || m_context.flavor == PPC_MODEL_403GB || m_context.flavor == PPC_MODEL_403GC || m_context.flavor == PPC_MODEL_403GCX || m_context.flavor == PPC_MODEL_405GP); } - bool is_601_class() const { return (m_context.flavor == PPC_MODEL_601); } - bool is_602_class() const { return (m_context.flavor == PPC_MODEL_602); } - bool is_603_class() const { return (m_context.flavor == PPC_MODEL_603 || m_context.flavor == PPC_MODEL_603E || m_context.flavor == PPC_MODEL_603EV || m_context.flavor == PPC_MODEL_603R); } + bool is_403_class() const { return (m_ppc->m_flavor == ppc_device::PPC_MODEL_403GA || m_ppc->m_flavor == ppc_device::PPC_MODEL_403GB || m_ppc->m_flavor == ppc_device::PPC_MODEL_403GC || m_ppc->m_flavor == ppc_device::PPC_MODEL_403GCX || m_ppc->m_flavor == ppc_device::PPC_MODEL_405GP); } + bool is_601_class() const { return (m_ppc->m_flavor == ppc_device::PPC_MODEL_601); } + bool is_602_class() const { return (m_ppc->m_flavor == ppc_device::PPC_MODEL_602); } + bool is_603_class() const { return (m_ppc->m_flavor == ppc_device::PPC_MODEL_603 || m_ppc->m_flavor == ppc_device::PPC_MODEL_603E || m_ppc->m_flavor == ppc_device::PPC_MODEL_603EV || m_ppc->m_flavor == ppc_device::PPC_MODEL_603R); } // internal helpers bool describe_13(UINT32 op, opcode_desc &desc, const opcode_desc *prev); @@ -70,7 +70,7 @@ private: bool describe_3f(UINT32 op, opcode_desc &desc, const opcode_desc *prev); // internal state - powerpc_state &m_context; + ppc_device *m_ppc; }; diff --git a/src/emu/drivers/testcpu.c b/src/emu/drivers/testcpu.c index fe85634d6a6..f5fdaa7dd93 100644 --- a/src/emu/drivers/testcpu.c +++ b/src/emu/drivers/testcpu.c @@ -97,7 +97,7 @@ public: m_space = &m_cpu->space(AS_PROGRAM); // configure DRC in the most compatible mode - ppcdrc_set_options(m_cpu, PPCDRC_COMPATIBLE_OPTIONS); + m_cpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS); // set a timer to go off right away timer_set(attotime::zero); @@ -185,17 +185,11 @@ ADDRESS_MAP_END // MACHINE DRIVERS //************************************************************************** -static const powerpc_config ppc_config = -{ - // 603e, Stretch, 1.3 - 66000000 // Multiplier 1, Bus = 66MHz, Core = 66MHz -}; - static MACHINE_CONFIG_START( testcpu, testcpu_state ) // CPUs MCFG_CPU_ADD("maincpu", PPC603E, 66000000) - MCFG_CPU_CONFIG(ppc_config) + MCFG_PPC_BUS_FREQUENCY(66000000) // Multiplier 1, Bus = 66MHz, Core = 66MHz MCFG_CPU_PROGRAM_MAP(ppc_mem) MACHINE_CONFIG_END diff --git a/src/mame/drivers/cobra.c b/src/mame/drivers/cobra.c index 54b13f603ac..571c0ebc8d9 100644 --- a/src/mame/drivers/cobra.c +++ b/src/mame/drivers/cobra.c @@ -617,9 +617,9 @@ public: { } - required_device<cpu_device> m_maincpu; - required_device<cpu_device> m_subcpu; - required_device<cpu_device> m_gfxcpu; + required_device<ppc_device> m_maincpu; + required_device<ppc4xx_device> m_subcpu; + required_device<ppc_device> m_gfxcpu; required_shared_ptr<UINT64> m_gfx_pagetable; required_device<k001604_device> m_k001604; required_device<ata_interface_device> m_ata; @@ -1923,6 +1923,7 @@ static void sub_sound_dma_w(device_t *device, int width, UINT32 data) static void sub_jvs_w(device_t *device, UINT8 data) { + cobra_state *cobra = device->machine().driver_data<cobra_state>(); cobra_jvs_host *jvs = downcast<cobra_jvs_host *>(device->machine().device("cobra_jvs_host")); #if LOG_JVS @@ -1947,7 +1948,7 @@ static void sub_jvs_w(device_t *device, UINT8 data) for (int i=0; i < rec_size; i++) { - ppc4xx_spu_receive_byte(device, rec_data[i]); + cobra->m_subcpu->ppc4xx_spu_receive_byte(rec_data[i]); } } } @@ -3116,17 +3117,6 @@ INPUT_PORTS_START( cobra ) PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_PLAYER(2) INPUT_PORTS_END -static powerpc_config main_ppc_cfg = -{ - XTAL_66_6667MHz /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ -}; - -static powerpc_config gfx_ppc_cfg = -{ - XTAL_66_6667MHz /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ -}; - - WRITE_LINE_MEMBER(cobra_state::ide_interrupt) { if (state == CLEAR_LINE) @@ -3176,7 +3166,7 @@ static MACHINE_CONFIG_START( cobra, cobra_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", PPC603, 100000000) /* 603EV, 100? MHz */ - MCFG_CPU_CONFIG(main_ppc_cfg) + MCFG_PPC_BUS_FREQUENCY(XTAL_66_6667MHz) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ MCFG_CPU_PROGRAM_MAP(cobra_main_map) MCFG_CPU_VBLANK_INT_DRIVER("screen", cobra_state, cobra_vblank) @@ -3184,7 +3174,7 @@ static MACHINE_CONFIG_START( cobra, cobra_state ) MCFG_CPU_PROGRAM_MAP(cobra_sub_map) MCFG_CPU_ADD("gfxcpu", PPC604, 100000000) /* 604, 100? MHz */ - MCFG_CPU_CONFIG(gfx_ppc_cfg) + MCFG_PPC_BUS_FREQUENCY(XTAL_66_6667MHz) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ MCFG_CPU_PROGRAM_MAP(cobra_gfx_map) MCFG_QUANTUM_TIME(attotime::from_hz(15005)) @@ -3273,12 +3263,12 @@ DRIVER_INIT_MEMBER(cobra_state, cobra) cobra_fifo::event_delegate(FUNC(cobra_state::s2mfifo_event_callback), this)) ); - ppc_set_dcstore_callback(m_maincpu, main_cpu_dc_store); + m_maincpu->ppc_set_dcstore_callback(main_cpu_dc_store); - ppc_set_dcstore_callback(m_gfxcpu, gfx_cpu_dc_store); + m_gfxcpu->ppc_set_dcstore_callback(gfx_cpu_dc_store); - ppc4xx_set_dma_write_handler(m_subcpu, 0, sub_sound_dma_w, 44100); - ppc4xx_spu_set_tx_handler(m_subcpu, sub_jvs_w); + m_subcpu->ppc4xx_set_dma_write_handler(0, sub_sound_dma_w, 44100); + m_subcpu->ppc4xx_spu_set_tx_handler(sub_jvs_w); m_comram[0] = auto_alloc_array(machine(), UINT32, 0x40000/4); diff --git a/src/mame/drivers/firebeat.c b/src/mame/drivers/firebeat.c index 591199faccf..d61f7a0a15c 100644 --- a/src/mame/drivers/firebeat.c +++ b/src/mame/drivers/firebeat.c @@ -181,7 +181,7 @@ public: m_ata(*this, "ata") { } - required_device<cpu_device> m_maincpu; + required_device<ppc4xx_device> m_maincpu; required_shared_ptr<UINT32> m_work_ram; required_device<fujitsu_29f016a_device> m_flash_main; required_device<fujitsu_29f016a_device> m_flash_snd1; @@ -1483,10 +1483,10 @@ READ16_MEMBER(firebeat_state::spu_unk_r) MACHINE_START_MEMBER(firebeat_state,firebeat) { /* set conservative DRC options */ - ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS); + m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS); /* configure fast RAM regions for DRC */ - ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x01ffffff, FALSE, m_work_ram); + m_maincpu->ppcdrc_add_fastram(0x00000000, 0x01ffffff, FALSE, m_work_ram); } static ADDRESS_MAP_START( firebeat_map, AS_PROGRAM, 32, firebeat_state ) @@ -1955,7 +1955,7 @@ static void security_w(device_t *device, UINT8 data) firebeat_state *state = device->machine().driver_data<firebeat_state>(); int r = state->ibutton_w(data); if (r >= 0) - ppc4xx_spu_receive_byte(state->m_maincpu, r); + state->m_maincpu->ppc4xx_spu_receive_byte(r); } /*****************************************************************************/ @@ -1983,7 +1983,7 @@ void firebeat_state::init_firebeat() m_cur_cab_data = cab_data; - ppc4xx_spu_set_tx_handler(m_maincpu, security_w); + m_maincpu->ppc4xx_spu_set_tx_handler(security_w); set_ibutton(rom); diff --git a/src/mame/drivers/gticlub.c b/src/mame/drivers/gticlub.c index e081580c9bd..b9b451d7ff4 100644 --- a/src/mame/drivers/gticlub.c +++ b/src/mame/drivers/gticlub.c @@ -265,7 +265,7 @@ public: static const int m_sound_timer_usec = 2400; required_shared_ptr<UINT32> m_work_ram; - required_device<cpu_device> m_maincpu; + required_device<ppc_device> m_maincpu; required_device<cpu_device> m_audiocpu; required_device<adsp21062_device> m_dsp; optional_device<cpu_device> m_dsp2; @@ -479,10 +479,10 @@ WRITE16_MEMBER(gticlub_state::soundtimer_count_w) MACHINE_START_MEMBER(gticlub_state,gticlub) { /* set conservative DRC options */ - ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS); + m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS); /* configure fast RAM regions for DRC */ - ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x000fffff, FALSE, m_work_ram); + m_maincpu->ppcdrc_add_fastram(0x00000000, 0x000fffff, FALSE, m_work_ram); m_sound_irq_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(gticlub_state::sound_irq), this)); } diff --git a/src/mame/drivers/hornet.c b/src/mame/drivers/hornet.c index 65b28167ae7..c043b937df8 100644 --- a/src/mame/drivers/hornet.c +++ b/src/mame/drivers/hornet.c @@ -357,7 +357,7 @@ public: required_shared_ptr<UINT32> m_workram; required_shared_ptr<UINT32> m_sharc_dataram0; optional_shared_ptr<UINT32> m_sharc_dataram1; - required_device<cpu_device> m_maincpu; + required_device<ppc4xx_device> m_maincpu; required_device<cpu_device> m_audiocpu; required_device<k056800_device> m_k056800; optional_device<cpu_device> m_gn680; @@ -919,10 +919,10 @@ void hornet_state::machine_start() m_jvs_sdata = auto_alloc_array_clear(machine(), UINT8, 1024); /* set conservative DRC options */ - ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS); + m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS); /* configure fast RAM regions for DRC */ - ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x003fffff, FALSE, m_workram); + m_maincpu->ppcdrc_add_fastram(0x00000000, 0x003fffff, FALSE, m_workram); save_item(NAME(m_led_reg0)); save_item(NAME(m_led_reg1)); @@ -1161,19 +1161,19 @@ int hornet_state::jvs_encode_data(UINT8 *in, int length) if (b == 0xe0) { sum += 0xd0 + 0xdf; - ppc4xx_spu_receive_byte(m_maincpu, 0xd0); - ppc4xx_spu_receive_byte(m_maincpu, 0xdf); + m_maincpu->ppc4xx_spu_receive_byte(0xd0); + m_maincpu->ppc4xx_spu_receive_byte(0xdf); } else if (b == 0xd0) { sum += 0xd0 + 0xcf; - ppc4xx_spu_receive_byte(m_maincpu, 0xd0); - ppc4xx_spu_receive_byte(m_maincpu, 0xcf); + m_maincpu->ppc4xx_spu_receive_byte(0xd0); + m_maincpu->ppc4xx_spu_receive_byte(0xcf); } else { sum += b; - ppc4xx_spu_receive_byte(m_maincpu, b); + m_maincpu->ppc4xx_spu_receive_byte(b); } } return sum; @@ -1266,11 +1266,11 @@ void hornet_state::jamma_jvs_cmd_exec() // write jvs return data sum = 0x00 + (rdata_ptr+1); - ppc4xx_spu_receive_byte(m_maincpu, 0xe0); // sync - ppc4xx_spu_receive_byte(m_maincpu, 0x00); // node - ppc4xx_spu_receive_byte(m_maincpu, rdata_ptr + 1); // num of bytes + m_maincpu->ppc4xx_spu_receive_byte(0xe0); // sync + m_maincpu->ppc4xx_spu_receive_byte(0x00); // node + m_maincpu->ppc4xx_spu_receive_byte(rdata_ptr + 1); // num of bytes sum += jvs_encode_data(rdata, rdata_ptr); - ppc4xx_spu_receive_byte(m_maincpu, sum - 1); // checksum + m_maincpu->ppc4xx_spu_receive_byte(sum - 1); // checksum m_jvs_sdata_ptr = 0; } @@ -1283,7 +1283,7 @@ DRIVER_INIT_MEMBER(hornet_state,hornet) m_konppc->set_cgboard_texture_bank(0, "bank5", memregion("user5")->base()); m_led_reg0 = m_led_reg1 = 0x7f; - ppc4xx_spu_set_tx_handler(m_maincpu, jamma_jvs_w); + m_maincpu->ppc4xx_spu_set_tx_handler(jamma_jvs_w); } DRIVER_INIT_MEMBER(hornet_state,hornet_2board) @@ -1292,7 +1292,7 @@ DRIVER_INIT_MEMBER(hornet_state,hornet_2board) m_konppc->set_cgboard_texture_bank(1, "bank6", memregion("user5")->base()); m_led_reg0 = m_led_reg1 = 0x7f; - ppc4xx_spu_set_tx_handler(m_maincpu, jamma_jvs_w); + m_maincpu->ppc4xx_spu_set_tx_handler(jamma_jvs_w); } /*****************************************************************************/ diff --git a/src/mame/drivers/konamim2.c b/src/mame/drivers/konamim2.c index cfe95dc6848..c3fa0f88d21 100644 --- a/src/mame/drivers/konamim2.c +++ b/src/mame/drivers/konamim2.c @@ -1148,11 +1148,6 @@ static INPUT_PORTS_START( m2 ) INPUT_PORTS_END -static const powerpc_config ppc602_config = -{ - 33000000 /* Multiplier 2, Bus = 33MHz, Core = 66MHz */ -}; - INTERRUPT_GEN_MEMBER(konamim2_state::m2) { if (m_irq_enable & 0x800000) @@ -1172,12 +1167,12 @@ static MACHINE_CONFIG_START( m2, konamim2_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", PPC602, 66000000) /* actually PPC602, 66MHz */ - MCFG_CPU_CONFIG(ppc602_config) + MCFG_PPC_BUS_FREQUENCY(33000000) /* Multiplier 2, Bus = 33MHz, Core = 66MHz */ MCFG_CPU_PROGRAM_MAP(m2_main) MCFG_CPU_VBLANK_INT_DRIVER("screen", konamim2_state, m2) MCFG_CPU_ADD("sub", PPC602, 66000000) /* actually PPC602, 66MHz */ - MCFG_CPU_CONFIG(ppc602_config) + MCFG_PPC_BUS_FREQUENCY(33000000) /* Multiplier 2, Bus = 33MHz, Core = 66MHz */ MCFG_CPU_PROGRAM_MAP(m2_main) /* video hardware */ diff --git a/src/mame/drivers/model3.c b/src/mame/drivers/model3.c index 6beb4b5bd9a..3b5339e3ad6 100644 --- a/src/mame/drivers/model3.c +++ b/src/mame/drivers/model3.c @@ -1184,10 +1184,10 @@ static void configure_fast_ram(running_machine &machine) { model3_state *state = machine.driver_data<model3_state>(); /* set conservative DRC options */ - ppcdrc_set_options(machine.device("maincpu"), PPCDRC_COMPATIBLE_OPTIONS - PPCDRC_ACCURATE_SINGLES); + machine.device<ppc_device>("maincpu")->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS - PPCDRC_ACCURATE_SINGLES); /* configure fast RAM regions for DRC */ - ppcdrc_add_fastram(machine.device("maincpu"), 0x00000000, 0x007fffff, FALSE, state->m_work_ram); + machine.device<ppc_device>("maincpu")->ppcdrc_add_fastram(0x00000000, 0x007fffff, FALSE, state->m_work_ram); } TIMER_CALLBACK_MEMBER(model3_state::model3_sound_timer_tick) @@ -5380,27 +5380,9 @@ TIMER_DEVICE_CALLBACK_MEMBER(model3_state::model3_interrupt) set_irq_line(0x0d, ASSERT_LINE); } -static const powerpc_config model3_10 = -{ - /* 603e, Stretch, 1.3 */ - 66000000 /* Multiplier 1, Bus = 66MHz, Core = 66MHz */ -}; - -static const powerpc_config model3_15 = -{ - /* 603e, Stretch, 1.3 */ - 66000000 /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ -}; - -static const powerpc_config model3_2x = -{ - /* 603e-PID7t, Goldeneye, 2.1 */ - 66000000 /* Multiplier 2.5, Bus = 66MHz, Core = 166MHz */ -}; - static MACHINE_CONFIG_START( model3_10, model3_state ) MCFG_CPU_ADD("maincpu", PPC603E, 66000000) - MCFG_CPU_CONFIG(model3_10) + MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 1, Bus = 66MHz, Core = 66MHz */ MCFG_CPU_PROGRAM_MAP(model3_mem) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", model3_state, model3_interrupt, "screen", 0, 1) @@ -5447,7 +5429,7 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_START( model3_15, model3_state ) MCFG_CPU_ADD("maincpu", PPC603E, 100000000) - MCFG_CPU_CONFIG(model3_15) + MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ MCFG_CPU_PROGRAM_MAP(model3_mem) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", model3_state, model3_interrupt, "screen", 0, 1) @@ -5498,7 +5480,7 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_START( model3_20, model3_state ) MCFG_CPU_ADD("maincpu", PPC603R, 166000000) - MCFG_CPU_CONFIG(model3_2x) + MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 2.5, Bus = 66MHz, Core = 166MHz */ MCFG_CPU_PROGRAM_MAP(model3_mem) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", model3_state, model3_interrupt, "screen", 0, 1) @@ -5535,7 +5517,7 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_START( model3_21, model3_state ) MCFG_CPU_ADD("maincpu", PPC603R, 166000000) - MCFG_CPU_CONFIG(model3_2x) + MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 2.5, Bus = 66MHz, Core = 166MHz */ MCFG_CPU_PROGRAM_MAP(model3_mem) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", model3_state, model3_interrupt, "screen", 0, 1) diff --git a/src/mame/drivers/nwk-tr.c b/src/mame/drivers/nwk-tr.c index 94d51b049e0..85fe51da442 100644 --- a/src/mame/drivers/nwk-tr.c +++ b/src/mame/drivers/nwk-tr.c @@ -256,7 +256,7 @@ public: UINT8 m_led_reg0; UINT8 m_led_reg1; required_shared_ptr<UINT32> m_work_ram; - required_device<cpu_device> m_maincpu; + required_device<ppc_device> m_maincpu; required_device<cpu_device> m_audiocpu; required_device<cpu_device> m_dsp; required_device<k056800_device> m_k056800; @@ -573,10 +573,10 @@ WRITE16_MEMBER(nwktr_state::soundtimer_count_w) void nwktr_state::machine_start() { /* set conservative DRC options */ - ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS); + m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS); /* configure fast RAM regions for DRC */ - ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x003fffff, FALSE, m_work_ram); + m_maincpu->ppcdrc_add_fastram(0x00000000, 0x003fffff, FALSE, m_work_ram); m_sound_irq_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(nwktr_state::sound_irq), this)); } diff --git a/src/mame/drivers/taitopjc.c b/src/mame/drivers/taitopjc.c index 169614ed213..35f494f2948 100644 --- a/src/mame/drivers/taitopjc.c +++ b/src/mame/drivers/taitopjc.c @@ -504,15 +504,9 @@ INTERRUPT_GEN_MEMBER(taitopjc_state::taitopjc_vbi) } -static const powerpc_config ppc603e_config = -{ - XTAL_66_6667MHz /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ -}; - - static MACHINE_CONFIG_START( taitopjc, taitopjc_state ) MCFG_CPU_ADD("maincpu", PPC603E, 100000000) - MCFG_CPU_CONFIG(ppc603e_config) + MCFG_PPC_BUS_FREQUENCY(XTAL_66_6667MHz) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ MCFG_CPU_PROGRAM_MAP(ppc603e_mem) /* TMP95C063F I/O CPU */ diff --git a/src/mame/drivers/taitotz.c b/src/mame/drivers/taitotz.c index 6d30c191bec..df4d7c55b98 100644 --- a/src/mame/drivers/taitotz.c +++ b/src/mame/drivers/taitotz.c @@ -547,7 +547,7 @@ public: { } - required_device<cpu_device> m_maincpu; + required_device<ppc_device> m_maincpu; required_device<cpu_device> m_iocpu; required_shared_ptr<UINT64> m_work_ram; required_shared_ptr<UINT16> m_mbox_ram; @@ -2641,10 +2641,10 @@ void taitotz_state::machine_reset() void taitotz_state::machine_start() { /* set conservative DRC options */ - ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS); + m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS); /* configure fast RAM regions for DRC */ - ppcdrc_add_fastram(m_maincpu, 0x40000000, 0x40ffffff, FALSE, m_work_ram); + m_maincpu->ppcdrc_add_fastram(0x40000000, 0x40ffffff, FALSE, m_work_ram); } @@ -2658,16 +2658,10 @@ WRITE_LINE_MEMBER(taitotz_state::ide_interrupt) m_iocpu->set_input_line(TLCS900_INT2, state); } -static const powerpc_config ppc603e_config = -{ - XTAL_66_6667MHz /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ -}; - - static MACHINE_CONFIG_START( taitotz, taitotz_state ) /* IBM EMPPC603eBG-100 */ MCFG_CPU_ADD("maincpu", PPC603E, 100000000) - MCFG_CPU_CONFIG(ppc603e_config) + MCFG_PPC_BUS_FREQUENCY(XTAL_66_6667MHz) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */ MCFG_CPU_PROGRAM_MAP(ppc603e_mem) /* TMP95C063F I/O CPU */ diff --git a/src/mame/drivers/triforce.c b/src/mame/drivers/triforce.c index 20e4fc72884..da2bb1ee609 100644 --- a/src/mame/drivers/triforce.c +++ b/src/mame/drivers/triforce.c @@ -439,7 +439,7 @@ public: virtual void machine_start(); virtual void video_start(); UINT32 screen_update_triforce(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); - required_device<cpu_device> m_maincpu; + required_device<ppc_device> m_maincpu; }; READ64_MEMBER(triforce_state::gc_pi_r) @@ -537,7 +537,7 @@ static void descrambler(UINT8* data, UINT32 size) void triforce_state::machine_start() { /* set conservative DRC options */ - ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS); + m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS); UINT8 *rom = (UINT8*)memregion("maincpu")->base(); descrambler(&rom[0x100], 0x1afe00); diff --git a/src/mame/drivers/ultrsprt.c b/src/mame/drivers/ultrsprt.c index 7cedda92f93..3eefeb5ce9c 100644 --- a/src/mame/drivers/ultrsprt.c +++ b/src/mame/drivers/ultrsprt.c @@ -25,7 +25,7 @@ public: static const UINT32 VRAM_PAGES = 2; static const UINT32 VRAM_PAGE_BYTES = 512 * 1024; - required_device<cpu_device> m_maincpu; + required_device<ppc_device> m_maincpu; required_device<cpu_device> m_audiocpu; required_device<k056800_device> m_k056800; required_shared_ptr<UINT32> m_workram; @@ -184,10 +184,10 @@ INPUT_PORTS_END void ultrsprt_state::machine_start() { /* set conservative DRC options */ - ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS); + m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS); /* configure fast RAM regions for DRC */ - ppcdrc_add_fastram(m_maincpu, 0xff000000, 0xff01ffff, FALSE, m_workram); + m_maincpu->ppcdrc_add_fastram(0xff000000, 0xff01ffff, FALSE, m_workram); m_vram = auto_alloc_array(machine(), UINT8, VRAM_PAGE_BYTES * VRAM_PAGES); diff --git a/src/mame/drivers/viper.c b/src/mame/drivers/viper.c index 24d547bfe92..cda792c6923 100644 --- a/src/mame/drivers/viper.c +++ b/src/mame/drivers/viper.c @@ -363,7 +363,7 @@ public: void mpc8240_epic_reset(void); int ds2430_insert_cmd_bit(int bit); void DS2430_w(int bit); - required_device<cpu_device> m_maincpu; + required_device<ppc_device> m_maincpu; required_device<ata_interface_device> m_ata; }; @@ -1986,11 +1986,6 @@ INPUT_PORTS_END /*****************************************************************************/ -static const powerpc_config viper_ppc_cfg = -{ - 100000000 -}; - INTERRUPT_GEN_MEMBER(viper_state::viper_vblank) { mpc8240_interrupt(MPC8240_IRQ0); @@ -2009,10 +2004,10 @@ void viper_state::machine_start() mpc8240_epic_init(); /* set conservative DRC options */ - ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS); + m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS); /* configure fast RAM regions for DRC */ - ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x00ffffff, FALSE, workram); + m_maincpu->ppcdrc_add_fastram(0x00000000, 0x00ffffff, FALSE, workram); ds2430_rom = (UINT8*)memregion("ds2430")->base(); } @@ -2033,7 +2028,7 @@ static MACHINE_CONFIG_START( viper, viper_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", MPC8240, 200000000) - MCFG_CPU_CONFIG(viper_ppc_cfg) + MCFG_PPC_BUS_FREQUENCY(100000000) MCFG_CPU_PROGRAM_MAP(viper_map) MCFG_CPU_VBLANK_INT_DRIVER("screen", viper_state, viper_vblank) diff --git a/src/mame/drivers/zr107.c b/src/mame/drivers/zr107.c index 70b9bfb0df6..3415a7a5690 100644 --- a/src/mame/drivers/zr107.c +++ b/src/mame/drivers/zr107.c @@ -210,7 +210,7 @@ public: m_konppc(*this, "konppc") { } - required_device<cpu_device> m_maincpu; + required_device<ppc_device> m_maincpu; required_device<cpu_device> m_audiocpu; required_device<cpu_device> m_dsp; optional_device<k001604_device> m_k001604; @@ -457,10 +457,10 @@ WRITE32_MEMBER(zr107_state::ccu_w) void zr107_state::machine_start() { /* set conservative DRC options */ - ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS); + m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS); /* configure fast RAM regions for DRC */ - ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x000fffff, FALSE, m_workram); + m_maincpu->ppcdrc_add_fastram(0x00000000, 0x000fffff, FALSE, m_workram); } static ADDRESS_MAP_START( zr107_map, AS_PROGRAM, 32, zr107_state ) diff --git a/src/mess/drivers/dm7000.c b/src/mess/drivers/dm7000.c index 8d041696f1b..a9af7336dfc 100644 --- a/src/mess/drivers/dm7000.c +++ b/src/mess/drivers/dm7000.c @@ -257,8 +257,8 @@ void dm7000_state::machine_reset() dcr[DCRSTB045_FRAME_BUFR_BASE] = 0x0f000000; m_scc0_lsr = UART_LSR_THRE | UART_LSR_TEMT; - ppc4xx_set_dcr_read_handler(m_maincpu, read32_delegate(FUNC(dm7000_state::dcr_r),this)); - ppc4xx_set_dcr_write_handler(m_maincpu, write32_delegate(FUNC(dm7000_state::dcr_w),this)); + m_maincpu->ppc4xx_set_dcr_read_handler(read32_delegate(FUNC(dm7000_state::dcr_r),this)); + m_maincpu->ppc4xx_set_dcr_write_handler(write32_delegate(FUNC(dm7000_state::dcr_w),this)); } void dm7000_state::video_start() @@ -297,16 +297,11 @@ WRITE8_MEMBER( dm7000_state::kbd_put ) m_scc0_lsr = 1; } -static const powerpc_config ppc405_config = -{ - 252000000 -}; - static MACHINE_CONFIG_START( dm7000, dm7000_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu",PPC405GP, 252000000 / 10) // Should be PPC405D4? // Slowed down 10 times in order to get normal response for now - MCFG_CPU_CONFIG(ppc405_config) + MCFG_PPC_BUS_FREQUENCY(252000000) MCFG_CPU_PROGRAM_MAP(dm7000_mem) diff --git a/src/mess/includes/dm7000.h b/src/mess/includes/dm7000.h index ed7276c4f8a..cb4ec4e96eb 100644 --- a/src/mess/includes/dm7000.h +++ b/src/mess/includes/dm7000.h @@ -17,7 +17,7 @@ public: { } - required_device<cpu_device> m_maincpu; + required_device<ppc4xx_device> m_maincpu; required_device<generic_terminal_device> m_terminal; DECLARE_WRITE8_MEMBER ( dm7000_iic0_w ); |