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author | 2022-03-05 04:35:01 +0900 | |
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committer | 2022-03-04 14:35:01 -0500 | |
commit | 79f0fe8c57bc01a09eb19590cdfce61ec51737af (patch) | |
tree | e90ba8376ee7f58b8af3a2fa51e3eca5ce5c65e5 | |
parent | 099f7c9bf743d83f846559488000c51182c108ce (diff) |
Added dmovt opcode to i960 cpu (#9341)
-rw-r--r-- | src/devices/cpu/i960/i960.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/devices/cpu/i960/i960.cpp b/src/devices/cpu/i960/i960.cpp index 68cb11d9357..9edd9f717d1 100644 --- a/src/devices/cpu/i960/i960.cpp +++ b/src/devices/cpu/i960/i960.cpp @@ -1455,6 +1455,22 @@ void i960_cpu_device::execute_op(uint32_t opcode) } break; + case 0x4: // dmovt + /* + The dmovt instruction moves a 32-bit word from one register to another + and tests the least-significant byte of the operand to determine if it is a + valid ASCII-coded decimal digit (001100002 through 001110012, + corresponding to the decimal digits 0 through 9). For valid digits, the + condition code (CC) is set to 000; otherwise the condition code is set to + 010. + */ + t1 = get_1_ri(opcode); + set_ri(opcode, t1); + m_AC &= 0xfff8; + if ((t1 & 0xff) < 0x30 || (t1 & 0xff) > 0x39) + m_AC |= 2; + break; + case 0x5: // modac m_icount -= 10; t1 = get_1_ri(opcode); |