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author couriersud <couriersud@gmx.org>2020-07-10 18:43:12 +0200
committer couriersud <couriersud@gmx.org>2020-07-10 20:04:16 +0200
commit5eef12fe18ec426ebdb7df1b4e4d3afe7634ca11 (patch)
tree75cd258bea429ccc019e09d9ac1928225cb359c8
parentd3422e1c944e4f17ee19af61efc465933293cfab (diff)
netlist: add 74121 device and refactor 74123 code.
* added 74121 device * migrate dip devices to netlist devices * refactor code to be based on device description structs
-rwxr-xr-xsrc/lib/netlist/buildVS/nltool.vcxproj1
-rwxr-xr-xsrc/lib/netlist/buildVS/nltool.vcxproj.filters3
-rw-r--r--src/lib/netlist/devices/net_lib.cpp6
-rw-r--r--src/lib/netlist/devices/nld_74123.cpp262
-rw-r--r--src/lib/netlist/devices/nld_74123.h20
-rw-r--r--src/lib/netlist/macro/nlm_cd4xxx.cpp57
-rw-r--r--src/lib/netlist/macro/nlm_cd4xxx.h3
-rw-r--r--src/lib/netlist/macro/nlm_ttl74xx.cpp222
-rw-r--r--src/lib/netlist/macro/nlm_ttl74xx.h9
-rw-r--r--src/lib/netlist/nl_base.h9
-rw-r--r--src/lib/netlist/prg/nltool.cpp2
11 files changed, 394 insertions, 200 deletions
diff --git a/src/lib/netlist/buildVS/nltool.vcxproj b/src/lib/netlist/buildVS/nltool.vcxproj
index 0cb27e86599..7c6982e680d 100755
--- a/src/lib/netlist/buildVS/nltool.vcxproj
+++ b/src/lib/netlist/buildVS/nltool.vcxproj
@@ -149,6 +149,7 @@
<AdditionalIncludeDirectories Condition="'$(Configuration)|$(Platform)'=='Release|x64'">$(SolutionDir)..\;$(SolutionDir)..\..\;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
<AdditionalOptions Condition="'$(Configuration)|$(Platform)'=='Release|x64'">/bigobj</AdditionalOptions>
</ClCompile>
+ <ClCompile Include="..\tests\test_pfunction.cpp" />
</ItemGroup>
<ItemGroup>
<ProjectReference Include="netlistlib.vcxproj">
diff --git a/src/lib/netlist/buildVS/nltool.vcxproj.filters b/src/lib/netlist/buildVS/nltool.vcxproj.filters
index 2a9c313c0d0..b7ef3607716 100755
--- a/src/lib/netlist/buildVS/nltool.vcxproj.filters
+++ b/src/lib/netlist/buildVS/nltool.vcxproj.filters
@@ -18,5 +18,8 @@
<ClCompile Include="..\prg\nltool.cpp">
<Filter>Source Files</Filter>
</ClCompile>
+ <ClCompile Include="..\tests\test_pfunction.cpp">
+ <Filter>Source Files</Filter>
+ </ClCompile>
</ItemGroup>
</Project> \ No newline at end of file
diff --git a/src/lib/netlist/devices/net_lib.cpp b/src/lib/netlist/devices/net_lib.cpp
index 5e9cd5607e2..02d888a1f3f 100644
--- a/src/lib/netlist/devices/net_lib.cpp
+++ b/src/lib/netlist/devices/net_lib.cpp
@@ -106,8 +106,8 @@ namespace devices
LIB_ENTRY(74107_dip)
#endif
LIB_ENTRY(74107A) // FIXME: implement missing DIP
+ LIB_ENTRY(74121)
LIB_ENTRY(74123)
- LIB_ENTRY(74123_dip)
LIB_ENTRY(74125)
LIB_ENTRY(74126)
LIB_ENTRY(74153)
@@ -152,7 +152,7 @@ namespace devices
LIB_ENTRY(CD4020)
LIB_ENTRY(CD4066_GATE)
LIB_ENTRY(CD4316_GATE)
- LIB_ENTRY(4538_dip)
+ LIB_ENTRY(4538)
LIB_ENTRY(schmitt_trigger)
// entries with suffix WI are legacy only
//ENTRY(4066, CD_4066, "+A,B")
@@ -173,7 +173,7 @@ namespace devices
LIB_ENTRY(74365_dip)
LIB_ENTRY(82S16_dip)
LIB_ENTRY(82S115_dip)
- LIB_ENTRY(9602_dip)
+ LIB_ENTRY(9602)
LIB_ENTRY(9310_dip)
LIB_ENTRY(9314_dip)
LIB_ENTRY(9316_dip)
diff --git a/src/lib/netlist/devices/nld_74123.cpp b/src/lib/netlist/devices/nld_74123.cpp
index e3b73c86d86..5ddd29a60db 100644
--- a/src/lib/netlist/devices/nld_74123.cpp
+++ b/src/lib/netlist/devices/nld_74123.cpp
@@ -12,27 +12,71 @@ namespace netlist
{
namespace devices
{
- template <int DEVTYPE = 74123>
+
+ /// \brief Base monostable device
+ ///
+ /// The basic operation is the following:
+ ///
+ /// After a trigger signal has been detected, the output changes to high.
+ /// The capacitor is quickly discharged until it reaches Vlow.
+ /// The device toggles into charging mode until Vhigh is reached. At this
+ /// point, the output is set to low. Charging continues until VCC - or
+ /// more specific VRC is reached.
+ ///
+ /// Using
+ ///
+ /// - Vlow = alpha * VCC
+ /// - Vhigh = (1-alpha) * VCC
+ /// - Ignoring Rext during discharge
+ ///
+ /// we have calculate the following time constants:
+ ///
+ /// - tD = - X*C * ln(alpha)
+ /// - tC = - R*C * ln(alhpa)
+ /// - tL = - R*C * ln(1.0 - alpha)
+ ///
+ /// where tD denotes the time to discharge from VCC to Vlow, tC denotes
+ /// the time to charge from 0.0 to Vhigh and tL denotes the time to charge
+ /// from 0 to Vlow. X denotes the internal resistance used to discharge the
+ /// capacitor. The total impulse duration is thus
+ ///
+ /// tP = tD + tC - tL
+ ///
+ /// Using K = ln(1 - alpha) - ln (alpha) = ln(1/alpha - 1)
+ ///
+ /// we get
+ ///
+ /// tP = R*C*K * (1 + X/R * ln(alpha) / K)
+ ///
+ /// and alpha = 1 / (1 + exp(K))
+ ///
+ /// Datasheets express the right term usually as
+ ///
+ /// (1 + f * 1000 / R) = (1 + X/R * ln(alpha) / K)
+ ///
+ /// and thus
+ ///
+ /// X = f * 1000 * K / ln(alpha)
+ ///
+ /// FIXME: Currently X is given directly (as RI). It would be better to use
+ /// f (usually 0.7) and K to calculate X.
+ ///
+ template <typename D>
NETLIB_OBJECT(74123_base)
{
- static_assert((DEVTYPE == 9602) || (DEVTYPE == 4538) || (DEVTYPE == 74123), "wrong device type");
-
NETLIB_CONSTRUCTOR(74123_base)
, m_RP(*this, "RP")
, m_RN(*this, "RN")
, m_RP_Q(*this, "_RP_Q")
, m_RN_Q(*this, "_RN_Q")
- , m_A(*this, "A")
- , m_B(*this, "B")
- , m_CLRQ(*this, "CLRQ")
+ , m_I(*this, D::names(), NETLIB_DELEGATE(ab_clear))
, m_Q(*this, "Q")
, m_QQ(*this, "QQ")
, m_CV(*this, "_CV") // internal
, m_last_trig(*this, "m_last_trig", 0)
, m_state(*this, "m_state", 0)
- , m_KP(*this, "m_KP", 0)
- , m_K(*this, "K", (DEVTYPE == 4538) ? nlconst::one() : nlconst::magic(0.4)) // CD4538 datasheet states PW=RC
- , m_RI(*this, "RI", nlconst::magic(400.0)) // around 250 for HC series, 400 on LS/TTL, estimated from datasheets
+ , m_KP(plib::reciprocal(nlconst::one() + plib::exp(D::K())))
+ //, m_power_pins(*this)
{
register_subalias("GND", m_RN.N());
@@ -46,60 +90,45 @@ namespace netlist
connect(m_RN.P(), m_RP.N());
connect(m_CV, m_RN.P());
- m_RP.m_RON.set(m_RI());
- m_RN.m_RON.set(m_RI());
+ m_RP.m_RON.set(D::RI());
+ m_RN.m_RON.set(D::RI());
}
- NETLIB_UPDATEI()
+ NETLIB_HANDLERI(ab_clear)
{
netlist_sig_t m_trig(0);
- netlist_sig_t res = !m_CLRQ();
- netlist_time t_AB_to_Q = NLTIME_FROM_NS(10);
- netlist_time t_C_to_Q = NLTIME_FROM_NS(10);
- if (DEVTYPE == 74123)
- {
- m_trig = (m_A() ^ 1) & m_B() & m_CLRQ();
- }
- else if (DEVTYPE == 9602)
- {
- m_trig = (m_A() ^ 1) | m_B();
- }
- else // 4538
- {
- m_trig = (m_B() ^ 1) | m_A();
- // The line below is from the datasheet truthtable ... doesn't make sense at all
- //res = res | m_A) | (m_B) ^ 1);
- t_AB_to_Q = NLTIME_FROM_NS(300);
- t_C_to_Q = NLTIME_FROM_NS(250);
- }
+ m_trig = D::trigfunc(m_I);
- if (res)
+ if (!D::clear(m_I))
{
- m_Q.push(0, t_C_to_Q);
- m_QQ.push(1, t_C_to_Q);
+ m_Q.push(0, D::t_C_to_Q::value());
+ m_QQ.push(1, D::t_C_to_Q::value());
/* quick charge until trigger */
/* FIXME: SGS datasheet shows quick charge to 5V,
* though schematics indicate quick charge to Vhigh only.
*/
- m_RP_Q.push(1, t_C_to_Q); // R_ON
- m_RN_Q.push(0, t_C_to_Q); // R_OFF
+ m_RP_Q.push(1, D::t_C_to_Q::value()); // R_ON
+ m_RN_Q.push(0, D::t_C_to_Q::value()); // R_OFF
m_state = 2; //charging (quick)
}
else if (!m_last_trig && m_trig)
{
// FIXME: Timing!
- m_Q.push(1, t_AB_to_Q);
- m_QQ.push(0,t_AB_to_Q);
+ m_Q.push(1, D::t_AB_to_Q::value());
+ m_QQ.push(0, D::t_AB_to_Q::value());
- m_RN_Q.push(1, t_AB_to_Q); // R_ON
- m_RP_Q.push(0, t_AB_to_Q); // R_OFF
+ m_RN_Q.push(1, D::t_AB_to_Q::value()); // R_ON
+ m_RP_Q.push(0, D::t_AB_to_Q::value()); // R_OFF
m_state = 1; // discharging
}
m_last_trig = m_trig;
+ }
+ NETLIB_UPDATEI()
+ {
if (m_state == 1)
{
const nl_fptype vLow = m_KP * m_RP.P()();
@@ -111,7 +140,7 @@ namespace netlist
}
if (m_state == 2)
{
- const nl_fptype vHigh = m_RP.P()() * (nlconst::one() - m_KP);
+ const nl_fptype vHigh = (nlconst::one() - m_KP) * m_RP.P()();
if (m_CV() > vHigh)
{
m_RP_Q.push(0, NLTIME_FROM_NS(10)); // R_OFF
@@ -125,8 +154,6 @@ namespace netlist
NETLIB_RESETI()
{
- m_KP = plib::reciprocal(nlconst::one() + plib::exp(m_K()));
-
m_RP.reset();
m_RN.reset();
@@ -138,16 +165,13 @@ namespace netlist
}
private:
- public:
NETLIB_SUB(sys_dsw1) m_RP;
NETLIB_SUB(sys_dsw1) m_RN;
logic_output_t m_RP_Q;
logic_output_t m_RN_Q;
- logic_input_t m_A;
- logic_input_t m_B;
- logic_input_t m_CLRQ;
+ object_array_t<logic_input_t, 3> m_I;
logic_output_t m_Q;
logic_output_t m_QQ;
@@ -155,130 +179,70 @@ namespace netlist
state_var<netlist_sig_t> m_last_trig;
state_var<unsigned> m_state;
- state_var<nl_fptype> m_KP;
-
- param_fp_t m_K;
- param_fp_t m_RI;
+ nl_fptype m_KP;
+ //nld_power_pins m_power_pins; // not needed, device exposes VCC and GND
};
- NETLIB_OBJECT(74123_dip)
+ struct desc_74123 : public desc_base
{
- NETLIB_CONSTRUCTOR(74123_dip)
- , m_A(*this, "A")
- , m_B(*this, "B")
+ using t_AB_to_Q = time_ns<10>;
+ using t_C_to_Q = time_ns<10>;
+ static constexpr nl_fptype K() { return nlconst::magic(0.4); }
+ static constexpr nl_fptype RI() { return nlconst::magic(400.0); }
+
+ static constexpr std::array<const char *, 3> names() { return {"CLRQ", "A", "B"};}
+ template<typename T>
+ static netlist_sig_t trigfunc(const T &in)
{
- register_subalias("1", m_A.m_A);
- register_subalias("2", m_A.m_B);
- register_subalias("3", m_A.m_CLRQ);
- register_subalias("4", m_A.m_QQ);
- register_subalias("5", m_B.m_Q);
- register_subalias("6", m_B.m_RN.N());
- register_subalias("7", m_B.m_RN.P());
- register_subalias("8", m_A.m_RN.N());
- connect(m_A.m_RN.N(), m_B.m_RN.N());
-
- register_subalias("9", m_B.m_A);
- register_subalias("10", m_B.m_B);
- register_subalias("11", m_B.m_CLRQ);
- register_subalias("12", m_B.m_QQ);
- register_subalias("13", m_A.m_Q);
- register_subalias("14", m_A.m_RN.N());
- register_subalias("15", m_A.m_RN.P());
- register_subalias("16", m_A.m_RP.P());
- connect(m_A.m_RP.P(), m_B.m_RP.P());
+ return ((in[1]() | (in[2]() ^ 1)) ^ 1) & in[0](); // ((m_A() | (m_B() ^ 1)) ^ 1) & m_CLRQ()
}
- NETLIB_RESETI() {}
- NETLIB_UPDATEI() {}
- private:
- NETLIB_SUB(74123_base)<74123> m_A;
- NETLIB_SUB(74123_base)<74123> m_B;
+ template<typename T> static constexpr netlist_sig_t clear(const T &in) { return in[0]();}
};
- NETLIB_OBJECT(9602_dip)
+ struct desc_74121 : public desc_74123
{
- NETLIB_CONSTRUCTOR(9602_dip)
- , m_A(*this, "A")
- , m_B(*this, "B")
+ static constexpr nl_fptype K() { return nlconst::magic(0.7); }
+
+ static constexpr std::array<const char *, 3> names() { return {"A1", "A2", "B"};}
+ template<typename T>
+ static netlist_sig_t trigfunc(const T &in)
{
- register_subalias("1", m_A.m_RN.N()); // C1
- register_subalias("2", m_A.m_RN.P()); // RC1
- register_subalias("3", m_A.m_CLRQ);
- register_subalias("4", m_A.m_B);
- register_subalias("5", m_A.m_A);
- register_subalias("6", m_A.m_Q);
- register_subalias("7", m_A.m_QQ);
- register_subalias("8", m_A.m_RN.N());
- connect(m_A.m_RN.N(), m_B.m_RN.N());
-
- register_subalias("9", m_B.m_QQ);
- register_subalias("10", m_B.m_Q);
- register_subalias("11", m_B.m_A);
- register_subalias("12", m_B.m_B);
- register_subalias("13", m_B.m_CLRQ);
- register_subalias("14", m_B.m_RN.P()); // RC2
- register_subalias("15", m_B.m_RN.N()); // C2
- register_subalias("16", m_A.m_RP.P());
- connect(m_A.m_RP.P(), m_B.m_RP.P());
+ return ((in[0]() | in[1]()) ^ 1) & in[0](); // ((m_A() | (m_B() ^ 1)) ^ 1) & m_CLRQ()
}
- NETLIB_RESETI() { }
- NETLIB_UPDATEI() { }
- private:
- NETLIB_SUB(74123_base)<9602> m_A;
- NETLIB_SUB(74123_base)<9602> m_B;
+ template<typename T> static constexpr netlist_sig_t clear(const T &in) { plib::unused_var(in); return 1;}
};
- NETLIB_OBJECT(4538_dip)
+ struct desc_9602 : public desc_74123
{
- NETLIB_CONSTRUCTOR_MODEL(4538_dip, "CD4XXX")
- , m_A(*this, "A")
- , m_B(*this, "B")
+ template<typename T>
+ static netlist_sig_t trigfunc(const T &in)
{
- register_subalias("1", m_A.m_RN.N()); // C1
- register_subalias("2", m_A.m_RN.P()); // RC1
- register_subalias("3", m_A.m_CLRQ);
- register_subalias("4", m_A.m_A);
- register_subalias("5", m_A.m_B);
- register_subalias("6", m_A.m_Q);
- register_subalias("7", m_A.m_QQ);
- register_subalias("8", m_A.m_RN.N());
- connect(m_A.m_RN.N(), m_B.m_RN.N());
-
- register_subalias("9", m_B.m_QQ);
- register_subalias("10", m_B.m_Q);
- register_subalias("11", m_B.m_B);
- register_subalias("12", m_B.m_A);
- register_subalias("13", m_B.m_CLRQ);
- register_subalias("14", m_B.m_RN.P()); // RC2
- register_subalias("15", m_B.m_RN.N()); // C2
- register_subalias("16", m_A.m_RP.P());
- connect(m_A.m_RP.P(), m_B.m_RP.P());
+ return ((in[1]() ^ 1) | in[2]()); // (m_A() ^ 1) | m_B()
}
- NETLIB_RESETI();
- NETLIB_UPDATEI();
- private:
- NETLIB_SUB(74123_base)<4538> m_A;
- NETLIB_SUB(74123_base)<4538> m_B;
};
- NETLIB_UPDATE(4538_dip)
+ struct desc_4538 : public desc_74123
{
- /* only called during startup */
- //m_1.update_dev();
- //m_2.update_dev();
- }
+ using t_AB_to_Q = time_ns<300>;
+ using t_C_to_Q = time_ns<250>;
+ static constexpr nl_fptype K() { return nlconst::one(); } // CD4538 datasheet states PW=RC
- NETLIB_RESET(4538_dip)
- {
- m_A.reset();
- m_B.reset();
- }
+ template<typename T>
+ static netlist_sig_t trigfunc(const T &in)
+ {
+ return (in[1]() | (in[2]() ^ 1)); // m_A() | (m_B() ^ 1)
+ }
+ };
- using NETLIB_NAME(74123) = NETLIB_NAME(74123_base)<74123>;
+ using NETLIB_NAME(74123) = NETLIB_NAME(74123_base)<desc_74123>;
+ using NETLIB_NAME(74121) = NETLIB_NAME(74123_base)<desc_74121>;
+ using NETLIB_NAME(4538) = NETLIB_NAME(74123_base)<desc_4538>;
+ using NETLIB_NAME(9602) = NETLIB_NAME(74123_base)<desc_9602>;
NETLIB_DEVICE_IMPL(74123, "TTL_74123", "")
- NETLIB_DEVICE_IMPL(74123_dip, "TTL_74123_DIP", "")
- NETLIB_DEVICE_IMPL(4538_dip, "CD4538_DIP", "")
- NETLIB_DEVICE_IMPL(9602_dip, "TTL_9602_DIP", "")
+ NETLIB_DEVICE_IMPL(74121, "TTL_74121", "")
+ NETLIB_DEVICE_IMPL(4538, "CD4538", "")
+ NETLIB_DEVICE_IMPL(9602, "TTL_9602", "")
} //namespace devices
} // namespace netlist
diff --git a/src/lib/netlist/devices/nld_74123.h b/src/lib/netlist/devices/nld_74123.h
index 3eca141b613..98e508f258d 100644
--- a/src/lib/netlist/devices/nld_74123.h
+++ b/src/lib/netlist/devices/nld_74123.h
@@ -54,21 +54,13 @@
#define TTL_74123(name) \
NET_REGISTER_DEV(TTL_74123, name)
-#define TTL_74123_DIP(name) \
- NET_REGISTER_DEV(TTL_74123_DIP, name)
+#define TTL_74121(name) \
+ NET_REGISTER_DEV(TTL_74121, name)
-/* The 9602 is very similar to the 123. Input triggering is slightly different
- * The 9602 uses an OR gate instead of an AND gate.
- */
-
-#define TTL_9602_DIP(name) \
- NET_REGISTER_DEV(TTL_9602_DIP, name)
-
-/*
- * The CD4538 is pretty similar to the 9602
- */
+#define TTL_9602(name) \
+ NET_REGISTER_DEV(TTL_9602, name)
-#define CD4538_DIP(name) \
- NET_REGISTER_DEV(CD4538_DIP, name)
+#define CD4538(name) \
+ NET_REGISTER_DEV(TTL_4538, name)
#endif /* NLD_74123_H_ */
diff --git a/src/lib/netlist/macro/nlm_cd4xxx.cpp b/src/lib/netlist/macro/nlm_cd4xxx.cpp
index 55aefe6f272..c5dfe1e9ef5 100644
--- a/src/lib/netlist/macro/nlm_cd4xxx.cpp
+++ b/src/lib/netlist/macro/nlm_cd4xxx.cpp
@@ -252,6 +252,62 @@ static NETLIST_START(CD4316_DIP)
NETLIST_END()
+//- Identifier: CD4538_DIP
+//- Title: CD4538BC Dual Precision Monostable
+//- Description: The CD4538BC is a dual, precision monostable multivibrator with
+//- independent trigger and reset controls. The device
+//- is retriggerable and resettable, and the control inputs are
+//- internally latched. Two trigger inputs are provided to allow
+//- either rising or falling edge triggering. The reset inputs are
+//- active LOW and prevent triggering while active. Precise
+//- control of output pulse-width has been achieved using linear
+//- CMOS techniques. The pulse duration and accuracy
+//- are determined by external components RX and CX. The
+//- device does not allow the timing capacitor to discharge
+//- through the timing pin on power-down condition. For this
+//- reason, no external protection resistor is required in series
+//- with the timing pin. Input protection from static discharge is
+//- provided on all pins.
+//-
+//- Pinalias: C1,RC1,CLRQ1,B1,A1,Q1,QQ1,GND,QQ2,Q2,A2,B2,CLRQ2,RC2,C2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- Limitations:
+//- Timing inaccuracies may occur for capacitances < 1nF. Please consult datasheet
+//-
+//- Example: 74123.cpp,74123_example
+//-
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/50871/FAIRCHILD/CD4538.html
+//-
+static NETLIST_START(CD4538_DIP)
+
+ CD4538(A)
+ CD4538(B)
+
+ ALIAS(1, A.C) // C1
+ ALIAS(2, A.RC) // RC1
+ ALIAS(3, A.CLRQ)
+ ALIAS(4, A.A)
+ ALIAS(5, A.B)
+ ALIAS(6, A.Q)
+ ALIAS(7, A.QQ)
+ ALIAS(8, A.C)
+
+ ALIAS(9, B.QQ)
+ ALIAS(10, B.Q)
+ ALIAS(11, B.B)
+ ALIAS(12, B.A)
+ ALIAS(13, B.CLRQ)
+ ALIAS(14, B.RC) // RC2
+ ALIAS(15, B.C) // C2
+ ALIAS(16, A.RP.1)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+NETLIST_END()
+
+
NETLIST_START(CD4XXX_lib)
TRUTHTABLE_START(CD4001_GATE, 2, 1, "")
@@ -287,5 +343,6 @@ NETLIST_START(CD4XXX_lib)
LOCAL_LIB_ENTRY(CD4016_DIP)
LOCAL_LIB_ENTRY(CD4066_DIP)
LOCAL_LIB_ENTRY(CD4316_DIP)
+ LOCAL_LIB_ENTRY(CD4538_DIP)
NETLIST_END()
diff --git a/src/lib/netlist/macro/nlm_cd4xxx.h b/src/lib/netlist/macro/nlm_cd4xxx.h
index 0de0c763718..ba90ad0fe64 100644
--- a/src/lib/netlist/macro/nlm_cd4xxx.h
+++ b/src/lib/netlist/macro/nlm_cd4xxx.h
@@ -61,6 +61,9 @@
#define CD4316_DIP(name) \
NET_REGISTER_DEV(CD4016_DIP, name)
+#define CD4538_DIP(name) \
+ NET_REGISTER_DEV(CD4538_DIP, name)
+
#endif
/* ----------------------------------------------------------------------------
* External declarations
diff --git a/src/lib/netlist/macro/nlm_ttl74xx.cpp b/src/lib/netlist/macro/nlm_ttl74xx.cpp
index 334b9dc8f5c..0f65bc52233 100644
--- a/src/lib/netlist/macro/nlm_ttl74xx.cpp
+++ b/src/lib/netlist/macro/nlm_ttl74xx.cpp
@@ -702,35 +702,169 @@ static NETLIST_START(TTL_74107_DIP)
NETLIST_END()
#endif
+//- Identifier: TTL_74121_DIP
+//- Title: DM74121 One-Shot with Clear and Complementary Outputs
+//- Description: The DM74121 is a monostable multivibrator featuring both
+//- positive and negative edge triggering with complementary
+//- outputs. An internal 2kΩ timing resistor is provided for
+//- design convenience minimizing component count and layout problems. this device can be used with a single external capacitor. Inputs (A) are active-LOW trigger transition
+//- inputs and input (B) is and active-HIGH transition Schmitttrigger input that allows jitter-free triggering from inputs with
+//- transition rates as slow as 1 volt/second. A high immunity
+//- to VCC noise of typically 1.5V is also provided by internal
+//- circuitry at the input stage.
+//- To obtain optimum and trouble free operation please read
+//- operating rules and one-shot application notes carefully
+//- and observe recommendations.
+//-
+//- Pinalias: QQ,NC,A1,A2,B,Q,GND,NC,RINT,C,RC,NC,NC,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- Limitations:
+//- Timing inaccuracies may occur for capacitances < 1nF. Please consult datasheet
+//-
+//- Example: 74123.cpp,74123_example
+//-
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/50894/FAIRCHILD/74121.html
+//-
+static NETLIST_START(TTL_74121_DIP)
+
+ TTL_74121(A)
+ RES(RINT, RES_K(2))
+ RES(RD, RES_M(1000))
+
+ ALIAS(1, A.QQ)
+ //ALIAS(2", ); NC
+ ALIAS(3, A.A1)
+ ALIAS(4, A.A2)
+ ALIAS(5, A.B)
+ ALIAS(6, A.Q)
+ ALIAS(7, A.GND)
+
+ //ALIAS(8", ); NC
+ ALIAS(9, RINT.1) // RINT
+ ALIAS(10, A.C) // CEXT
+ ALIAS(11, A.RC) // REXT
+ //ALIAS(12", ); NC
+ //ALIAS(13", ); NC
+ ALIAS(14, A.VCC)
+
+ NET_C(RINT.2, A.RC)
+
+ // Avoid error messages if RINT is not used.
+ NET_C(RINT.1, RD.2)
+ NET_C(RD.1, A.GND)
-/*
- * DM74155/DM74156: Dual 2-Line to 4-Line Decoders/Demultiplexers
- *
- * +-----+-------++-----------------+
- * | B A | G1 C1 || 1Y0 1Y1 1Y2 1Y3 |
- * +=====+=======++=================+
- * | X X | 1 X || 1 1 1 1 |
- * | 0 0 | 0 1 || 0 1 1 1 |
- * | 0 1 | 0 1 || 1 0 1 1 |
- * | 1 0 | 0 1 || 1 1 0 1 |
- * | 1 1 | 0 1 || 1 1 1 0 |
- * | X X | X 0 || 1 1 1 1 |
- * +-----+-------++-----------------+
- *
- * +-----+-------++-----------------+
- * | B A | G2 C2 || 2Y0 2Y1 2Y2 2Y3 |
- * +=====+=======++=================+
- * | X X | 1 X || 1 1 1 1 |
- * | 0 0 | 0 0 || 0 1 1 1 |
- * | 0 1 | 0 0 || 1 0 1 1 |
- * | 1 0 | 0 0 || 1 1 0 1 |
- * | 1 1 | 0 0 || 1 1 1 0 |
- * | X X | X 1 || 1 1 1 1 |
- * +-----+-------++-----------------+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
+NETLIST_END()
+
+//- Identifier: TTL_74123_DIP
+//- Title: DM74123 Dual Retriggerable One-Shot with Clear and Complementary Outputs
+//- Description: The DM74123 is a dual retriggerable monostable multivibrator
+//- capable of generating output pulses from a few
+//- nano-seconds to extremely long duration up to 100% duty
+//- cycle. Each device has three inputs permitting the choice of
+//- either leading-edge or trailing edge triggering. Pin (A) is an
+//- active-LOW transition trigger input and pin (B) is an activeHIGH transition trigger input. A LOW at the clear (CLR)
+//- input terminates the output pulse: which also inhibits triggering. An internal connection from CLR to the input gate
+//- makes it possible to trigger the circuit by a positive-going
+//- signal on CLR as shown in the Truth Table.
+//-
+//- To obtain the best and trouble free operation from this
+//- device please read the Operating Rules as well as the
+//- One–Shot Application Notes carefully and observe recommendations.
+//-
+//- Pinalias: A1,B1,CLRQ1,QQ1,Q2,C2,RC2,GND,A2,B2,CLRQ2,QQ2,Q1,C1,RC1,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- Limitations:
+//- Timing inaccuracies may occur for capacitances < 1nF. Please consult datasheet
+//-
+//- Example: 74123.cpp,74123_example
+//-
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/50893/FAIRCHILD/DM74123.html
+//-
+static NETLIST_START(TTL_74123_DIP)
+
+ TTL_74123(A)
+ TTL_74123(B)
+
+ ALIAS(1, A.A)
+ ALIAS(2, A.B)
+ ALIAS(3, A.CLRQ)
+ ALIAS(4, A.QQ)
+ ALIAS(5, B.Q)
+ ALIAS(6, B.C) // CEXT
+ ALIAS(7, B.RC) // REXT
+ ALIAS(8, A.GND)
+
+ ALIAS(9, B.A)
+ ALIAS(10, B.B)
+ ALIAS(11, B.CLRQ)
+ ALIAS(12, B.QQ)
+ ALIAS(13, A.Q)
+ ALIAS(14, A.C) // CEXT
+ ALIAS(15, A.RC) // REXT
+ ALIAS(16, A.VCC)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+NETLIST_END()
+
+//- Identifier: TTL_9602_DIP
+//- Title: DM9602 Dual Retriggerable, Resettable One Shots
+//- Description: These dual resettable, retriggerable one shots have two
+//- inputs per function; one which is active HIGH, and one
+//- which is active LOW. This allows the designer to employ
+//- either leading-edge or trailing-edge triggering, which is
+//- independent of input transition times. When input conditions for triggering are met, a new cycle starts and the
+//- external capacitor is allowed to rapidly discharge and then
+//- charge again. The retriggerable feature permits output
+//- pulse widths to be extended. In fact a continuous true output can be maintained by having an input cycle time which
+//- is shorter than the output cycle time. The output pulse may
+//- then be terminated at any time by applying a LOW logic
+//- level to the RESET pin. Retriggering may be inhibited by
+//- either connecting the Q output to an active HIGH input, or
+//- the Q output to an active LOW input.
+//- The DM74123 is a dual retriggerable monostable multivibrator
+//-
+//- Pinalias: C1,RC1,CLRQ1,B1,A1,Q1,QQ1,GND,QQ2,Q2,A2,B2,CLRQ2,RC2,C2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- Limitations:
+//- Timing inaccuracies may occur for capacitances < 1nF. Please consult datasheet
+//-
+//- Example: 74123.cpp,74123_example
+//-
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/51137/FAIRCHILD/DM9602.html
+//-
+static NETLIST_START(TTL_9602_DIP)
+
+ TTL_9602(A)
+ TTL_9602(B)
+
+ ALIAS(1, A.C) // C1
+ ALIAS(2, A.RC) // RC1
+ ALIAS(3, A.CLRQ)
+ ALIAS(4, A.B)
+ ALIAS(5, A.A)
+ ALIAS(6, A.Q)
+ ALIAS(7, A.QQ)
+ ALIAS(8, A.GND)
+
+ ALIAS(9, B.QQ)
+ ALIAS(10, B.Q)
+ ALIAS(11, B.A)
+ ALIAS(12, B.B)
+ ALIAS(13, B.CLRQ)
+ ALIAS(14, B.RC) // RC2
+ ALIAS(15, B.C) // C2
+ ALIAS(16, A.VCC)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+NETLIST_END()
//- Identifier: TTL_74125_DIP
//- Title: SN74125 QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
@@ -832,6 +966,35 @@ static NETLIST_START(TTL_74126_DIP)
NET_C(A1.GND, A2.GND, A3.GND, A4.GND)
NETLIST_END()
+/*
+ * DM74155/DM74156: Dual 2-Line to 4-Line Decoders/Demultiplexers
+ *
+ * +-----+-------++-----------------+
+ * | B A | G1 C1 || 1Y0 1Y1 1Y2 1Y3 |
+ * +=====+=======++=================+
+ * | X X | 1 X || 1 1 1 1 |
+ * | 0 0 | 0 1 || 0 1 1 1 |
+ * | 0 1 | 0 1 || 1 0 1 1 |
+ * | 1 0 | 0 1 || 1 1 0 1 |
+ * | 1 1 | 0 1 || 1 1 1 0 |
+ * | X X | X 0 || 1 1 1 1 |
+ * +-----+-------++-----------------+
+ *
+ * +-----+-------++-----------------+
+ * | B A | G2 C2 || 2Y0 2Y1 2Y2 2Y3 |
+ * +=====+=======++=================+
+ * | X X | 1 X || 1 1 1 1 |
+ * | 0 0 | 0 0 || 0 1 1 1 |
+ * | 0 1 | 0 0 || 1 0 1 1 |
+ * | 1 0 | 0 0 || 1 1 0 1 |
+ * | 1 1 | 0 0 || 1 1 1 0 |
+ * | X X | X 1 || 1 1 1 1 |
+ * +-----+-------++-----------------+
+ *
+ * Naming conventions follow National Semiconductor datasheet
+ *
+ */
+
static NETLIST_START(TTL_74155_DIP)
NET_REGISTER_DEV(TTL_74155A_GATE, A)
NET_REGISTER_DEV(TTL_74155B_GATE, B)
@@ -1682,6 +1845,9 @@ NETLIST_START(TTL74XX_lib)
LOCAL_LIB_ENTRY(TTL_7448_DIP)
#endif
LOCAL_LIB_ENTRY(TTL_7486_DIP)
+ LOCAL_LIB_ENTRY(TTL_74121_DIP)
+ LOCAL_LIB_ENTRY(TTL_74123_DIP)
+ LOCAL_LIB_ENTRY(TTL_9602_DIP)
LOCAL_LIB_ENTRY(TTL_74125_DIP)
LOCAL_LIB_ENTRY(TTL_74126_DIP)
#if (NL_USE_TRUTHTABLE_74107)
diff --git a/src/lib/netlist/macro/nlm_ttl74xx.h b/src/lib/netlist/macro/nlm_ttl74xx.h
index 63417177ccd..060ac8d54eb 100644
--- a/src/lib/netlist/macro/nlm_ttl74xx.h
+++ b/src/lib/netlist/macro/nlm_ttl74xx.h
@@ -284,6 +284,15 @@
#endif
+#define TTL_74121_DIP(name) \
+ NET_REGISTER_DEV(TTL_74121_DIP, name)
+
+#define TTL_74123_DIP(name) \
+ NET_REGISTER_DEV(TTL_74123_DIP, name)
+
+#define TTL_9602_DIP(name) \
+ NET_REGISTER_DEV(TTL_9602_DIP, name)
+
#define TTL_74125_DIP(name) \
NET_REGISTER_DEV(TTL_74125_DIP, name)
diff --git a/src/lib/netlist/nl_base.h b/src/lib/netlist/nl_base.h
index 0891e81c6b4..2e6f0f68d46 100644
--- a/src/lib/netlist/nl_base.h
+++ b/src/lib/netlist/nl_base.h
@@ -1919,12 +1919,11 @@ namespace netlist
{
public:
template<class D, typename... Args>
- object_array_base_t(D &dev, const std::initializer_list<const char *> &names, Args&&... args)
+ //object_array_base_t(D &dev, const std::initializer_list<const char *> &names, Args&&... args)
+ object_array_base_t(D &dev, std::array<const char *, N> &&names, Args&&... args)
{
- passert_always_msg(names.size() == N, "initializer_list size mismatch");
- std::size_t i = 0;
- for (const auto &n : names)
- this->emplace(i++, dev, pstring(n), std::forward<Args>(args)...);
+ for (std::size_t i = 0; i<N; i++)
+ this->emplace(i, dev, pstring(names[i]), std::forward<Args>(args)...);
}
template<class D>
diff --git a/src/lib/netlist/prg/nltool.cpp b/src/lib/netlist/prg/nltool.cpp
index 7b18b00d77d..eeeabc772c2 100644
--- a/src/lib/netlist/prg/nltool.cpp
+++ b/src/lib/netlist/prg/nltool.cpp
@@ -1069,7 +1069,7 @@ void tool_app_t::create_docheader()
poutprefix("///", "");
poutprefix("///", " @section {}_4 Function Table", d.id);
poutprefix("///", "");
- if (!d.functiontable.empty())
+ if (d.functiontable.empty())
poutprefix("///", " Please refer to the datasheet.");
else
poutprefix("///", " {}", d.functiontable);