diff options
author | 2017-12-22 23:49:18 +0100 | |
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committer | 2017-12-22 23:49:41 +0100 | |
commit | 50ee57f1b321318d746b9f27398fb6afbbba19e4 (patch) | |
tree | 508781cd431e8f63b6e64ebae4b8c49b28701cb0 | |
parent | be9fea28e4d6a8860c1bafc228b3a8f174fba8a6 (diff) |
tms1000: split execute_run into execute_one (nw)
-rw-r--r-- | src/devices/cpu/tms1000/tms1000c.cpp | 18 | ||||
-rw-r--r-- | src/devices/cpu/tms1000/tms1000c.h | 1 | ||||
-rw-r--r-- | src/devices/cpu/tms1000/tms1k_base.cpp | 259 | ||||
-rw-r--r-- | src/devices/cpu/tms1000/tms1k_base.h | 47 |
4 files changed, 171 insertions, 154 deletions
diff --git a/src/devices/cpu/tms1000/tms1000c.cpp b/src/devices/cpu/tms1000/tms1000c.cpp index f6287012d16..e7563fac9d4 100644 --- a/src/devices/cpu/tms1000/tms1000c.cpp +++ b/src/devices/cpu/tms1000/tms1000c.cpp @@ -64,3 +64,21 @@ u32 tms1000c_cpu_device::decode_micro(u8 sel) return decode; } + + +// execute +void tms1000c_cpu_device::execute_run() +{ + while (m_icount > 0) + { + if (m_halt_pin) + { + // not running (output pins remain unchanged) + m_icount = 0; + return; + } + + m_icount--; + execute_one(); + } +} diff --git a/src/devices/cpu/tms1000/tms1000c.h b/src/devices/cpu/tms1000/tms1000c.h index 7857bf07f0c..364dd56879f 100644 --- a/src/devices/cpu/tms1000/tms1000c.h +++ b/src/devices/cpu/tms1000/tms1000c.h @@ -23,6 +23,7 @@ protected: // overrides virtual void device_add_mconfig(machine_config &config) override; virtual u32 decode_micro(u8 sel) override; + virtual void execute_run() override; virtual void op_br() override { op_br3(); } // 3-level stack virtual void op_call() override { op_call3(); } // " diff --git a/src/devices/cpu/tms1000/tms1k_base.cpp b/src/devices/cpu/tms1000/tms1k_base.cpp index eaac999b2ce..780cb399cd3 100644 --- a/src/devices/cpu/tms1000/tms1k_base.cpp +++ b/src/devices/cpu/tms1000/tms1k_base.cpp @@ -144,7 +144,7 @@ void tms1k_base_device::device_start() m_r = 0; m_o = 0; m_o_index = 0; - m_halt = false; + m_halt_pin = false; m_cki_bus = 0; m_c4 = 0; m_p = 0; @@ -184,7 +184,7 @@ void tms1k_base_device::device_start() save_item(NAME(m_r)); save_item(NAME(m_o)); save_item(NAME(m_o_index)); - save_item(NAME(m_halt)); + save_item(NAME(m_halt_pin)); save_item(NAME(m_cki_bus)); save_item(NAME(m_c4)); save_item(NAME(m_p)); @@ -314,7 +314,7 @@ void tms1k_base_device::execute_set_input(int line, int state) return; // HALT pin (CMOS only) - m_halt = bool(state); + m_halt_pin = bool(state); } void tms1k_base_device::write_o_output(u8 index) @@ -604,145 +604,142 @@ void tms1k_base_device::op_sbl() //------------------------------------------------- -// execute_run +// execute //------------------------------------------------- -void tms1k_base_device::execute_run() +void tms1k_base_device::execute_one() { - while (m_icount > 0) + switch (m_subcycle) { - m_icount--; - - if (m_halt) - { - // not running (output pins remain unchanged) - m_icount = 0; - return; - } - - switch (m_subcycle) - { - case 0: - // fetch: rom address 1/2 - - // execute: br/call 2/2 - if (m_fixed & F_BR) op_br(); - if (m_fixed & F_CALL) op_call(); - if (m_fixed & F_RETN) op_retn(); - - // execute: k input valid, read ram, clear alu inputs - dynamic_output(); - set_cki_bus(); - m_ram_in = m_data->read_byte(m_ram_address) & 0xf; - m_dam_in = m_data->read_byte(m_ram_address | (0x10 << (m_x_bits-1))) & 0xf; - m_p = 0; - m_n = 0; - m_carry_in = 0; + case 0: + // fetch: rom address 1/2 + + // execute: br/call 2/2 + if (m_fixed & F_BR) op_br(); + if (m_fixed & F_CALL) op_call(); + if (m_fixed & F_RETN) op_retn(); + + // execute: k input valid, read ram, clear alu inputs + dynamic_output(); + set_cki_bus(); + m_ram_in = m_data->read_byte(m_ram_address) & 0xf; + m_dam_in = m_data->read_byte(m_ram_address | (0x10 << (m_x_bits-1))) & 0xf; + m_p = 0; + m_n = 0; + m_carry_in = 0; + + break; + + case 1: + // fetch: rom address 2/2 + m_rom_address = (m_ca << (m_pc_bits+4)) | (m_pa << m_pc_bits) | m_pc; + + // execute: update alu inputs + // N inputs + if (m_micro & M_15TN) m_n |= 0xf; + if (m_micro & M_ATN) m_n |= m_a; + if (m_micro & M_NATN) m_n |= (~m_a & 0xf); + if (m_micro & M_CKN) m_n |= m_cki_bus; + if (m_micro & M_MTN) m_n |= m_ram_in; + + // P inputs + if (m_micro & M_CKP) m_p |= m_cki_bus; + if (m_micro & M_MTP) m_p |= m_ram_in; + if (m_micro & M_YTP) m_p |= m_y; + if (m_micro & M_DMTP) m_p |= m_dam_in; + if (m_micro & M_NDMTP) m_p |= (~m_dam_in & 0xf); + + // carry input + if (m_micro & M_CIN) m_carry_in |= 1; + if (m_micro & M_SSS) m_carry_in |= m_eac; + + break; + + case 2: + { + // fetch: nothing - break; + // execute: perform alu logic + // note: officially, only 1 alu operation is allowed per opcode + m_adder_out = m_p + m_n + m_carry_in; + int carry_out = m_adder_out >> 4 & 1; + int status = 1; + m_ram_out = -1; - case 1: - // fetch: rom address 2/2 - m_rom_address = (m_ca << (m_pc_bits+4)) | (m_pa << m_pc_bits) | m_pc; - - // execute: update alu inputs - // N inputs - if (m_micro & M_15TN) m_n |= 0xf; - if (m_micro & M_ATN) m_n |= m_a; - if (m_micro & M_NATN) m_n |= (~m_a & 0xf); - if (m_micro & M_CKN) m_n |= m_cki_bus; - if (m_micro & M_MTN) m_n |= m_ram_in; - - // P inputs - if (m_micro & M_CKP) m_p |= m_cki_bus; - if (m_micro & M_MTP) m_p |= m_ram_in; - if (m_micro & M_YTP) m_p |= m_y; - if (m_micro & M_DMTP) m_p |= m_dam_in; - if (m_micro & M_NDMTP) m_p |= (~m_dam_in & 0xf); - - // carry input - if (m_micro & M_CIN) m_carry_in |= 1; - if (m_micro & M_SSS) m_carry_in |= m_eac; + if (m_micro & M_C8) status &= carry_out; + if (m_micro & M_NE) status &= (m_n != m_p); // COMP + if (m_micro & M_CKM) m_ram_out = m_cki_bus; - break; - - case 2: + // special status circuit + if (m_micro & M_SSE) { - // fetch: nothing - - // execute: perform alu logic - // note: officially, only 1 alu operation is allowed per opcode - m_adder_out = m_p + m_n + m_carry_in; - int carry_out = m_adder_out >> 4 & 1; - int status = 1; - m_ram_out = -1; - - if (m_micro & M_C8) status &= carry_out; - if (m_micro & M_NE) status &= (m_n != m_p); // COMP - if (m_micro & M_CKM) m_ram_out = m_cki_bus; - - // special status circuit - if (m_micro & M_SSE) - { - m_eac = m_carry_out; - if (m_add) - m_eac |= carry_out; - } - m_carry_out = carry_out; - - if (m_micro & M_STO || (m_micro & M_CME && m_eac == m_add)) - m_ram_out = m_a; - - // handle the other fixed opcodes here - if (m_fixed & F_SBIT) op_sbit(); - if (m_fixed & F_RBIT) op_rbit(); - if (m_fixed & F_SETR) op_setr(); - if (m_fixed & F_RSTR) op_rstr(); - if (m_fixed & F_TDO) op_tdo(); - if (m_fixed & F_CLO) op_clo(); - if (m_fixed & F_LDX) op_ldx(); - if (m_fixed & F_COMX) op_comx(); - if (m_fixed & F_COMX8) op_comx8(); - if (m_fixed & F_LDP) op_ldp(); - if (m_fixed & F_COMC) op_comc(); - if (m_fixed & F_TPC) op_tpc(); - if (m_fixed & F_OFF) op_off(); - if (m_fixed & F_SEAC) op_seac(); - if (m_fixed & F_REAC) op_reac(); - if (m_fixed & F_SAL) op_sal(); - if (m_fixed & F_SBL) op_sbl(); - if (m_fixed & F_XDA) op_xda(); - - // after fixed opcode handling: store status, write ram - m_status = status; - if (m_ram_out != -1) - m_data->write_byte(m_ram_address, m_ram_out); - - break; + m_eac = m_carry_out; + if (m_add) + m_eac |= carry_out; } + m_carry_out = carry_out; + + if (m_micro & M_STO || (m_micro & M_CME && m_eac == m_add)) + m_ram_out = m_a; + + // handle the other fixed opcodes here + if (m_fixed & F_SBIT) op_sbit(); + if (m_fixed & F_RBIT) op_rbit(); + if (m_fixed & F_SETR) op_setr(); + if (m_fixed & F_RSTR) op_rstr(); + if (m_fixed & F_TDO) op_tdo(); + if (m_fixed & F_CLO) op_clo(); + if (m_fixed & F_LDX) op_ldx(); + if (m_fixed & F_COMX) op_comx(); + if (m_fixed & F_COMX8) op_comx8(); + if (m_fixed & F_LDP) op_ldp(); + if (m_fixed & F_COMC) op_comc(); + if (m_fixed & F_TPC) op_tpc(); + if (m_fixed & F_OFF) op_off(); + if (m_fixed & F_SEAC) op_seac(); + if (m_fixed & F_REAC) op_reac(); + if (m_fixed & F_SAL) op_sal(); + if (m_fixed & F_SBL) op_sbl(); + if (m_fixed & F_XDA) op_xda(); + + // after fixed opcode handling: store status, write ram + m_status = status; + if (m_ram_out != -1) + m_data->write_byte(m_ram_address, m_ram_out); + + break; + } - case 3: - // fetch: update pc, ram address 1/2 - // execute: register store 1/2 - break; - - case 4: - // execute: register store 2/2 - if (m_micro & M_AUTA) m_a = m_adder_out & 0xf; - if (m_micro & M_AUTY) m_y = m_adder_out & 0xf; - if (m_micro & M_STSL) m_status_latch = m_status; - - // fetch: update pc, ram address 2/2 - read_opcode(); - m_ram_address = m_x << 4 | m_y; - break; + case 3: + // fetch: update pc, ram address 1/2 + // execute: register store 1/2 + break; + + case 4: + // execute: register store 2/2 + if (m_micro & M_AUTA) m_a = m_adder_out & 0xf; + if (m_micro & M_AUTY) m_y = m_adder_out & 0xf; + if (m_micro & M_STSL) m_status_latch = m_status; + + // fetch: update pc, ram address 2/2 + read_opcode(); + m_ram_address = m_x << 4 | m_y; + break; + + case 5: + // fetch: instruction decode (handled above, before next_pc) + // execute: br/call 1/2 + break; + } - case 5: - // fetch: instruction decode (handled above, before next_pc) - // execute: br/call 1/2 - break; - } + m_subcycle = (m_subcycle + 1) % 6; +} - m_subcycle = (m_subcycle + 1) % 6; +void tms1k_base_device::execute_run() +{ + while (m_icount > 0) + { + m_icount--; + execute_one(); } } diff --git a/src/devices/cpu/tms1000/tms1k_base.h b/src/devices/cpu/tms1000/tms1k_base.h index b5e75ec77d2..e34e93e7d1c 100644 --- a/src/devices/cpu/tms1000/tms1k_base.h +++ b/src/devices/cpu/tms1000/tms1k_base.h @@ -106,10 +106,11 @@ protected: // device_execute_interface overrides virtual u32 execute_min_cycles() const override { return 1; } - virtual u32 execute_max_cycles() const override { return 6; } + virtual u32 execute_max_cycles() const override { return 1; } virtual u32 execute_input_lines() const override { return 1; } virtual void execute_set_input(int line, int state) override; virtual void execute_run() override; + virtual void execute_one(); // device_memory_interface overrides virtual space_config_vector memory_space_config() const override; @@ -151,28 +152,28 @@ protected: // standard/fixed instructions - these are documented more in their specific handlers enum { - F_BR = (1<<0), - F_CALL = (1<<1), - F_CLO = (1<<2), - F_COMC = (1<<3), - F_COMX = (1<<4), + F_BR = (1<<0), + F_CALL = (1<<1), + F_CLO = (1<<2), + F_COMC = (1<<3), + F_COMX = (1<<4), F_COMX8 = (1<<5), - F_LDP = (1<<6), - F_LDX = (1<<7), - F_RBIT = (1<<8), - F_RETN = (1<<9), - F_RSTR = (1<<10), - F_SBIT = (1<<11), - F_SETR = (1<<12), - F_TDO = (1<<13), - F_TPC = (1<<14), - - F_OFF = (1<<15), - F_REAC = (1<<16), - F_SAL = (1<<17), - F_SBL = (1<<18), - F_SEAC = (1<<19), - F_XDA = (1<<20) + F_LDP = (1<<6), + F_LDX = (1<<7), + F_RBIT = (1<<8), + F_RETN = (1<<9), + F_RSTR = (1<<10), + F_SBIT = (1<<11), + F_SETR = (1<<12), + F_TDO = (1<<13), + F_TPC = (1<<14), + + F_OFF = (1<<15), + F_REAC = (1<<16), + F_SAL = (1<<17), + F_SBL = (1<<18), + F_SEAC = (1<<19), + F_XDA = (1<<20) }; void next_pc(); @@ -256,7 +257,7 @@ protected: int m_subcycle; int m_icount; u8 m_o_index; - bool m_halt; // halt pin state + bool m_halt_pin; u8 m_o_pins; // how many O pins u8 m_r_pins; // how many R pins |