summaryrefslogtreecommitdiffstatshomepage
path: root/src/mess/machine/special.c
blob: 3ead45b349ff11d5e56b3d60bd5c226a478161b0 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
/***************************************************************************

        Specialist machine driver by Miodrag Milanovic

        20/03/2008 Cassette support
        15/03/2008 Preliminary driver.

****************************************************************************/



#include "includes/special.h"


/* Driver initialization */
DRIVER_INIT_MEMBER(special_state,special)
{
	/* set initialy ROM to be visible on first bank */
	UINT8 *RAM = machine().root_device().memregion("maincpu")->base();
	memset(RAM,0x0000,0x3000); // make first page empty by default
	membank("bank1")->configure_entries(1, 2, RAM, 0x0000);
	membank("bank1")->configure_entries(0, 2, RAM, 0xc000);
}

READ8_MEMBER( special_state::specialist_8255_porta_r )
{
	if (ioport("LINE0")->read()!=0xff) return 0xfe;
	if (ioport("LINE1")->read()!=0xff) return 0xfd;
	if (ioport("LINE2")->read()!=0xff) return 0xfb;
	if (ioport("LINE3")->read()!=0xff) return 0xf7;
	if (ioport("LINE4")->read()!=0xff) return 0xef;
	if (ioport("LINE5")->read()!=0xff) return 0xdf;
	if (ioport("LINE6")->read()!=0xff) return 0xbf;
	if (ioport("LINE7")->read()!=0xff) return 0x7f;
	return 0xff;
}

READ8_MEMBER( special_state::specialist_8255_portb_r )
{
	UINT8 dat = 0;
	double level;

	if ((m_specialist_8255_porta & 0x01)==0) dat ^= (ioport("LINE0")->read() ^ 0xff);
	if ((m_specialist_8255_porta & 0x02)==0) dat ^= (ioport("LINE1")->read() ^ 0xff);
	if ((m_specialist_8255_porta & 0x04)==0) dat ^= (ioport("LINE2")->read() ^ 0xff);
	if ((m_specialist_8255_porta & 0x08)==0) dat ^= (ioport("LINE3")->read() ^ 0xff);
	if ((m_specialist_8255_porta & 0x10)==0) dat ^= (ioport("LINE4")->read() ^ 0xff);
	if ((m_specialist_8255_porta & 0x20)==0) dat ^= (ioport("LINE5")->read() ^ 0xff);
	if ((m_specialist_8255_porta & 0x40)==0) dat ^= (ioport("LINE6")->read() ^ 0xff);
	if ((m_specialist_8255_porta & 0x80)==0) dat ^= (ioport("LINE7")->read() ^ 0xff);
	if ((m_specialist_8255_portc & 0x01)==0) dat ^= (ioport("LINE8")->read() ^ 0xff);
	if ((m_specialist_8255_portc & 0x02)==0) dat ^= (ioport("LINE9")->read() ^ 0xff);
	if ((m_specialist_8255_portc & 0x04)==0) dat ^= (ioport("LINE10")->read() ^ 0xff);
	if ((m_specialist_8255_portc & 0x08)==0) dat ^= (ioport("LINE11")->read() ^ 0xff);

	dat = (dat  << 2) ^0xff;
	if (ioport("LINE12")->read()!=0xff) dat ^= 0x02;

	level = m_cass->input();
	if (level >=  0)
			dat ^= 0x01;

	return dat;
}

READ8_MEMBER( special_state::specialist_8255_portc_r )
{
	if (ioport("LINE8")->read()!=0xff) return 0x0e;
	if (ioport("LINE9")->read()!=0xff) return 0x0d;
	if (ioport("LINE10")->read()!=0xff) return 0x0b;
	if (ioport("LINE11")->read()!=0xff) return 0x07;
	return 0x0f;
}

WRITE8_MEMBER( special_state::specialist_8255_porta_w )
{
	m_specialist_8255_porta = data;
}

WRITE8_MEMBER( special_state::specialist_8255_portb_w )
{
	m_specialist_8255_portb = data;
}

WRITE8_MEMBER( special_state::specialist_8255_portc_w )
{
	m_specialist_8255_portc = data;

	m_cass->output(BIT(data, 7) ? 1 : -1);

	m_dac->write_unsigned8(BIT(data, 5)); //beeper
}

I8255_INTERFACE( specialist_ppi8255_interface )
{
	DEVCB_DRIVER_MEMBER(special_state, specialist_8255_porta_r),
	DEVCB_DRIVER_MEMBER(special_state, specialist_8255_porta_w),
	DEVCB_DRIVER_MEMBER(special_state, specialist_8255_portb_r),
	DEVCB_DRIVER_MEMBER(special_state, specialist_8255_portb_w),
	DEVCB_DRIVER_MEMBER(special_state, specialist_8255_portc_r),
	DEVCB_DRIVER_MEMBER(special_state, specialist_8255_portc_w)
};

TIMER_CALLBACK_MEMBER(special_state::special_reset)
{
	membank("bank1")->set_entry(0);
}


MACHINE_RESET_MEMBER(special_state,special)
{
	machine().scheduler().timer_set(attotime::from_usec(10), timer_expired_delegate(FUNC(special_state::special_reset),this));
	membank("bank1")->set_entry(1);
}


/*
     Specialist MX
*/
WRITE8_MEMBER( special_state::video_memory_w )
{
	m_ram->pointer()[0x9000 + offset] = data;
	m_specimx_colorram[offset] = m_specimx_color;
}

WRITE8_MEMBER( special_state::specimx_video_color_w )
{
	m_specimx_color = data;
}

READ8_MEMBER( special_state::specimx_video_color_r )
{
	return m_specimx_color;
}

void special_state::specimx_set_bank(offs_t i, UINT8 data)
{
	address_space &space = m_maincpu->space(AS_PROGRAM);
	UINT8 *ram = m_ram->pointer();

	space.install_write_bank(0xc000, 0xffbf, "bank3");
	space.install_write_bank(0xffc0, 0xffdf, "bank4");
	membank("bank4")->set_base(ram + 0xffc0);
	switch(i)
	{
		case 0 :
			space.install_write_bank(0x0000, 0x8fff, "bank1");
			space.install_write_handler(0x9000, 0xbfff, write8_delegate(FUNC(special_state::video_memory_w), this));

			membank("bank1")->set_base(ram);
			membank("bank2")->set_base(ram + 0x9000);
			membank("bank3")->set_base(ram + 0xc000);
			break;
		case 1 :
			space.install_write_bank(0x0000, 0x8fff, "bank1");
			space.install_write_bank(0x9000, 0xbfff, "bank2");

			membank("bank1")->set_base(ram + 0x10000);
			membank("bank2")->set_base(ram + 0x19000);
			membank("bank3")->set_base(ram + 0x1c000);
			break;
		case 2 :
			space.unmap_write(0x0000, 0x8fff);
			space.unmap_write(0x9000, 0xbfff);

			membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base() + 0x10000);
			membank("bank2")->set_base(machine().root_device().memregion("maincpu")->base() + 0x19000);

			if (data & 0x80)
				membank("bank3")->set_base(ram + 0x1c000);
			else
				membank("bank3")->set_base(ram + 0xc000);

			break;
	}
}

WRITE8_MEMBER( special_state::specimx_select_bank )
{
	specimx_set_bank(offset, data);
}

WRITE_LINE_MEMBER( special_state::specimx_pit8253_out0_changed )
{
	specimx_set_input( m_specimx_audio, 0, state );
}

WRITE_LINE_MEMBER( special_state::specimx_pit8253_out1_changed )
{
	specimx_set_input( m_specimx_audio, 1, state );
}

WRITE_LINE_MEMBER( special_state::specimx_pit8253_out2_changed )
{
	specimx_set_input( m_specimx_audio, 2, state );
}



const struct pit8253_config specimx_pit8253_intf =
{
	{
		{
			2000000,
			DEVCB_NULL,
			DEVCB_DRIVER_LINE_MEMBER(special_state, specimx_pit8253_out0_changed)
		},
		{
			2000000,
			DEVCB_NULL,
			DEVCB_DRIVER_LINE_MEMBER(special_state, specimx_pit8253_out1_changed)
		},
		{
			2000000,
			DEVCB_NULL,
			DEVCB_DRIVER_LINE_MEMBER(special_state, specimx_pit8253_out2_changed)
		}
	}
};

MACHINE_START_MEMBER(special_state,specimx)
{
	m_specimx_audio = machine().device("custom");
	m_drive = 0;
	m_fdc->setup_drq_cb(fd1793_t::line_cb(FUNC(special_state::fdc_drq), this));
}

TIMER_CALLBACK_MEMBER(special_state::setup_pit8253_gates)
{
	device_t *pit8253 = machine().device("pit8253");

	pit8253_gate0_w(pit8253, 0);
	pit8253_gate1_w(pit8253, 0);
	pit8253_gate2_w(pit8253, 0);
}

MACHINE_RESET_MEMBER(special_state,specimx)
{
	specimx_set_bank(2, 0); // Initiali load ROM disk
	machine().scheduler().timer_set(attotime::zero, timer_expired_delegate(FUNC(special_state::setup_pit8253_gates),this));
}

READ8_MEMBER( special_state::specimx_disk_ctrl_r )
{
	return 0xff;
}

void special_state::fdc_drq(bool state)
{
	/* Clears HALT state of CPU when data is ready to read */
	if(state) {
		m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	}
}

WRITE8_MEMBER( special_state::specimx_disk_ctrl_w )
{
	static const char *names[] = { "fd0", "fd1"};
	floppy_image_device *floppy = NULL;
	floppy_connector *con = machine().device<floppy_connector>(names[m_drive & 1]);
	if(con)
		floppy = con->get_device();

	m_fdc->set_floppy(floppy);
	floppy->mon_w(0);

	switch(offset)
	{
		case 0 : 
				m_maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
				break;
		case 2 :
				floppy->ss_w(data & 1);
				break;
		case 3 :
				m_drive = data & 1;
				break;
	}
}

/*
    Erik
*/

void special_state::erik_set_bank()
{
	UINT8 bank1 = m_RR_register & 3;
	UINT8 bank2 = (m_RR_register >> 2) & 3;
	UINT8 bank3 = (m_RR_register >> 4) & 3;
	UINT8 bank4 = (m_RR_register >> 6) & 3;
	UINT8 *mem = memregion("maincpu")->base();
	UINT8 *ram = m_ram->pointer();
	address_space &space = m_maincpu->space(AS_PROGRAM);

	space.install_write_bank(0x0000, 0x3fff, "bank1");
	space.install_write_bank(0x4000, 0x8fff, "bank2");
	space.install_write_bank(0x9000, 0xbfff, "bank3");
	space.install_write_bank(0xc000, 0xefff, "bank4");
	space.install_write_bank(0xf000, 0xf7ff, "bank5");
	space.install_write_bank(0xf800, 0xffff, "bank6");

	switch(bank1)
	{
		case	1:
		case	2:
		case	3:
			membank("bank1")->set_base(ram + 0x10000*(bank1-1));
			break;
		case	0:
			space.unmap_write(0x0000, 0x3fff);
			membank("bank1")->set_base(mem + 0x10000);
			break;
	}
	switch(bank2)
	{
		case	1:
		case	2:
		case	3:
			membank("bank2")->set_base(ram + 0x10000*(bank2-1) + 0x4000);
			break;
		case	0:
			space.unmap_write(0x4000, 0x8fff);
			membank("bank2")->set_base(mem + 0x14000);
			break;
	}
	switch(bank3)
	{
		case	1:
		case	2:
		case	3:
			membank("bank3")->set_base(ram + 0x10000*(bank3-1) + 0x9000);
			break;
		case	0:
			space.unmap_write(0x9000, 0xbfff);
			membank("bank3")->set_base(mem + 0x19000);
			break;
	}
	switch(bank4)
	{
		case	1:
		case	2:
		case	3:
			membank("bank4")->set_base(ram + 0x10000*(bank4-1) + 0x0c000);
			membank("bank5")->set_base(ram + 0x10000*(bank4-1) + 0x0f000);
			membank("bank6")->set_base(ram + 0x10000*(bank4-1) + 0x0f800);
			break;
		case	0:
			space.unmap_write(0xc000, 0xefff);
			membank("bank4")->set_base(mem + 0x1c000);
			space.unmap_write(0xf000, 0xf7ff);
			space.nop_read(0xf000, 0xf7ff);
			space.install_readwrite_handler(0xf800, 0xf803, 0, 0x7fc, read8_delegate(FUNC(i8255_device::read), (i8255_device*)m_ppi), write8_delegate(FUNC(i8255_device::write), (i8255_device*)m_ppi));
			break;
	}
}

DRIVER_INIT_MEMBER(special_state,erik)
{
	m_erik_color_1 = 0;
	m_erik_color_2 = 0;
	m_erik_background = 0;
}

MACHINE_RESET_MEMBER(special_state,erik)
{
	m_RR_register = 0x00;
	m_RC_register = 0x00;
	erik_set_bank();
}

READ8_MEMBER( special_state::erik_rr_reg_r )
{
	return m_RR_register;
}

WRITE8_MEMBER( special_state::erik_rr_reg_w )
{
	m_RR_register = data;
	erik_set_bank();
}

READ8_MEMBER( special_state::erik_rc_reg_r )
{
	return m_RC_register;
}

WRITE8_MEMBER( special_state::erik_rc_reg_w )
{
	m_RC_register = data;
	m_erik_color_1 = m_RC_register & 7;
	m_erik_color_2 = (m_RC_register >> 3) & 7;
	m_erik_background = BIT(m_RC_register, 6) + BIT(m_RC_register, 7) * 4;
}

READ8_MEMBER( special_state::erik_disk_reg_r )
{
	return 0xff;
}

WRITE8_MEMBER( special_state::erik_disk_reg_w )
{
/*
	wd17xx_set_side (m_fdc,data & 1);
	wd17xx_set_drive(m_fdc,(data >> 1) & 1);
	wd17xx_dden_w(m_fdc, BIT(data, 2));
	floppy_mon_w(floppy_get_device(machine(), BIT(data, 1)), 0);
	floppy_mon_w(floppy_get_device(machine(), BIT(data, 1) ^ 1), 1);
	floppy_drive_set_ready_state(floppy_get_device(machine(), BIT(data, 1)), 1, 1);*/
}