blob: ed07e71e32f6df8442b9b853d46f7a7e85cf9e43 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
|
#ifndef __NES_HENGGEDIANZI_H
#define __NES_HENGGEDIANZI_H
#include "machine/nes_nxrom.h"
// ======================> nes_hengg_srich_device
class nes_hengg_srich_device : public nes_nrom_device
{
public:
// construction/destruction
nes_hengg_srich_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// device-level overrides
virtual void device_start();
virtual DECLARE_WRITE8_MEMBER(write_h);
virtual void pcb_reset();
};
// ======================> nes_hengg_xhzs_device
class nes_hengg_xhzs_device : public nes_nrom_device
{
public:
// construction/destruction
nes_hengg_xhzs_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// device-level overrides
virtual void device_start();
virtual DECLARE_WRITE8_MEMBER(write_l);
virtual DECLARE_WRITE8_MEMBER(write_h);
virtual void pcb_reset();
};
// ======================> nes_hengg_shjy3_device
class nes_hengg_shjy3_device : public nes_nrom_device
{
public:
// construction/destruction
nes_hengg_shjy3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// device-level overrides
virtual void device_start();
virtual DECLARE_WRITE8_MEMBER(write_h);
virtual void hblank_irq(int scanline, int vblank, int blanked);
virtual void pcb_reset();
private:
void update_banks();
UINT16 m_irq_count, m_irq_count_latch;
int m_irq_enable;
int m_chr_mode;
UINT8 m_mmc_prg_bank[2];
UINT8 m_mmc_vrom_bank[8];
UINT8 m_mmc_extra_bank[8];
};
// device type definition
extern const device_type NES_HENGG_SRICH;
extern const device_type NES_HENGG_XHZS;
extern const device_type NES_HENGG_SHJY3;
#endif
|