1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
|
// license:BSD-3-Clause
// copyright-holders:Angelo Salese
/***************************************************************************
Namco C139 - Serial I/F Controller
TODO:
- Make this to actually work!
- Is RAM shared with a specific CPU other than master/slave?
- is this another MCU with internal ROM?
***************************************************************************/
#include "emu.h"
#include "namco_c139.h"
//**************************************************************************
// GLOBAL VARIABLES
//**************************************************************************
// device type definition
DEFINE_DEVICE_TYPE(NAMCO_C139, namco_c139_device, "namco_c139", "Namco C139 Serial")
//**************************************************************************
// LIVE DEVICE
//**************************************************************************
void namco_c139_device::data_map(address_map &map)
{
map(0x0000, 0x3fff).ram().share("sharedram");
}
void namco_c139_device::regs_map(address_map &map)
{
map(0x00, 0x01).r(FUNC(namco_c139_device::status_r)); // WRITE clears flags
map(0x02, 0x03).noprw(); // settings?
// map(0x0a, 0x0b) // WRITE tx_w
// map(0x0c, 0x0d) // READ rx_r
// map(0x0e, 0x0f) //
}
//-------------------------------------------------
// namco_c139_device - constructor
//-------------------------------------------------
namco_c139_device::namco_c139_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, NAMCO_C139, tag, owner, clock),
device_memory_interface(mconfig, *this),
m_space_config("data", ENDIANNESS_BIG, 16, 14, 0, address_map_constructor(FUNC(namco_c139_device::data_map), this))
{
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void namco_c139_device::device_start()
{
m_ram = (uint16_t*)memshare("sharedram")->ptr();
}
//-------------------------------------------------
// device_reset - device-specific reset
//-------------------------------------------------
void namco_c139_device::device_reset()
{
}
//-------------------------------------------------
// memory_space_config - return a description of
// any address spaces owned by this device
//-------------------------------------------------
device_memory_interface::space_config_vector namco_c139_device::memory_space_config() const
{
return space_config_vector {
std::make_pair(AS_DATA, &m_space_config)
};
}
//**************************************************************************
// READ/WRITE HANDLERS
//**************************************************************************
uint16_t namco_c139_device::ram_r(offs_t offset)
{
return m_ram[offset];
}
void namco_c139_device::ram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_ram[offset]);
}
uint16_t namco_c139_device::status_r()
{
/*
x-- RX READY or irq pending?
-x- IRQ direction: 1 RX cause - 0 TX cause
*/
return 4; // STATUS bit?
}
|