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/***************************************************************************
RP5H01
***************************************************************************/
#ifndef __RP5H01_H__
#define __RP5H01_H__
/***************************************************************************
PARAMETERS
***************************************************************************/
/* these also work as the address masks */
enum {
COUNTER_MODE_6_BITS = 0x3f,
COUNTER_MODE_7_BITS = 0x7f
};
/***************************************************************************
MACROS / CONSTANTS
***************************************************************************/
class rp5h01_device : public device_t
{
public:
rp5h01_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
DECLARE_WRITE8_MEMBER( enable_w ); /* /CE */
DECLARE_WRITE8_MEMBER( reset_w ); /* RESET */
DECLARE_WRITE8_MEMBER( cs_w ); /* CS */
DECLARE_WRITE8_MEMBER( clock_w ); /* DATA CLOCK (active low) */
DECLARE_WRITE8_MEMBER( test_w ); /* TEST */
DECLARE_READ8_MEMBER( counter_r ); /* COUNTER OUT */
DECLARE_READ8_MEMBER( data_r ); /* DATA */
protected:
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
private:
// internal state
int m_counter;
int m_counter_mode; /* test pin */
int m_enabled; /* chip enable */
int m_old_reset; /* reset pin state (level-triggered) */
int m_old_clock; /* clock pin state (level-triggered) */
UINT8 *m_data;
};
extern const device_type RP5H01;
#define MCFG_RP5H01_ADD(_tag) \
MCFG_DEVICE_ADD(_tag, RP5H01, 0)
/*
* Device uses memory region
* with the same tag as the one
* assigned to device.
*/
#endif /* __RP5H01_H__ */
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