summaryrefslogtreecommitdiffstatshomepage
path: root/src/emu/cpu/sharc/sharcdma.c
blob: 8f6abf1964ce4af441e64f3f66864b719c5b4c00 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
/* SHARC DMA operations */

#define DMA_PMODE_NO_PACKING		0
#define DMA_PMODE_16_32				1
#define DMA_PMODE_16_48				2
#define DMA_PMODE_32_48				3
#define DMA_PMODE_8_48				4

static void schedule_chained_dma_op(SHARC_REGS *cpustate, int channel, UINT32 dma_chain_ptr, int chained_direction)
{
	UINT32 op_ptr = 0x20000 + dma_chain_ptr;

	UINT32 int_index		= dm_read32(cpustate, op_ptr - 0);
	UINT32 int_modifier		= dm_read32(cpustate, op_ptr - 1);
	UINT32 int_count		= dm_read32(cpustate, op_ptr - 2);
	UINT32 chain_ptr		= dm_read32(cpustate, op_ptr - 3);
	//UINT32 gen_purpose        = dm_read32(cpustate, op_ptr - 4);
	UINT32 ext_index		= dm_read32(cpustate, op_ptr - 5);
	UINT32 ext_modifier 	= dm_read32(cpustate, op_ptr - 6);
	UINT32 ext_count		= dm_read32(cpustate, op_ptr - 7);

	if (cpustate->dma_op[channel].active)
	{
		fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!\n", cpustate->pc);
	}

	if (chained_direction)		// Transmit to external
	{
		cpustate->dma_op[channel].dst			= ext_index;
		cpustate->dma_op[channel].dst_modifier	= ext_modifier;
		cpustate->dma_op[channel].dst_count		= ext_count;
		cpustate->dma_op[channel].src			= int_index;
		cpustate->dma_op[channel].src_modifier	= int_modifier;
		cpustate->dma_op[channel].src_count		= int_count;
	}
	else						// Receive from external
	{
		cpustate->dma_op[channel].src 			= ext_index;
		cpustate->dma_op[channel].src_modifier	= ext_modifier;
		cpustate->dma_op[channel].src_count		= ext_count;
		cpustate->dma_op[channel].dst			= int_index;
		cpustate->dma_op[channel].dst_modifier	= int_modifier;
		cpustate->dma_op[channel].dst_count		= int_count;
	}

	cpustate->dma_op[channel].pmode = 0;
	cpustate->dma_op[channel].chain_ptr = chain_ptr;
	cpustate->dma_op[channel].chained_direction = chained_direction;

	cpustate->dma_op[channel].active = true;

	int cycles = cpustate->dma_op[channel].src_count / 4;
	cpustate->dma_op[channel].timer->adjust(cpustate->device->cycles_to_attotime(cycles), channel);

	// enable busy flag
	cpustate->dma_status |= (1 << channel);
}

static void schedule_dma_op(SHARC_REGS *cpustate, int channel, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode)
{
	if (cpustate->dma_op[channel].active)
	{
		fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!\n", cpustate->pc);
	}

	cpustate->dma_op[channel].src = src;
	cpustate->dma_op[channel].dst = dst;
	cpustate->dma_op[channel].src_modifier = src_modifier;
	cpustate->dma_op[channel].dst_modifier = dst_modifier;
	cpustate->dma_op[channel].src_count = src_count;
	cpustate->dma_op[channel].dst_count = dst_count;
	cpustate->dma_op[channel].pmode = pmode;
	cpustate->dma_op[channel].chain_ptr = 0;

	cpustate->dma_op[channel].active = true;

	int cycles = src_count / 4;
	cpustate->dma_op[channel].timer->adjust(cpustate->device->cycles_to_attotime(cycles), channel);

	// enable busy flag
	cpustate->dma_status |= (1 << channel);
}

static void dma_op(SHARC_REGS *cpustate, int channel)
{
	int i;
	UINT32 src			= cpustate->dma_op[channel].src;
	UINT32 dst			= cpustate->dma_op[channel].dst;
	int src_modifier	= cpustate->dma_op[channel].src_modifier;
	int dst_modifier	= cpustate->dma_op[channel].dst_modifier;
	int src_count		= cpustate->dma_op[channel].src_count;
	//int dst_count		= cpustate->dma_op[channel].dst_count;
	int pmode			= cpustate->dma_op[channel].pmode;

	//printf("dma_op: %08X, %08X, %08X, %08X, %08X, %08X, %d\n", src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode);

	switch (pmode)
	{
		case DMA_PMODE_NO_PACKING:
		{
			for (i=0; i < src_count; i++)
			{
				UINT32 data = dm_read32(cpustate, src);
				dm_write32(cpustate, dst, data);
				src += src_modifier;
				dst += dst_modifier;
			}
			break;
		}
		case DMA_PMODE_16_32:
		{
			int length = src_count/2;
			for (i=0; i < length; i++)
			{
				UINT32 data = ((dm_read32(cpustate, src+0) & 0xffff) << 16) | (dm_read32(cpustate, src+1) & 0xffff);

				dm_write32(cpustate, dst, data);
				src += src_modifier * 2;
				dst += dst_modifier;
			}
			break;
		}
		case DMA_PMODE_8_48:
		{
			int length = src_count/6;
			for (i=0; i < length; i++)
			{
				UINT64 data = ((UINT64)(dm_read32(cpustate, src+0) & 0xff) <<  0) |
							  ((UINT64)(dm_read32(cpustate, src+1) & 0xff) <<  8) |
							  ((UINT64)(dm_read32(cpustate, src+2) & 0xff) << 16) |
							  ((UINT64)(dm_read32(cpustate, src+3) & 0xff) << 24) |
							  ((UINT64)(dm_read32(cpustate, src+4) & 0xff) << 32) |
							  ((UINT64)(dm_read32(cpustate, src+5) & 0xff) << 40);

				pm_write48(cpustate, dst, data);
				src += src_modifier * 6;
				dst += dst_modifier;
			}
			break;
		}
		default:
		{
			fatalerror("SHARC: dma_op: unimplemented packing mode %d\n", pmode);
		}
	}

	if (channel == 6)
	{
		cpustate->irptl |= (1 << (channel+10));

		/* DMA interrupt */
		if (cpustate->imask & (1 << (channel+10)))
		{
			cpustate->irq_active |= 1 << (channel+10);
		}
	}

	// clear busy flag
	cpustate->dma_status &= ~(1 << channel);

	cpustate->dma_op[channel].active = false;
}

static void sharc_dma_exec(SHARC_REGS *cpustate, int channel)
{
	UINT32 src, dst;
	UINT32 src_count, dst_count;
	UINT32 src_modifier, dst_modifier;
	int chen, tran, dtype, pmode, /*mswf, master,*/ ishake, intio/*, ext, flsh*/;

	chen = (cpustate->dma[channel].control >> 1) & 0x1;
	tran = (cpustate->dma[channel].control >> 2) & 0x1;
	dtype = (cpustate->dma[channel].control >> 5) & 0x1;
	pmode = (cpustate->dma[channel].control >> 6) & 0x3;
	//mswf = (cpustate->dma[channel].control >> 8) & 0x1;
	//master = (cpustate->dma[channel].control >> 9) & 0x1;
	ishake = (cpustate->dma[channel].control >> 10) & 0x1;
	intio = (cpustate->dma[channel].control >> 11) & 0x1;
	//ext = (cpustate->dma[channel].control >> 12) & 0x1;
	//flsh = (cpustate->dma[channel].control >> 13) & 0x1;

	if (ishake)
		fatalerror("SHARC: dma_exec: handshake not supported\n");
	if (intio)
		fatalerror("SHARC: dma_exec: single-word interrupt enable not supported\n");



	if (chen)		// Chained DMA
	{
		UINT32 dma_chain_ptr = cpustate->dma[channel].chain_ptr & 0x1ffff;

		schedule_chained_dma_op(cpustate, channel, dma_chain_ptr, tran);
	}
	else
	{
		if (tran)		// Transmit to external
		{
			dst 			= cpustate->dma[channel].ext_index;
			dst_modifier	= cpustate->dma[channel].ext_modifier;
			dst_count		= cpustate->dma[channel].ext_count;
			src				= cpustate->dma[channel].int_index;
			src_modifier	= cpustate->dma[channel].int_modifier;
			src_count		= cpustate->dma[channel].int_count;
		}
		else			// Receive from external
		{
			src 			= cpustate->dma[channel].ext_index;
			src_modifier	= cpustate->dma[channel].ext_modifier;
			src_count		= cpustate->dma[channel].ext_count;
			dst				= cpustate->dma[channel].int_index;
			dst_modifier	= cpustate->dma[channel].int_modifier;
			dst_count		= cpustate->dma[channel].int_count;

			if (dst < 0x20000)
			{
				dst |= 0x20000;
			}
		}

		if (dtype)
		//if (src_count != dst_count)
		{
			pmode = DMA_PMODE_8_48;
		}

		schedule_dma_op(cpustate, channel, src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode);
	}
}

static TIMER_CALLBACK(sharc_dma_callback)
{
	SHARC_REGS *cpustate = (SHARC_REGS *)ptr;
	int channel = param;

	cpustate->dma_op[channel].timer->adjust(attotime::never, 0);

	cpustate->irptl |= (1 << (channel+10));

	// DMA interrupt
	if (cpustate->imask & (1 << (channel+10)))
	{
		cpustate->irq_active |= 1 << (channel+10);
	}

	dma_op(cpustate, channel);
	if (cpustate->dma_op[channel].chain_ptr != 0)
	{
		schedule_chained_dma_op(cpustate, channel, cpustate->dma_op[channel].chain_ptr, cpustate->dma_op[channel].chained_direction);
	}
}