summaryrefslogtreecommitdiffstatshomepage
path: root/src/emu/cpu/m68000/68307sim.h
blob: 76b26391288e222fe467cd62aa1c3320d7758703 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
/* 68307 SIM module */

READ16_HANDLER( m68307_internal_sim_r );
WRITE16_HANDLER( m68307_internal_sim_w );

/* ports */
#define m68307SIM_PACNT (0x10)
#define m68307SIM_PADDR (0x12)
#define m68307SIM_PADAT (0x14)
#define m68307SIM_PBCNT (0x16)
#define m68307SIM_PBDDR (0x18)
#define m68307SIM_PBDAT (0x1a)


/* interrupt logic */
#define m68307SIM_LICR1 (0x20)
#define m68307SIM_LICR2 (0x22)
#define m68307SIM_PICR  (0x24)
#define m68307SIM_PIVR  (0x26)

/* used for the CS logic */
#define m68307SIM_BR0 (0x40)
#define m68307SIM_OR0 (0x42)
#define m68307SIM_BR1 (0x44)
#define m68307SIM_OR1 (0x46)
#define m68307SIM_BR2 (0x48)
#define m68307SIM_OR2 (0x4a)
#define m68307SIM_BR3 (0x4c)
#define m68307SIM_OR3 (0x4e)

class m68307_sim
{
	public:

	UINT16 m_pacnt; // 8-bit
	UINT16 m_paddr; // 8-bit
	UINT16 m_padat; // 8-bit

	UINT16 m_pbcnt;
	UINT16 m_pbddr;
	UINT16 m_pbdat;

	UINT16 m_pivr; // 8-bit

	UINT16 m_br[4];
	UINT16 m_or[4];
	UINT16 m_picr;
	UINT16 m_licr1;
	UINT16 m_licr2;


	void write_pacnt(UINT16 data, UINT16 mem_mask);
	void write_paddr(UINT16 data, UINT16 mem_mask);
	UINT16 read_padat(address_space *space, UINT16 mem_mask);
	void write_padat(address_space *space, UINT16 data, UINT16 mem_mask);

	void write_pbcnt(UINT16 data, UINT16 mem_mask);
	void write_pbddr(UINT16 data, UINT16 mem_mask);
	UINT16 read_pbdat(address_space *space, UINT16 mem_mask);
	void write_pbdat(address_space *space, UINT16 data, UINT16 mem_mask);



	void write_licr1(UINT16 data, UINT16 mem_mask);
	void write_licr2(UINT16 data, UINT16 mem_mask);
	void write_picr(UINT16 data, UINT16 mem_mask);
	void write_pivr(UINT16 data, UINT16 mem_mask);

	void reset(void);
};