summaryrefslogtreecommitdiffstatshomepage
path: root/src/emu/cpu/i8089/i8089_channel.c
blob: b8d93c7e0bf5c99119ef76210aa18596961186ab (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
/***************************************************************************

    Intel 8089 I/O Processor

    I/O channel

***************************************************************************/

#include "emu.h"
#include "debugger.h"
#include "i8089_channel.h"


//**************************************************************************
//  MACROS/CONSTANTS
//**************************************************************************

#define VERBOSE      1
#define VERBOSE_DMA  1

// channel control register fields
#define CC_TMC     ((m_r[CC].w >>  0) & 0x07)   // terminate on masked compare
#define CC_TBC     ((m_r[CC].w >>  3) & 0x03)   // terminate on byte count
#define CC_TX      ((m_r[CC].w >>  5) & 0x03)   // terminate on external signal
#define CC_TS      ((m_r[CC].w >>  7) & 0x01)   // terminate on single transfer
#define CC_CHAIN   ((m_r[CC].w >>  8) & 0x01)   // chaining
#define CC_LOCK    ((m_r[CC].w >>  9) & 0x01)   // actuate lock
#define CC_SOURCE  ((m_r[CC].w >> 10) & 0x01)   // source register
#define CC_SYNC    ((m_r[CC].w >> 11) & 0x03)   // synchronization
#define CC_TRANS   ((m_r[CC].w >> 13) & 0x01)   // translation
#define CC_FUNC    ((m_r[CC].w >> 14) & 0x03)   // function


//**************************************************************************
//  DEVICE DEFINITIONS
//**************************************************************************

const device_type I8089_CHANNEL = &device_creator<i8089_channel>;


//**************************************************************************
//  LIVE DEVICE
//**************************************************************************

//-------------------------------------------------
//  i8089_channel - constructor
//-------------------------------------------------

i8089_channel::i8089_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	device_t(mconfig, I8089_CHANNEL, "Intel 8089 I/O Channel", tag, owner, clock, "i8089_channel", __FILE__),
	m_write_sintr(*this),
	m_icount(0),
	m_xfer_pending(false),
	m_dma_value(0),
	m_dma_state(DMA_IDLE)
{
}

//-------------------------------------------------
//  device_start - device-specific startup
//-------------------------------------------------

void i8089_channel::device_start()
{
	// get parent device
	m_iop = downcast<i8089_device *>(owner());

	// resolve callbacks
	m_write_sintr.resolve_safe();

	// register for save states
	save_item(NAME(m_xfer_pending));
	save_item(NAME(m_dma_value));
	save_item(NAME(m_dma_state));

	for (int i = 0; i < ARRAY_LENGTH(m_r); i++)
	{
		save_item(NAME(m_r[i].w), i);
		save_item(NAME(m_r[i].t), i);
	}
}

//-------------------------------------------------
//  device_reset - device-specific reset
//-------------------------------------------------

void i8089_channel::device_reset()
{
	m_xfer_pending = false;

	// initialize registers
	for (int i = 0; i < ARRAY_LENGTH(m_r); i++)
	{
		m_r[i].w = 0;
		m_r[i].t = 0;
	}
}


//**************************************************************************
//  IMPLEMENTATION
//**************************************************************************

void i8089_channel::set_reg(int reg, int value, int tag)
{
	m_r[reg].w = value;

	if (tag != -1)
		m_r[reg].t = tag;

	if (reg == TP)
		m_iop->m_current_tp = value;
}

// channel status
bool i8089_channel::executing()    { return BIT(m_r[PSW].w, 2); }
bool i8089_channel::transferring() { return BIT(m_r[PSW].w, 6); }
bool i8089_channel::priority()     { return BIT(m_r[PSW].w, 7); }
bool i8089_channel::chained()      { return CC_CHAIN; }
bool i8089_channel::lock()         { return CC_LOCK; }

UINT16 i8089_channel::displacement(int wb)
{
	UINT16 displacement = 0;

	if (wb == 1)
	{
		displacement = m_iop->read_byte(m_r[TP].w);
		set_reg(TP, m_r[TP].w + 1);
	}
	else if (wb == 2)
	{
		displacement = m_iop->read_word(m_r[TP].w);
		set_reg(TP, m_r[TP].w + 2);
	}

	return displacement;
}

UINT8 i8089_channel::offset(int aa)
{
	UINT8 offset = 0;

	if (aa == 1)
	{
		offset = m_iop->read_byte(m_r[TP].w);
		set_reg(TP, m_r[TP].w + 1);
	}

	return offset;
}

UINT8 i8089_channel::imm8()
{
	UINT8 imm8 = m_iop->read_byte(m_r[TP].w);
	set_reg(TP, m_r[TP].w + 1);
	return imm8;
}

UINT16 i8089_channel::imm16()
{
	UINT16 imm16 = m_iop->read_word(m_r[TP].w);
	set_reg(TP, m_r[TP].w + 2);
	return imm16;
}

// adjust task pointer and continue execution
void i8089_channel::terminate_dma(int offset)
{
	if (VERBOSE)
		logerror("%s('%s'): terminating dma transfer\n", shortname(), tag());

	set_reg(TP, m_r[TP].w + offset);
	m_r[PSW].w |= 1 << 2;
	m_r[PSW].w &= ~(1 << 6);
	m_dma_state = DMA_IDLE;
}

int i8089_channel::execute_run()
{
	m_icount = 0;

	// active transfer?
	if (transferring())
	{
		// new transfer?
		if (executing())
		{
			// we are no longer executing task blocks
			m_r[PSW].w &= ~(1 << 2);
			m_xfer_pending = false;

			if (VERBOSE)
			{
				logerror("%s('%s'): ---- starting dma transfer ----\n", shortname(), tag());
				logerror("%s('%s'): ga = %06x, gb = %06x, gc = %06x\n", shortname(), tag(), m_r[GA].w, m_r[GB].w, m_r[GC].w);
				logerror("%s('%s'): bc = %04x, cc = %04x, mc = %04x\n", shortname(), tag(), m_r[BC].w, m_r[CC].w, m_r[MC].w);
			}
		}

		// todo: port transfers
		if (CC_FUNC != 0x03)
			fatalerror("%s('%s'): port transfer\n", shortname(), tag());

		switch (m_dma_state)
		{
		case DMA_IDLE:
			if (VERBOSE_DMA)
				logerror("%s('%s'): entering state: DMA_IDLE (bc = %04x)\n", shortname(), tag(), m_r[BC].w);

			// synchronize on source?
			if (CC_SYNC == 0x01)
				m_dma_state = DMA_WAIT_FOR_SOURCE_DRQ;
			else
				m_dma_state = DMA_FETCH;
			break;

		case DMA_WAIT_FOR_SOURCE_DRQ:
			fatalerror("%s('%s'): wait for source drq not supported\n", shortname(), tag());
			break;

		case DMA_FETCH:
			if (VERBOSE_DMA)
				logerror("%s('%s'): entering state: DMA_FETCH", shortname(), tag());

			// source is 16-bit?
			if (BIT(m_r[PSW].w, 1))
			{
				m_dma_value = m_iop->read_word(m_r[GA + CC_SOURCE].w);
				m_r[GA + CC_SOURCE].w += 2;
				m_r[BC].w -= 2;
			}
			// destination is 16-bit, byte count is even
			else if (BIT(m_r[PSW].w, 0) && !(m_r[BC].w & 1))
			{
				m_dma_value = m_iop->read_byte(m_r[GA + CC_SOURCE].w);
				m_r[GA + CC_SOURCE].w++;
				m_r[BC].w--;
			}
			// destination is 16-bit, byte count is odd
			else if (BIT(m_r[PSW].w, 0) && (m_r[BC].w & 1))
			{
				m_dma_value |= m_iop->read_byte(m_r[GA + CC_SOURCE].w) << 8;
				m_r[GA + CC_SOURCE].w++;
				m_r[BC].w--;
			}
			// 8-bit transfer
			else
			{
				m_dma_value = m_iop->read_byte(m_r[GA + CC_SOURCE].w);
				m_r[GA + CC_SOURCE].w++;
				m_r[BC].w--;
			}

			if (VERBOSE_DMA)
				logerror("[ %04x ]\n", m_dma_value);

			if (BIT(m_r[PSW].w, 0) && (m_r[BC].w & 1))
				m_dma_state = DMA_FETCH;
			else if (CC_TRANS)
				m_dma_state = DMA_TRANSLATE;
			else if (CC_SYNC == 0x02)
				m_dma_state = DMA_WAIT_FOR_DEST_DRQ;
			else
				m_dma_state = DMA_STORE;

			break;

		case DMA_TRANSLATE:
			fatalerror("%s('%s'): dma translate requested\n", shortname(), tag());
			break;

		case DMA_WAIT_FOR_DEST_DRQ:
			fatalerror("%s('%s'): wait for destination drq not supported\n", shortname(), tag());
			break;

		case DMA_STORE:
			if (VERBOSE_DMA)
				logerror("%s('%s'): entering state: DMA_STORE", shortname(), tag());

			// destination is 16-bit?
			if (BIT(m_r[PSW].w, 0))
			{
				m_iop->write_word(m_r[GB - CC_SOURCE].w, m_dma_value);
				m_r[GB - CC_SOURCE].w += 2;

				if (VERBOSE_DMA)
					logerror("[ %04x ]\n", m_dma_value);
			}
			// destination is 8-bit
			else
			{
				m_iop->write_byte(m_r[GB - CC_SOURCE].w, m_dma_value & 0xff);
				m_r[GB - CC_SOURCE].w++;

				if (VERBOSE_DMA)
					logerror("[ %02x ]\n", m_dma_value & 0xff);
			}

			if (CC_TMC & 0x03)
				m_dma_state = DMA_COMPARE;
			else
				m_dma_state = DMA_TERMINATE;

			break;

		case DMA_COMPARE:
			fatalerror("%s('%s'): dma compare requested\n", shortname(), tag());
			break;

		case DMA_TERMINATE:
			if (VERBOSE_DMA)
				logerror("%s('%s'): entering state: DMA_TERMINATE\n", shortname(), tag());

			// terminate on masked compare?
			if (CC_TMC & 0x03)
				fatalerror("%s('%s'): terminate on masked compare not supported\n", shortname(), tag());

			// terminate on byte count?
			else if (CC_TBC && m_r[BC].w == 0)
				terminate_dma((CC_TBC - 1) * 4);

			// terminate on external signal
			else if (CC_TX)
				fatalerror("%s('%s'): terminate on external signal not supported\n", shortname(), tag());

			// terminate on single transfer
			else if (CC_TS)
				fatalerror("%s('%s'): terminate on single transfer not supported\n", shortname(), tag());

			// not terminated, continue transfer
			else
				// do we need to read another byte?
				if (BIT(m_r[PSW].w, 1) && !BIT(m_r[PSW].w, 0))
					if (CC_SYNC == 0x02)
						m_dma_state = DMA_WAIT_FOR_DEST_DRQ;
					else
						m_dma_state = DMA_STORE_BYTE_HIGH;

				// transfer done
				else
					m_dma_state = DMA_IDLE;

			break;

		case DMA_STORE_BYTE_HIGH:
			if (VERBOSE_DMA)
				logerror("%s('%s'): entering state: DMA_STORE_BYTE_HIGH[ %02x ]\n", shortname(), tag(), (m_dma_value >> 8) & 0xff);

			m_iop->write_byte(m_r[GB - CC_SOURCE].w, (m_dma_value >> 8) & 0xff);
			m_r[GB - CC_SOURCE].w++;
			m_dma_state = DMA_TERMINATE;

			break;
		}

		m_icount++;
	}

	// executing task block instructions?
	else if (executing())
	{
		// call debugger
		debugger_instruction_hook(m_iop, m_iop->m_current_tp);

		// dma transfer pending?
		if (m_xfer_pending)
			m_r[PSW].w |= 1 << 6;

		// fetch first two instruction bytes
		UINT16 op = m_iop->read_word(m_r[TP].w);
		set_reg(TP, m_r[TP].w + 2);

		// extract parameters
		UINT8 params = op & 0xff;
		UINT8 opcode = (op >> 8) & 0xff;

		int brp = (params >> 5) & 0x07;
		int wb  = (params >> 3) & 0x03;
		int aa  = (params >> 1) & 0x03;
		int w   = (params >> 0) & 0x01;
		int opc = (opcode >> 2) & 0x3f;
		int mm  = (opcode >> 0) & 0x03;

		// fix-up so we can use our register array
		if (mm == BC) mm = PP;

		UINT8 o;
		UINT16 off, seg;

		switch (opc)
		{
		case 0x00: // control
			switch (brp)
			{
			case 0: nop(); break;
			case 1: invalid(opc); break;
			case 2: sintr(); break;
			case 3: xfer(); break;
			default: wid(BIT(brp, 1), BIT(brp, 0));
			}
			break;

		case 0x02: // lpdi
			off = imm16();
			seg = imm16();
			lpdi(brp, seg, off);
			break;

		case 0x08: // add(b)i r, i
			if (w) addi_ri(brp, imm16());
			else   addbi_ri(brp, imm8());
			break;

		case 0x0a: // and(b)i r, i
			if (w) andi_ri(brp, imm16());
			else   andbi_ri(brp, imm8());
			break;

		case 0x0c: // mov(b)i r, i
			if (w) movi_ri(brp, imm16());
			else   movbi_ri(brp, imm8());
			break;

		case 0x0f: // dec r
			dec_r(brp);
			break;

		case 0x12: // hlt
			if (BIT(brp, 0)) hlt();
			else             invalid(opc);
			break;

		case 0x22: // lpd
			o = offset(aa);
			lpd(brp, mm, o);
			break;

		case 0x28: // add(b) r, m
			if (w) add_rm(brp, mm, offset(aa));
			else   addb_rm(brp, mm, offset(aa));
			break;

		case 0x2a: // and(b) r, m
			if (w) and_rm(brp, mm, offset(aa));
			else   andb_rm(brp, mm, offset(aa));
			break;

		case 0x27: // call
			o = offset(aa);
			call(mm, displacement(wb), o);
			break;

		case 0x30: // add(b)i m, i
			o = offset(aa);
			if (w) addi_mi(mm, imm16(), o);
			else   addbi_mi(mm, imm8(), o);
			break;

		case 0x32: // and(b)i m, i
			o = offset(aa);
			if (w) andi_mi(mm, imm16(), o);
			else   andbi_mi(mm, imm8(), o);
			break;

		case 0x34: // add(b) m, r
			if (w) add_mr(mm, brp, offset(aa));
			else   addb_mr(mm, brp, offset(aa));
			break;

		case 0x36: // and(b) m, r
			if (w) and_mr(mm, brp, offset(aa));
			else   andb_mr(mm, brp, offset(aa));
			break;

		case 0x3b: // dec(b) m
			if (w) dec_m(mm, offset(aa));
			else   decb(mm, offset(aa));
			break;

		case 0x3e: // clr
			clr(mm, brp, offset(aa));
			break;

		default:
			invalid(opc);
		}

		m_icount++;
	}

	// nothing to do
	else
	{
		m_icount++;
	}

	return m_icount;
}

void i8089_channel::examine_ccw(UINT8 ccw)
{
	// priority and bus load limit, bit 7 and 5
	m_r[PSW].w = (m_r[PSW].w & 0x5f) | (ccw & 0xa0);

	// acknowledge interrupt
	if (BIT(ccw, 4))
	{
		m_write_sintr(0);
		m_r[PSW].w &= ~(1 << 5);
	}

	// interrupt enable
	if (BIT(ccw, 5))
	{
		if (BIT(ccw, 4))
			m_r[PSW].w &= ~(1 << 4);
		else
			m_r[PSW].w |= 1 << 4;
	}
}

void i8089_channel::attention()
{
	// examine control byte
	UINT8 ccw = m_iop->read_byte(m_r[CP].w);

	switch (ccw & 0x07)
	{
	// no channel command
	case 0:
		if (VERBOSE)
			logerror("%s('%s'): command received: update psw\n", shortname(), tag());

		examine_ccw(ccw);
		break;

	// start channel, tb in local space
	case 1:
		if (VERBOSE)
			logerror("%s('%s'): command received: start channel in local space\n", shortname(), tag());

		examine_ccw(ccw);

		lpd(PP, CP, 2);
		movp_pm(TP, PP);
		movbi_mi(CP, 0xff, 1);

		m_r[PSW].w |= 1 << 2;

		break;

	// reserved
	case 2:
		if (VERBOSE)
			logerror("%s('%s'): command received: invalid command 010\n", shortname(), tag());

		break;

	// start channel, tb in system space
	case 3:
		if (VERBOSE)
			logerror("%s('%s'): command received: start channel in system space\n", shortname(), tag());

		examine_ccw(ccw);

		lpd(PP, CP, 2);
		lpd(TP, PP);
		movbi_mi(CP, 0xff, 1);

		m_r[PSW].w |= 1 << 2;

		if (VERBOSE)
		{
			logerror("%s('%s'): ---- starting channel ----\n", shortname(), tag());
			logerror("%s('%s'): parameter block address: %06x\n", shortname(), tag(), m_r[PP].w);
			logerror("%s('%s'): task pointer: %06x\n", shortname(), tag(), m_r[TP].w);
		}

		break;

	case 4:
		if (VERBOSE)
			logerror("%s('%s'): command received: invalid command 100\n", shortname(), tag());

		break;

	// continue channel processing
	case 5:
		if (VERBOSE)
			logerror("%s('%s'): command received: continue channel processing\n", shortname(), tag());

		// restore task pointer and parameter block
		movp_pm(TP, PP);
		movb_rm(PSW, PP, 3);
		movbi_mi(CP, 0xff, 1);

		m_r[PSW].w |= 1 << 2;

		if (VERBOSE)
		{
			logerror("%s('%s'): ---- continuing channel ----\n", shortname(), tag());
			logerror("%s('%s'): task pointer: %06x\n", shortname(), tag(), m_r[TP].w);
		}

		break;

	// halt channel, save tp
	case 6:
		if (VERBOSE)
			logerror("%s('%s'): command received: halt channel and save tp\n", shortname(), tag());

		// save task pointer and psw to parameter block
		movp_mp(PP, TP);
		movb_mr(PP, PSW, 3);
		hlt();

		break;

	// halt channel, don't save tp
	case 7:
		if (VERBOSE)
			logerror("%s('%s'): command received: halt channel\n", shortname(), tag());

		hlt();

		break;
	}
}

WRITE_LINE_MEMBER( i8089_channel::ext_w )
{
	if (VERBOSE)
		logerror("%s('%s'): ext_w: %d\n", shortname(), tag(), state);
}

WRITE_LINE_MEMBER( i8089_channel::drq_w )
{
	if (VERBOSE)
		logerror("%s('%s'): ext_w: %d\n", shortname(), tag(), state);
}