summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/machine/mb8421.cpp
blob: a5b08f5ea90201360613e103ee2f9d728a953447 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
// license:BSD-3-Clause
// copyright-holders:hap,AJR
/**********************************************************************

    Fujitsu MB8421/22/31/32-90/-90L/-90LL/-12/-12L/-12LL
    CMOS 16K-bit (2KB) dual-port SRAM

    MB84x2 lacks interrupt pins, it's basically as simple as AM_RAM AM_SHARE("x")
    MB843x is same as MB842x, except that it supports slave mode for 16-bit or
    32-bit expansion. It makes sure there are no clashes with the _BUSY pin.

    IDT71321 is function compatible, but not pin compatible with MB8421

**********************************************************************/

#include "emu.h"
#include "machine/mb8421.h"


DEFINE_DEVICE_TYPE(MB8421, mb8421_device, "mb8421", "MB8421 8-bit Dual-Port SRAM with Interrupts")
DEFINE_DEVICE_TYPE(IDT71321, idt71321_device, "idt71321", "IDT71321 8-bit Dual-Port SRAM with Interrupts")
DEFINE_DEVICE_TYPE(MB8421_MB8431_16BIT, mb8421_mb8431_16_device, "mb8421_mb8431_16", "MB8421/MB8431 16-bit Dual-Port SRAM with Interrupts")

//-------------------------------------------------
//  mb8421_master_device - constructor
//-------------------------------------------------

mb8421_master_device::mb8421_master_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
	: device_t(mconfig, type, tag, owner, clock)
	, m_intl_callback(*this)
	, m_intr_callback(*this)
{
}

//-------------------------------------------------
//  mb8421_device - constructor
//-------------------------------------------------

mb8421_device::mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
	: mb8421_master_device(mconfig, MB8421, tag, owner, clock)
{
}

mb8421_device::mb8421_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
	: mb8421_master_device(mconfig, type, tag, owner, clock)
{
}

//-------------------------------------------------
//  idt71321_device - constructor
//-------------------------------------------------

idt71321_device::idt71321_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
	: mb8421_device(mconfig, IDT71321, tag, owner, clock)
{
}

//-------------------------------------------------
//  mb8421_mb8431_16_device - constructor
//-------------------------------------------------

mb8421_mb8431_16_device::mb8421_mb8431_16_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
	: mb8421_master_device(mconfig, MB8421_MB8431_16BIT, tag, owner, clock)
{
}

//-------------------------------------------------
//  device_resolve_objects - resolve objects that
//  may be needed for other devices to set
//  initial conditions at start time
//-------------------------------------------------

void mb8421_master_device::device_resolve_objects()
{
	// resolve callbacks
	m_intl_callback.resolve_safe();
	m_intr_callback.resolve_safe();
}

//-------------------------------------------------
//  device_start - device-specific startup
//-------------------------------------------------

void mb8421_device::device_start()
{
	m_ram = make_unique_clear<u8[]>(0x800);

	// state save
	save_pointer(NAME(m_ram), 0x800);
}

void mb8421_mb8431_16_device::device_start()
{
	m_ram = make_unique_clear<u16[]>(0x800);

	// state save
	save_pointer(NAME(m_ram), 0x800);
}

//-------------------------------------------------
//  device_reset - device-specific reset
//-------------------------------------------------

void mb8421_master_device::device_reset()
{
	m_intl_callback(CLEAR_LINE);
	m_intr_callback(CLEAR_LINE);
}

//-------------------------------------------------
//  update_intr - update interrupt lines upon
//  read or write accesses to special locations
//-------------------------------------------------

template<read_or_write row, bool is_right>
void mb8421_master_device::update_intr(offs_t offset)
{
	if (machine().side_effects_disabled())
		return;

	if (row == read_or_write::WRITE && offset == (is_right ? 0x7fe : 0x7ff))
		(is_right ? m_intl_callback : m_intr_callback)(ASSERT_LINE);
	else if (row == read_or_write::READ && offset == (is_right ? 0x7ff : 0x7fe))
		(is_right ? m_intr_callback : m_intl_callback)(CLEAR_LINE);
}

//-------------------------------------------------
//  left_w - write access for left-side bus
//  (write to 7FF asserts INTR)
//-------------------------------------------------

WRITE8_MEMBER(mb8421_device::left_w)
{
	offset &= 0x7ff;
	m_ram[offset] = data;
	update_intr<read_or_write::WRITE, false>(offset);
}

WRITE16_MEMBER(mb8421_mb8431_16_device::left_w)
{
	offset &= 0x7ff;
	COMBINE_DATA(&m_ram[offset]);
	update_intr<read_or_write::WRITE, false>(offset);
}

//-------------------------------------------------
//  left_r - read access for left-side bus
//  (read from 7FE acknowledges INTL)
//-------------------------------------------------

READ8_MEMBER(mb8421_device::left_r)
{
	offset &= 0x7ff;
	update_intr<read_or_write::READ, false>(offset);
	return m_ram[offset];
}

READ16_MEMBER(mb8421_mb8431_16_device::left_r)
{
	offset &= 0x7ff;
	update_intr<read_or_write::READ, false>(offset);
	return m_ram[offset];
}

//-------------------------------------------------
//  right_w - write access for right-side bus
//  (write to 7FE asserts INTL)
//-------------------------------------------------

WRITE8_MEMBER(mb8421_device::right_w)
{
	offset &= 0x7ff;
	m_ram[offset] = data;
	update_intr<read_or_write::WRITE, true>(offset);
}

WRITE16_MEMBER(mb8421_mb8431_16_device::right_w)
{
	offset &= 0x7ff;
	COMBINE_DATA(&m_ram[offset]);
	update_intr<read_or_write::WRITE, true>(offset);
}

//-------------------------------------------------
//  right_r - read access for right-side bus
//  (read from 7FF acknowledges INTR)
//-------------------------------------------------

READ8_MEMBER(mb8421_device::right_r)
{
	offset &= 0x7ff;
	update_intr<read_or_write::READ, true>(offset);
	return m_ram[offset];
}

READ16_MEMBER(mb8421_mb8431_16_device::right_r)
{
	offset &= 0x7ff;
	update_intr<read_or_write::READ, true>(offset);
	return m_ram[offset];
}