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// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/******************************************************************************
*
*   Sony PlayStation 2 IOP DMAC device skeleton
*
*   To Do:
*     Everything
*
*/

#ifndef MAME_MACHINE_IOPDMA_H
#define MAME_MACHINE_IOPDMA_H

#pragma once

#include "ps2sif.h"
#include "iopintc.h"
#include "iopsio2.h"
#include "sound/iopspu.h"

class iop_dma_device : public device_t, public device_execute_interface
{
public:
	template <typename T, typename U, typename V, typename W, typename X>
	iop_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&intc_tag, U &&ram_tag, V &&sif_tag, W &&spu_tag, X &&sio2_tag)
		: iop_dma_device(mconfig, tag, owner, clock)
	{
		m_intc.set_tag(std::forward<T>(intc_tag));
		m_ram.set_tag(std::forward<U>(ram_tag));
		m_sif.set_tag(std::forward<V>(sif_tag));
		m_spu.set_tag(std::forward<W>(spu_tag));
		m_sio2.set_tag(std::forward<X>(sio2_tag));
	}

	iop_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
	virtual ~iop_dma_device() override;

	DECLARE_READ32_MEMBER(bank0_r);
	DECLARE_WRITE32_MEMBER(bank0_w);
	DECLARE_READ32_MEMBER(bank1_r);
	DECLARE_WRITE32_MEMBER(bank1_w);

	enum channel_type : uint32_t
	{
		MDEC_IN = 0,
		MDEC_OUT,
		GPU,
		CDVD,
		SPU_BANK1,
		PIO,
		OTC,
		UNUSED_BANK0,
		SPU_BANK2,
		UNKNOWN0,
		SIF0,
		SIF1,
		SIO2_IN,
		SIO2_OUT,
		UNKNOWN1,
		UNUSED_BANK1
	};

protected:
	struct intctrl_t
	{
		uint8_t m_mask;
		uint8_t m_status;
		bool m_enabled;
	};

	class channel_t
	{
		friend class iop_dma_device;

	public:
		channel_t()
			: m_priority(0)
			, m_enabled(false)
			, m_busy(false)
			, m_end(false)
			, m_addr(0)
			, m_ctrl(0)
			, m_tag_addr(0)
			, m_block(0)
			, m_block_count(0)
			, m_word_count(0)
			, m_count(0)
		{
		}

		void set_pri_ctrl(uint32_t pri_ctrl);
		void set_addr(uint32_t addr) { m_addr = addr; }
		void set_block(uint32_t block, uint32_t mem_mask);
		void set_block_count(uint32_t block_count);
		void set_word_count(uint32_t word_count);
		void set_count(uint32_t count) { m_count = count; }
		void set_ctrl(uint32_t ctrl);
		void set_tag_addr(uint32_t tag_addr) { m_tag_addr = tag_addr; }

		bool enabled() const { return m_enabled; }
		bool end() const { return m_end; }
		bool busy() const { return m_busy; }

		uint32_t addr() const { return m_addr; }
		uint32_t ctrl() const { return m_ctrl; }
		uint32_t tag_addr() const { return m_tag_addr; }

		uint32_t block() const { return m_block; }
		uint32_t block_count() const { return m_block_count; }
		uint32_t word_count() const { return m_word_count; }
		uint32_t count() const { return m_count; }

	protected:
		uint8_t m_priority;
		bool m_enabled;
		bool m_busy;
		bool m_end;

		uint32_t m_addr;
		uint32_t m_ctrl;
		uint32_t m_tag_addr;

		uint32_t m_block;
		uint32_t m_block_count;
		uint32_t m_word_count;
		uint32_t m_count;
	};

	virtual void device_start() override;
	virtual void device_reset() override;
	virtual void execute_run() override;

	void set_dpcr(uint32_t data, uint32_t index);
	void set_dicr(uint32_t data, uint32_t index);
	void update_interrupts();

	void transfer_sif0(uint32_t chan);
	void transfer_sif1(uint32_t chan);
	void transfer_spu(uint32_t chan);
	void transfer_to_sio2(uint32_t chan);
	void transfer_from_sio2(uint32_t chan);
	void transfer_finish(uint32_t chan);

	required_device<iop_intc_device> m_intc;
	required_shared_ptr<uint32_t> m_ram;
	required_device<ps2_sif_device> m_sif;
	required_device<iop_spu_device> m_spu;
	required_device<iop_sio2_device> m_sio2;

	int m_icount;

	uint32_t m_dpcr[2];
	uint32_t m_dicr[2];
	channel_t m_channels[16];
	intctrl_t m_int_ctrl[2];

	uint32_t m_running_mask;
	uint32_t m_last_serviced;
};

DECLARE_DEVICE_TYPE(SONYIOP_DMA, iop_dma_device)

#endif // MAME_MACHINE_IOPDMA_H
span class="w"> 0x000000, 0x000000); voodoo_pci_device::device_start(); add_map(16 * 1024 * 1024, M_MEM | M_PREF, *m_voodoo, FUNC(voodoo_1_device::core_map)); bank_infos[0].adr = 0xff000000; command = 0; command_mask = 2; status = 0; // no max_gnt / max_lat (hardwired to 0, cannot bus master) intr_line = 5; // INTA# intr_pin = 1; } void voodoo_2_pci_device::device_start() { // TODO: straps class code from fb_addr_a[6] (if =1 then 0x040000) set_ids(0x121a0002, 0x02, 0x038000, 0x000000); voodoo_pci_device::device_start(); add_map(16 * 1024 * 1024, M_MEM | M_PREF, *m_voodoo, FUNC(voodoo_2_device::core_map)); bank_infos[0].adr = 0xff000000; command = 0; command_mask = 2; // FIXME: straps from fb_addr_b[1] (AGP) / fb_addr_a[8] // (fast back-to-back & fast/medium DEVSEL#) //status = 0x0280; status = 0; // reported with default 0 intr_line = 0; // INTA# intr_pin = 1; } void voodoo_banshee_pci_device::device_start() { // FIXME: proper PCI values (check manual) set_ids(0x121a0003, 0x02, 0x030000, 0x000000); voodoo_pci_device::device_start(); add_map(32 * 1024 * 1024, M_MEM, *m_voodoo, FUNC(voodoo_banshee_device::core_map)); add_map(32 * 1024 * 1024, M_MEM, *m_voodoo, FUNC(voodoo_banshee_device::lfb_map)); add_map(256, M_IO, *m_voodoo, FUNC(voodoo_banshee_device::io_map)); bank_infos[0].adr = 0xf8000000; bank_infos[1].adr = 0xf8000008; bank_infos[2].adr = 0xfffffff0; } void voodoo_3_pci_device::device_start() { // FIXME: proper PCI values (check manual) set_ids(0x121a0005, 0x02, 0x030000, 0x000000); voodoo_pci_device::device_start(); // need to downcast to voodoo_banshee_device because the map functions are shared // this will cleaner when the PCI interface is implemented as a mix-in auto &banshee = static_cast<voodoo_banshee_device &>(*m_voodoo); add_map(32 * 1024 * 1024, M_MEM, banshee, FUNC(voodoo_banshee_device::core_map)); add_map(32 * 1024 * 1024, M_MEM, banshee, FUNC(voodoo_banshee_device::lfb_map)); add_map(256, M_IO, banshee, FUNC(voodoo_banshee_device::io_map)); bank_infos[0].adr = 0xf8000000; bank_infos[1].adr = 0xf8000008; bank_infos[2].adr = 0xfffffff0; } void voodoo_pci_device::postload() { remap_cb(); } void voodoo_pci_device::device_reset() { memset(m_pcictrl_reg, 0, sizeof(m_pcictrl_reg)); pci_device::device_reset(); } void voodoo_pci_device::map_extra(u64 memory_window_start, u64 memory_window_end, u64 memory_offset, address_space *memory_space, u64 io_window_start, u64 io_window_end, u64 io_offset, address_space *io_space) { logerror("%s: map_extra\n", this->tag()); } void voodoo_banshee_pci_device::map_extra(u64 memory_window_start, u64 memory_window_end, u64 memory_offset, address_space *memory_space, u64 io_window_start, u64 io_window_end, u64 io_offset, address_space *io_space) { logerror("%s: map_extra\n", this->tag()); // Map VGA legacy access // Should really be dependent on voodoo VGAINIT0 bit 8 and IO base + 0xc3 bit 0 u64 start = io_offset + 0x3b0; u64 end = io_offset + 0x3df; io_space->install_readwrite_handler(start, end, read32s_delegate(*this, FUNC(voodoo_pci_device::vga_r)), write32s_delegate(*this, FUNC(voodoo_pci_device::vga_w))); logerror("%s: map %s at %0*x-%0*x\n", this->tag(), "vga_r/w", 4, u32(start), 4, u32(end)); } void voodoo_3_pci_device::map_extra(u64 memory_window_start, u64 memory_window_end, u64 memory_offset, address_space *memory_space, u64 io_window_start, u64 io_window_end, u64 io_offset, address_space *io_space) { logerror("%s: map_extra\n", this->tag()); // Map VGA legacy access // Should really be dependent on voodoo VGAINIT0 bit 8 and IO base + 0xc3 bit 0 u64 start = io_offset + 0x3b0; u64 end = io_offset + 0x3df; io_space->install_readwrite_handler(start, end, read32s_delegate(*this, FUNC(voodoo_pci_device::vga_r)), write32s_delegate(*this, FUNC(voodoo_pci_device::vga_w))); logerror("%s: map %s at %0*x-%0*x\n", this->tag(), "vga_r/w", 4, u32(start), 4, u32(end)); } u32 voodoo_pci_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) { return m_generic_voodoo->update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED; } // PCI bus control u32 voodoo_pci_device::pcictrl_r(offs_t offset, u32 mem_mask) { u32 result = m_pcictrl_reg[offset]; // The address map starts at 0x40 switch (offset + 0x40 / 4) { case 0x40/4: { // V1: initEnable: 11:0 // V2: initEnable: Fab ID=19:16, Graphics Rev=15:12 // Banshee/V3: fabID: ScratchPad=31:4 fabID=3:0 auto model = m_generic_voodoo->model(); if (model == voodoo::voodoo_model::VOODOO_2) result = (result & ~0xff000) | 0x00044000; // Vegas driver needs this value else if (model >= voodoo::voodoo_model::VOODOO_BANSHEE) result = (result & ~0xf) | 0x1; break; } case 0x54/4: // V2: SiProcess Register: Osc Force On, Osc Ring Sel, Osc Count Reset, 12 bit PCI Counter, 16 bit Oscillator Counter // V3: AGP Capability Register: 8 bit 0, 4 bit AGP Major, 4 bit AGP Minor, 8 bit Next Ptr, 8 bit Capability ID // Tenthdeg (vegas) checks this result = 0x00006002; break; } if (1) logerror("%s:voodoo_pci_device pcictrl_r from offset %02X = %08X & %08X\n", machine().describe_context(), offset*4 + 0x40, result, mem_mask); return result; } void voodoo_pci_device::pcictrl_w(offs_t offset, u32 data, u32 mem_mask) { COMBINE_DATA(&m_pcictrl_reg[offset]); // The address map starts at 0x40 switch (offset + 0x40 / 4) { case 0x40/4: // HW initEnable m_generic_voodoo->set_init_enable(data); logerror("%s:voodoo_pci_device pcictrl_w (initEnable) offset %02X = %08X & %08X\n", machine().describe_context(), offset * 4 + 0x40, data, mem_mask); break; default: logerror("%s:voodoo_pci_device pcictrl_w to offset %02X = %08X & %08X\n", machine().describe_context(), offset*4 + 0x40, data, mem_mask); break; } } // VGA legacy accesses u32 voodoo_pci_device::vga_r(offs_t offset, u32 mem_mask) { // map to I/O space at offset 0xb0 return m_generic_voodoo->read(0xb0/4 + offset, mem_mask); } void voodoo_pci_device::vga_w(offs_t offset, u32 data, u32 mem_mask) { // map to I/O space at offset 0xb0 m_generic_voodoo->write(0xb0/4 + offset, data, mem_mask); } // x86 cards, same with additional BIOS ROM voodoo_banshee_x86_pci_device::voodoo_banshee_x86_pci_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : voodoo_banshee_pci_device(mconfig, VOODOO_BANSHEE_X86_PCI, tag, owner, clock) , m_vga_rom(*this, "vga_rom") { } void voodoo_banshee_x86_pci_device::device_start() { voodoo_banshee_pci_device::device_start(); add_rom((u8 *)m_vga_rom->base(), 0x8000); expansion_rom_base = 0xc0000; } ROM_START( voodoo_banshee ) ROM_REGION32_LE( 0x8000, "vga_rom", ROMREGION_ERASEFF ) ROM_SYSTEM_BIOS( 0, "gainward", "Gainward Dragon 4000" ) ROMX_LOAD( "gainward.bin", 0x000000, 0x008000, CRC(a53df538) SHA1(679f94619eac11c59effb89fe44bb74f589e3050), ROM_BIOS(0) ) ROM_IGNORE( 0x8000 ) ROM_SYSTEM_BIOS( 1, "atrend", "A-Trend Helios 3D" ) ROMX_LOAD( "a-trend.vbi", 0x000000, 0x008000, CRC(117a9e6f) SHA1(48b0bc08d142be3aa0d937ee56afd299b3b20386), ROM_BIOS(1) ) ROM_END const tiny_rom_entry *voodoo_banshee_x86_pci_device::device_rom_region() const { return ROM_NAME(voodoo_banshee); }