summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/unsp/unsp_exxx.cpp
blob: 07e8f056984cf0b0cb136c79ecb262f889058e1c (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
// license:GPL-2.0+
// copyright-holders:Segher Boessenkool, Ryan Holtz, David Haywood

#include "emu.h"
#include "unsp.h"
#include "unspfe.h"

#include "debugger.h"

#include "unspdasm.h"

#define LOG_UNSP_MULS            (1U << 1)
#define LOG_UNSP_SHIFTS          (1U << 2)

#define VERBOSE             (LOG_UNSP_SHIFTS)

#include "logmacro.h"


void unsp_device::execute_exxx_group(uint16_t op)
{
	// several exxx opcodes have already been decoded as jumps by the time we get here
	//logerror("<DUNNO>\n");
	unimplemented_opcode(op);
	return;
}

void unsp_12_device::execute_exxx_group(uint16_t op)
{
	// several exxx opcodes have already been decoded as jumps by the time we get here

	//   Register BITOP  BITOP Rd,Rs             1 1 1 0   r r r 0   0 0 b b   0 r r r
	//   Register BITOP  BITOP Rd,offset         1 1 1 0   r r r 0   0 1 b b   o o o o
	//   Memory BITOP    BITOP [Rd], offset      1 1 1 0   r r r 1   1 0 b b   o o o o
	//   Memory BITOP    BITOP ds:[Rd], offset   1 1 1 0   r r r 1   1 1 b b   o o o o
	//   Memory BITOP    BITOP [Rd], Rs          1 1 1 0   r r r 1   0 0 b b   0 r r r
	//   Memory BITOP    BITOP ds:[Rd], Rs       1 1 1 0   r r r 1   0 1 b b   0 r r r

	if (((op & 0xf1c8) == 0xe000))
	{
		// Register BITOP  BITOP Rd,Rs
		uint8_t bitop = (op & 0x0030) >> 4;
		uint8_t rd =    (op & 0x0e00) >> 9;
		uint8_t rs =    (op & 0x0007) >> 0;
		logerror("%s %s,%s\n", bitops[bitop], regs[rd], regs[rs]);
		unimplemented_opcode(op);
		return;
	}
	else if (((op & 0xf1c0) == 0xe040))
	{
		// Register BITOP  BITOP Rd,offset
		const uint8_t bitop =  (op & 0x0030) >> 4;
		const uint8_t rd =     (op & 0x0e00) >> 9;
		const uint8_t offset = (op & 0x000f) >> 0;
		m_core->m_r[REG_SR] &= ~UNSP_Z;
		m_core->m_r[REG_SR] |= BIT(m_core->m_r[rd], offset) ? 0 : UNSP_Z;

		switch (bitop)
		{
		case 0x00: // tstb
			return;

		case 0x01: // setb
			m_core->m_r[rd] |= (1 << offset);
			return;

		case 0x02: // clrb
			m_core->m_r[rd] &= ~(1 << offset);
			return;

		case 0x03:
			m_core->m_r[rd] ^= (1 << offset);
			return;
		}
		return;
	}
	else if (((op & 0xf1c0) == 0xe180))
	{
		// Memory BITOP    BITOP [Rd], offset
		const uint8_t bitop =  (op & 0x0030) >> 4;
		const uint8_t rd =     (op & 0x0e00) >> 9;
		const uint8_t offset = (op & 0x000f) >> 0;
		const uint16_t addr =  m_core->m_r[rd];
		const uint16_t orig =  read16(addr);
		m_core->m_r[REG_SR] &= ~UNSP_Z;
		m_core->m_r[REG_SR] |= BIT(m_core->m_r[rd], offset) ? 0 : UNSP_Z;

		switch (bitop)
		{
		case 0x00: // tstb
			return;

		case 0x01: // setb
			write16(addr, orig | (1 << offset));
			return;

		case 0x02: // clrb
			write16(addr, orig & ~(1 << offset));
			return;

		case 0x03:
			write16(addr, orig ^ (1 << offset));
			return;
		}
		return;
	}
	else if (((op & 0xf1c0) == 0xe1c0))
	{
		// Memory BITOP    BITOP ds:[Rd], offset
		const uint8_t bitop =  (op & 0x0030) >> 4;
		const uint8_t rd =     (op & 0x0e00) >> 9;
		const uint8_t offset = (op & 0x000f) >> 0;
		const uint32_t addr =  m_core->m_r[rd] | (get_ds() << 16);
		const uint16_t orig =  read16(addr);
		m_core->m_r[REG_SR] &= ~UNSP_Z;
		m_core->m_r[REG_SR] |= BIT(m_core->m_r[rd], offset) ? 0 : UNSP_Z;

		switch (bitop)
		{
		case 0x00: // tstb
			return;

		case 0x01: // setb
			write16(addr, orig | (1 << offset));
			return;

		case 0x02: // clrb
			write16(addr, orig & ~(1 << offset));
			return;

		case 0x03:
			write16(addr, orig ^ (1 << offset));
			return;
		}
		return;
	}
	else if (((op & 0xf1c8) == 0xe100))
	{
		// Memory BITOP    BITOP [Rd], Rs
		const uint8_t bitop =  (op & 0x0030) >> 4;
		const uint8_t rd =     (op & 0x0e00) >> 9;
		const uint8_t rs =     (op & 0x0007) >> 0;
		const uint8_t offset = (1 << m_core->m_r[rs]);
		const uint16_t addr =  m_core->m_r[rd];
		const uint16_t orig =  read16(addr);
		m_core->m_r[REG_SR] &= ~UNSP_Z;
		m_core->m_r[REG_SR] |= BIT(m_core->m_r[rd], offset) ? 0 : UNSP_Z;

		switch (bitop)
		{
		case 0x00: // tstb
			return;

		case 0x01: // setb
			write16(addr, orig | (1 << offset));
			return;

		case 0x02: // clrb
			write16(addr, orig & ~(1 << offset));
			return;

		case 0x03:
			write16(addr, orig ^ (1 << offset));
			return;
		}
		return;
	}
	else if (((op & 0xf1c8) == 0xe140))
	{
		// Memory BITOP    BITOP ds:[Rd], Rs
		const uint8_t bitop =  (op & 0x0030) >> 4;
		const uint8_t rd =     (op & 0x0e00) >> 9;
		const uint8_t rs =     (op & 0x0007) >> 0;
		const uint8_t offset = (1 << m_core->m_r[rs]);
		const uint32_t addr =  m_core->m_r[rd] | (get_ds() << 16);
		const uint16_t orig =  read16(addr);
		m_core->m_r[REG_SR] &= ~UNSP_Z;
		m_core->m_r[REG_SR] |= BIT(m_core->m_r[rd], offset) ? 0 : UNSP_Z;

		switch (bitop)
		{
		case 0x00: // tstb
			return;

		case 0x01: // setb
			write16(addr, orig | (1 << offset));
			return;

		case 0x02: // clrb
			write16(addr, orig & ~(1 << offset));
			return;

		case 0x03:
			write16(addr, orig ^ (1 << offset));
			return;
		}
		return;
	}
	else if (((op & 0xf0f8) == 0xe008))
	{
		// MUL operations
		// MUL      1 1 1 0*  r r r S*  0 0 0 0   1 r r r     (* = sign bit, fixed here)
		/*
		print_mul(stream, op); // MUL uu or MUL su
		*/

		if (op & 0x0100)
		{
			// MUL su ( unsigned * signed )
			const uint16_t opa = (op >> 9) & 7;
			const uint16_t opb = op & 7;
			m_core->m_icount -= 12;

			LOGMASKED(LOG_UNSP_MULS, "%s: MUL su with %04x (signed) * %04x (unsigned) (fra:%d) :\n", machine().describe_context(), m_core->m_r[opa], m_core->m_r[opb], m_core->m_fra);

			uint32_t lres = m_core->m_r[opa] * m_core->m_r[opb];
			if (m_core->m_r[opa] & 0x8000)
			{
				lres -= m_core->m_r[opb] << 16;
			}
			m_core->m_r[REG_R4] = lres >> 16;
			m_core->m_r[REG_R3] = (uint16_t)lres;

			LOGMASKED(LOG_UNSP_MULS, "result was : %08x\n", lres);

			return;
		}
		else
		{
			// MUL uu (unsigned * unsigned)
			uint32_t lres = 0;
			const uint16_t opa = (op >> 9) & 7;
			const uint16_t opb = op & 7;

			m_core->m_icount -= 12; // unknown
			lres = m_core->m_r[opa] * m_core->m_r[opb];
			m_core->m_r[REG_R4] = lres >> 16;
			m_core->m_r[REG_R3] = (uint16_t)lres;
			return;
		}
		return;
	}
	else if (((op & 0xf080) == 0xe080))
	{
		// MULS     1 1 1 0*  r r r S*  1 s s s   s r r r    (* = sign bit, fixed here)
		/*
		// MULS uu or MULS su (invalid?)
		print_muls(stream, op);
		*/
		LOGMASKED(LOG_UNSP_MULS, "MULS uu or su\n");
		unimplemented_opcode(op);
		return;
	}
	else if (((op & 0xf188) == 0xe108))
	{
		// 16 bit Shift    1 1 1 0   r r r 1   0 l l l   1 r r r
		uint8_t rd =    (op & 0x0e00) >> 9;
		uint8_t shift = (op & 0x0070) >> 4;
		uint8_t rs =    (op & 0x0007) >> 0;

		switch (shift)
		{
		case 0x00:
		{
			LOGMASKED(LOG_UNSP_SHIFTS, "%s = %s asr %s\n", regs[rd], regs[rd], regs[rs]);

			uint32_t rdval = (uint16_t)(m_core->m_r[rd]);
			int shift = (m_core->m_r[rs] & 0x01f);
			if (shift == 0)
				return;

			uint32_t res;
			if (BIT(rd, (32 - shift)))
			{
				if (shift >= 16)
				{
					res = 0x0000ffff;
				}
				else
				{
					res = (rdval >> shift) | (uint16_t)(0xffff0000 >> shift);
				}
			}
			else
			{
				if (shift >= 16)
				{
					res = 0;
				}
				else
				{
					res = rdval >> shift;
				}
			}

			LOGMASKED(LOG_UNSP_SHIFTS, "result: %08x\n", res);
			m_core->m_r[rd] = res;
			return;
		}

		case 0x01: // jak_car2 on starting a game
		{
			LOGMASKED(LOG_UNSP_SHIFTS, "%s = %s asror %s (%04x %04x)\n", regs[rd], regs[rd], regs[rs], m_core->m_r[rd], m_core->m_r[rs]);

			const int32_t rdval = (int32_t)(m_core->m_r[rd] << 16);
			const int shift = (m_core->m_r[rs] & 0x01f);
			const uint32_t res = rdval >> shift;
			m_core->m_r[REG_R3] |= (uint16_t)res;
			m_core->m_r[REG_R4] |= (uint16_t)(res >> 16);
			LOGMASKED(LOG_UNSP_SHIFTS, "result: %04x%04x\n", m_core->m_r[REG_R4], m_core->m_r[REG_R3]);
			return;
		}

		case 0x02:
		{
			LOGMASKED(LOG_UNSP_SHIFTS, "pc:%06x: %s = %s lsl %s (%04x %04x)\n", UNSP_LPC, regs[rd], regs[rd], regs[rs], m_core->m_r[rd], m_core->m_r[rs]);
			const uint32_t rdval = (uint16_t)(m_core->m_r[rd]);
			const int shift = (m_core->m_r[rs] & 0x01f);
			const uint32_t res = (uint16_t)(rdval << shift);
			LOGMASKED(LOG_UNSP_SHIFTS, "result: %08x\n", res);
			m_core->m_r[rd] = res;
			return;
		}

		case 0x03:
		{
			// wrlshunt uses this
			LOGMASKED(LOG_UNSP_SHIFTS, "pc:%06x: %s = %s lslor %s  (%04x %04x)\n", UNSP_LPC, regs[rd], regs[rd], regs[rs], m_core->m_r[rd], m_core->m_r[rs]);

			const uint32_t rdval = m_core->m_r[rd];
			const int shift = (m_core->m_r[rs] & 0x01f);
			const uint32_t res = rdval << shift;
			m_core->m_r[REG_R3] = (uint16_t)res;
			m_core->m_r[REG_R4] |= (uint16_t)(res >> 16);
			LOGMASKED(LOG_UNSP_SHIFTS, "result: %04x%04x\n", m_core->m_r[REG_R4], m_core->m_r[REG_R3]);
			return;
		}

		case 0x04:
		{
			// smartfp loops increasing shift by 4 up to values of 28
			LOGMASKED(LOG_UNSP_SHIFTS, "pc:%06x: %s = %s lsr %s  (%04x %04x)\n", UNSP_LPC, regs[rd], regs[rd], regs[rs], m_core->m_r[rd], m_core->m_r[rs]);

			const uint32_t rdval = (uint16_t)(m_core->m_r[rd]);
			const int shift = (m_core->m_r[rs] & 0x01f);
			const uint32_t res = (uint16_t)(rdval >> shift);
			LOGMASKED(LOG_UNSP_SHIFTS, "result: %08x\n", res);
			m_core->m_r[rd] = res;
			return;
		}

		case 0x05:
		{
			LOGMASKED(LOG_UNSP_SHIFTS, "pc:%06x: %s = %s lsror %s  (%04x %04x)\n", UNSP_LPC, regs[rd], regs[rd], regs[rs], m_core->m_r[rd], m_core->m_r[rs]);
			const uint32_t rdval = m_core->m_r[rd] << 16;
			const int shift = (m_core->m_r[rs] & 0x01f);
			const uint32_t res = rdval >> shift;
			m_core->m_r[REG_R3] |= (uint16_t)res;
			m_core->m_r[REG_R4] = (uint16_t)(res >> 16);
			LOGMASKED(LOG_UNSP_SHIFTS, "result: %04x%04x\n", m_core->m_r[REG_R4], m_core->m_r[REG_R3]);
			return;
		}

		case 0x06:
			LOGMASKED(LOG_UNSP_SHIFTS, "%s = %s rol %s\n", regs[rd], regs[rd], regs[rs]);
			unimplemented_opcode(op);
			return;

		case 0x07:
			LOGMASKED(LOG_UNSP_SHIFTS, "%s = %s ror %s\n", regs[rd], regs[rd], regs[rs]);
			unimplemented_opcode(op);
			return;
		}
	}

	logerror("<DUNNO>\n");
	unimplemented_opcode(op);
	return;
}